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- `timescale 1ns/1ps
- module dct(clk, rst, in, out);
- parameter g_vec_size = 8;
- parameter g_data_width = 16;
- input clk;
- input rst;
- input [g_vec_size*g_data_width-1:0] in;
- output [g_vec_size*g_data_width-1:0] out;
- wire [g_data_width-1:0] in_vec[0:g_vec_size-1];
- wire [g_data_width-1:0] out_vec[0:g_vec_size-1];
- reg [g_data_width-1:0] matrix[0:g_vec_size-1][0:g_vec_size-1];
- reg [g_data_width-1:0] out_reg[0:g_vec_size-1];
- initial begin
- matrix[0][0] = 23170;
- matrix[0][1] = 23170;
- matrix[0][2] = 23170;
- matrix[0][3] = 23170;
- matrix[0][4] = 23170;
- matrix[0][5] = 23170;
- matrix[0][6] = 23170;
- matrix[0][7] = 23170;
- matrix[1][0] = 32138;
- matrix[1][1] = 27245;
- matrix[1][2] = 18204;
- matrix[1][3] = 6392;
- matrix[1][4] = -6392;
- matrix[1][5] = -18204;
- matrix[1][6] = -27245;
- matrix[1][7] = -32138;
- matrix[2][0] = 30273;
- matrix[2][1] = 12539;
- matrix[2][2] = -12539;
- matrix[2][3] = -30273;
- matrix[2][4] = -30273;
- matrix[2][5] = -12539;
- matrix[2][6] = -12539;
- matrix[2][7] = 30273;
- matrix[3][0] = 27245;
- matrix[3][1] = -6392;
- matrix[3][2] = -32138;
- matrix[3][3] = -18204;
- matrix[3][4] = 18204;
- matrix[3][5] = -32138;
- matrix[3][6] = 6392;
- matrix[3][7] = -27245;
- matrix[4][0] = 23170;
- matrix[4][1] = -23170;
- matrix[4][2] = -23170;
- matrix[4][3] = 23170;
- matrix[4][4] = 23170;
- matrix[4][5] = -23170;
- matrix[4][6] = -23170;
- matrix[4][7] = 23170;
- matrix[5][0] = 18204;
- matrix[5][1] = -32138;
- matrix[5][2] = 6392;
- matrix[5][3] = 27245;
- matrix[5][4] = -27245;
- matrix[5][5] = -6392;
- matrix[5][6] = 32138;
- matrix[5][7] = -18204;
- matrix[6][0] = 12539;
- matrix[6][1] = -30273;
- matrix[6][2] = 30273;
- matrix[6][3] = -12539;
- matrix[6][4] = -12539;
- matrix[6][5] = 30273;
- matrix[6][6] = -30273;
- matrix[6][7] = 12539;
- matrix[7][0] = 6392;
- matrix[7][1] = -18204;
- matrix[7][2] = 27245;
- matrix[7][3] = -32138;
- matrix[7][4] = 32138;
- matrix[7][5] = -27245;
- matrix[7][6] = 18204;
- matrix[7][7] = -6392;
- end
- genvar g;
- generate
- for (g = 0; g < g_vec_size; g = g + 1) begin
- assign in_vec[g] = in[g_data_width * (g + 1) - 1 : g_data_width * g];
- assign out[g_data_width * (g + 1) - 1 : g_data_width * g] = out_vec[g];
- assign out_vec[g] = out_reg[g];
- end
- endgenerate
- integer i;
- integer j;
- always @(posedge clk or posedge rst)
- begin
- if (rst == 1)
- for (i = 0; i < g_vec_size; i = i + 1) begin
- out_reg[i] = 0;
- end
- else
- for (i = 0; i < 8; i = i + 1) begin
- for (j = 0; j < 8; j = j + 1) begin
- out_reg[i] = out_reg[i] + matrix[i][j] * in_vec[j];
- end
- end
- end
- endmodule
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