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  1. /dts-v1/;
  2.  
  3. /memreserve/ 0x0000000040020000 0x0000000000000800;
  4. /memreserve/ 0x0000000048000000 0x0000000001000000;
  5. /memreserve/ 0x0000000048100000 0x0000000000004000;
  6. /memreserve/ 0x0000000048104000 0x0000000000001000;
  7. /memreserve/ 0x0000000048105000 0x0000000000001000;
  8. / {
  9. model = "sun50iw6";
  10. compatible = "arm,sun50iw6p1";
  11. interrupt-parent = <0x1>;
  12. #address-cells = <0x2>;
  13. #size-cells = <0x2>;
  14.  
  15. clocks {
  16. compatible = "allwinner,sunxi-clk-init";
  17. device_type = "clocks";
  18. #address-cells = <0x2>;
  19. #size-cells = <0x2>;
  20. ranges;
  21. reg = <0x0 0x3001000 0x0 0x1000 0x0 0x7010000 0x0 0x400 0x0 0x7000000 0x0 0x4>;
  22.  
  23. losc {
  24. #clock-cells = <0x0>;
  25. compatible = "allwinner,fixed-clock";
  26. clock-frequency = <0x8000>;
  27. clock-output-names = "losc";
  28. linux,phandle = <0xd>;
  29. phandle = <0xd>;
  30. };
  31.  
  32. iosc {
  33. #clock-cells = <0x0>;
  34. compatible = "allwinner,fixed-clock";
  35. clock-frequency = <0xf42400>;
  36. clock-output-names = "iosc";
  37. linux,phandle = <0xe>;
  38. phandle = <0xe>;
  39. };
  40.  
  41. hosc {
  42. #clock-cells = <0x0>;
  43. compatible = "allwinner,fixed-clock";
  44. clock-frequency = <0x16e3600>;
  45. clock-output-names = "hosc";
  46. linux,phandle = <0x7>;
  47. phandle = <0x7>;
  48. };
  49.  
  50. osc48m {
  51. #clock-cells = <0x0>;
  52. compatible = "allwinner,fixed-clock";
  53. clock-frequency = <0x2dc6c00>;
  54. clock-output-names = "osc48m";
  55. linux,phandle = <0x8>;
  56. phandle = <0x8>;
  57. };
  58.  
  59. pll_cpu {
  60. #clock-cells = <0x0>;
  61. compatible = "allwinner,sunxi-pll-clock";
  62. lock-mode = "new";
  63. clock-output-names = "pll_cpu";
  64. };
  65.  
  66. pll_ddr0 {
  67. #clock-cells = <0x0>;
  68. compatible = "allwinner,sunxi-pll-clock";
  69. lock-mode = "new";
  70. clock-output-names = "pll_ddr0";
  71. linux,phandle = <0xd6>;
  72. phandle = <0xd6>;
  73. };
  74.  
  75. pll_periph0 {
  76. #clock-cells = <0x0>;
  77. compatible = "allwinner,sunxi-pll-clock";
  78. assigned-clock-rates = <0x23c34600>;
  79. lock-mode = "new";
  80. clock-output-names = "pll_periph0";
  81. linux,phandle = <0x2>;
  82. phandle = <0x2>;
  83. };
  84.  
  85. pll_periph1 {
  86. #clock-cells = <0x0>;
  87. compatible = "allwinner,sunxi-pll-clock";
  88. assigned-clock-rates = <0x23c34600>;
  89. lock-mode = "new";
  90. clock-output-names = "pll_periph1";
  91. linux,phandle = <0x3>;
  92. phandle = <0x3>;
  93. };
  94.  
  95. pll_gpu {
  96. #clock-cells = <0x0>;
  97. compatible = "allwinner,sunxi-pll-clock";
  98. lock-mode = "new";
  99. clock-output-names = "pll_gpu";
  100. linux,phandle = <0xd8>;
  101. phandle = <0xd8>;
  102. };
  103.  
  104. pll_video0 {
  105. #clock-cells = <0x0>;
  106. compatible = "allwinner,sunxi-pll-clock";
  107. lock-mode = "new";
  108. clock-output-names = "pll_video0";
  109. linux,phandle = <0x5>;
  110. phandle = <0x5>;
  111. };
  112.  
  113. pll_video1 {
  114. #clock-cells = <0x0>;
  115. compatible = "allwinner,sunxi-pll-clock";
  116. lock-mode = "new";
  117. assigned-clock-rates = <0x2367b880>;
  118. clock-output-names = "pll_video1";
  119. linux,phandle = <0x6>;
  120. phandle = <0x6>;
  121. };
  122.  
  123. pll_ve {
  124. #clock-cells = <0x0>;
  125. compatible = "allwinner,sunxi-pll-clock";
  126. device_type = "clk_pll_ve";
  127. lock-mode = "new";
  128. clock-output-names = "pll_ve";
  129. linux,phandle = <0x17>;
  130. phandle = <0x17>;
  131. };
  132.  
  133. pll_de {
  134. #clock-cells = <0x0>;
  135. compatible = "allwinner,sunxi-pll-clock";
  136. assigned-clock-rates = <0x297c1e00>;
  137. lock-mode = "new";
  138. clock-output-names = "pll_de";
  139. linux,phandle = <0x9>;
  140. phandle = <0x9>;
  141. };
  142.  
  143. pll_hsic {
  144. #clock-cells = <0x0>;
  145. compatible = "allwinner,sunxi-pll-clock";
  146. lock-mode = "new";
  147. clock-output-names = "pll_hsic";
  148. linux,phandle = <0x3f>;
  149. phandle = <0x3f>;
  150. };
  151.  
  152. pll_audio {
  153. #clock-cells = <0x0>;
  154. compatible = "allwinner,sunxi-pll-clock";
  155. lock-mode = "new";
  156. clock-output-names = "pll_audio";
  157. linux,phandle = <0x4>;
  158. phandle = <0x4>;
  159. };
  160.  
  161. pll_periph0x2 {
  162. #clock-cells = <0x0>;
  163. compatible = "allwinner,fixed-factor-clock";
  164. clocks = <0x2>;
  165. clock-mult = <0x2>;
  166. clock-div = <0x1>;
  167. clock-output-names = "pll_periph0x2";
  168. linux,phandle = <0x1b>;
  169. phandle = <0x1b>;
  170. };
  171.  
  172. pll_periph0x4 {
  173. #clock-cells = <0x0>;
  174. compatible = "allwinner,fixed-factor-clock";
  175. clocks = <0x2>;
  176. clock-mult = <0x4>;
  177. clock-div = <0x1>;
  178. clock-output-names = "pll_periph0x4";
  179. };
  180.  
  181. periph32k {
  182. #clock-cells = <0x0>;
  183. compatible = "allwinner,fixed-factor-clock";
  184. clocks = <0x2>;
  185. clock-mult = <0x2>;
  186. clock-div = <0x8f0d>;
  187. clock-output-names = "periph32k";
  188. };
  189.  
  190. pll_periph1x2 {
  191. #clock-cells = <0x0>;
  192. compatible = "allwinner,fixed-factor-clock";
  193. clocks = <0x3>;
  194. clock-mult = <0x2>;
  195. clock-div = <0x1>;
  196. clock-output-names = "pll_periph1x2";
  197. linux,phandle = <0x75>;
  198. phandle = <0x75>;
  199. };
  200.  
  201. pll_audiox4 {
  202. #clock-cells = <0x0>;
  203. compatible = "allwinner,fixed-factor-clock";
  204. clocks = <0x4>;
  205. clock-mult = <0x4>;
  206. clock-div = <0x1>;
  207. clock-output-names = "pll_audiox4";
  208. };
  209.  
  210. pll_audiox2 {
  211. #clock-cells = <0x0>;
  212. compatible = "allwinner,fixed-factor-clock";
  213. clocks = <0x4>;
  214. clock-mult = <0x2>;
  215. clock-div = <0x1>;
  216. clock-output-names = "pll_audiox2";
  217. };
  218.  
  219. pll_video0x4 {
  220. #clock-cells = <0x0>;
  221. compatible = "allwinner,fixed-factor-clock";
  222. clocks = <0x5>;
  223. clock-mult = <0x4>;
  224. clock-div = <0x1>;
  225. clock-output-names = "pll_video0x4";
  226. };
  227.  
  228. pll_video1x4 {
  229. #clock-cells = <0x0>;
  230. compatible = "allwinner,fixed-factor-clock";
  231. clocks = <0x6>;
  232. clock-mult = <0x4>;
  233. clock-div = <0x1>;
  234. clock-output-names = "pll_video1x4";
  235. };
  236.  
  237. hoscd2 {
  238. #clock-cells = <0x0>;
  239. compatible = "allwinner,fixed-factor-clock";
  240. clocks = <0x7>;
  241. clock-mult = <0x1>;
  242. clock-div = <0x2>;
  243. clock-output-names = "hoscd2";
  244. };
  245.  
  246. osc48md4 {
  247. #clock-cells = <0x0>;
  248. compatible = "allwinner,fixed-factor-clock";
  249. clocks = <0x8>;
  250. clock-mult = <0x1>;
  251. clock-div = <0x4>;
  252. clock-output-names = "osc48md4";
  253. linux,phandle = <0x39>;
  254. phandle = <0x39>;
  255. };
  256.  
  257. pll_periph0d6 {
  258. #clock-cells = <0x0>;
  259. compatible = "allwinner,fixed-factor-clock";
  260. clocks = <0x2>;
  261. clock-mult = <0x1>;
  262. clock-div = <0x6>;
  263. clock-output-names = "pll_periph0d6";
  264. };
  265.  
  266. cpu {
  267. #clock-cells = <0x0>;
  268. compatible = "allwinner,sunxi-periph-clock";
  269. clock-output-names = "cpu";
  270. };
  271.  
  272. axi {
  273. #clock-cells = <0x0>;
  274. compatible = "allwinner,sunxi-periph-clock";
  275. clock-output-names = "axi";
  276. };
  277.  
  278. cpuapb {
  279. #clock-cells = <0x0>;
  280. compatible = "allwinner,sunxi-periph-clock";
  281. clock-output-names = "cpuapb";
  282. };
  283.  
  284. psi {
  285. #clock-cells = <0x0>;
  286. compatible = "allwinner,sunxi-periph-clock";
  287. clock-output-names = "psi";
  288. };
  289.  
  290. ahb1 {
  291. #clock-cells = <0x0>;
  292. compatible = "allwinner,sunxi-periph-clock";
  293. clock-output-names = "ahb1";
  294. };
  295.  
  296. ahb2 {
  297. #clock-cells = <0x0>;
  298. compatible = "allwinner,sunxi-periph-clock";
  299. clock-output-names = "ahb2";
  300. };
  301.  
  302. ahb3 {
  303. #clock-cells = <0x0>;
  304. compatible = "allwinner,sunxi-periph-clock";
  305. clock-output-names = "ahb3";
  306. };
  307.  
  308. apb1 {
  309. #clock-cells = <0x0>;
  310. compatible = "allwinner,sunxi-periph-clock";
  311. clock-output-names = "apb1";
  312. };
  313.  
  314. apb2 {
  315. #clock-cells = <0x0>;
  316. compatible = "allwinner,sunxi-periph-clock";
  317. clock-output-names = "apb2";
  318. linux,phandle = <0xad>;
  319. phandle = <0xad>;
  320. };
  321.  
  322. mbus {
  323. #clock-cells = <0x0>;
  324. compatible = "allwinner,sunxi-periph-clock";
  325. clock-output-names = "mbus";
  326. };
  327.  
  328. de {
  329. #clock-cells = <0x0>;
  330. compatible = "allwinner,sunxi-periph-clock";
  331. assigned-clock-parents = <0x9>;
  332. assigned-clock-rates = <0x297c1e00>;
  333. clock-output-names = "de";
  334. linux,phandle = <0x86>;
  335. phandle = <0x86>;
  336. };
  337.  
  338. di {
  339. #clock-cells = <0x0>;
  340. compatible = "allwinner,sunxi-periph-clock";
  341. clock-output-names = "di";
  342. linux,phandle = <0xab>;
  343. phandle = <0xab>;
  344. };
  345.  
  346. gpu {
  347. #clock-cells = <0x0>;
  348. compatible = "allwinner,sunxi-periph-clock";
  349. clock-output-names = "gpu";
  350. linux,phandle = <0xd9>;
  351. phandle = <0xd9>;
  352. };
  353.  
  354. ce {
  355. #clock-cells = <0x0>;
  356. compatible = "allwinner,sunxi-periph-clock";
  357. clock-output-names = "ce";
  358. linux,phandle = <0xaa>;
  359. phandle = <0xaa>;
  360. };
  361.  
  362. ve {
  363. #clock-cells = <0x0>;
  364. compatible = "allwinner,sunxi-periph-clock";
  365. clock-output-names = "ve";
  366. linux,phandle = <0x18>;
  367. phandle = <0x18>;
  368. };
  369.  
  370. emce {
  371. #clock-cells = <0x0>;
  372. compatible = "allwinner,sunxi-periph-clock";
  373. clock-output-names = "emce";
  374. linux,phandle = <0xa9>;
  375. phandle = <0xa9>;
  376. };
  377.  
  378. vp9 {
  379. #clock-cells = <0x0>;
  380. compatible = "allwinner,sunxi-periph-clock";
  381. clock-output-names = "vp9";
  382. linux,phandle = <0x1a>;
  383. phandle = <0x1a>;
  384. };
  385.  
  386. dma {
  387. #clock-cells = <0x0>;
  388. compatible = "allwinner,sunxi-periph-clock";
  389. clock-output-names = "dma";
  390. linux,phandle = <0xc>;
  391. phandle = <0xc>;
  392. };
  393.  
  394. msgbox {
  395. #clock-cells = <0x0>;
  396. compatible = "allwinner,sunxi-periph-clock";
  397. clock-output-names = "msgbox";
  398. linux,phandle = <0xf>;
  399. phandle = <0xf>;
  400. };
  401.  
  402. hwspinlock_rst {
  403. #clock-cells = <0x0>;
  404. compatible = "allwinner,sunxi-periph-clock";
  405. clock-output-names = "hwspinlock_rst";
  406. linux,phandle = <0x10>;
  407. phandle = <0x10>;
  408. };
  409.  
  410. hwspinlock_bus {
  411. #clock-cells = <0x0>;
  412. compatible = "allwinner,sunxi-periph-clock";
  413. clock-output-names = "hwspinlock_bus";
  414. linux,phandle = <0x11>;
  415. phandle = <0x11>;
  416. };
  417.  
  418. hstimer {
  419. #clock-cells = <0x0>;
  420. compatible = "allwinner,sunxi-periph-clock";
  421. clock-output-names = "hstimer";
  422. };
  423.  
  424. avs {
  425. #clock-cells = <0x0>;
  426. compatible = "allwinner,sunxi-periph-clock";
  427. clock-output-names = "avs";
  428. };
  429.  
  430. dbgsys {
  431. #clock-cells = <0x0>;
  432. compatible = "allwinner,sunxi-periph-clock";
  433. clock-output-names = "dbgsys";
  434. };
  435.  
  436. pwm {
  437. #clock-cells = <0x0>;
  438. compatible = "allwinner,sunxi-periph-clock";
  439. clock-output-names = "pwm";
  440. linux,phandle = <0x92>;
  441. phandle = <0x92>;
  442. };
  443.  
  444. iommu {
  445. #clock-cells = <0x0>;
  446. compatible = "allwinner,sunxi-periph-clock";
  447. clock-output-names = "iommu";
  448. linux,phandle = <0xd7>;
  449. phandle = <0xd7>;
  450. };
  451.  
  452. sdram {
  453. #clock-cells = <0x0>;
  454. compatible = "allwinner,sunxi-periph-clock";
  455. clock-output-names = "sdram";
  456. };
  457.  
  458. nand0 {
  459. #clock-cells = <0x0>;
  460. compatible = "allwinner,sunxi-periph-clock";
  461. clock-output-names = "nand0";
  462. linux,phandle = <0xb5>;
  463. phandle = <0xb5>;
  464. };
  465.  
  466. nand1 {
  467. #clock-cells = <0x0>;
  468. compatible = "allwinner,sunxi-periph-clock";
  469. clock-output-names = "nand1";
  470. linux,phandle = <0xb6>;
  471. phandle = <0xb6>;
  472. };
  473.  
  474. sdmmc0_mod {
  475. #clock-cells = <0x0>;
  476. compatible = "allwinner,sunxi-periph-clock";
  477. clock-output-names = "sdmmc0_mod";
  478. linux,phandle = <0x7b>;
  479. phandle = <0x7b>;
  480. };
  481.  
  482. sdmmc0_bus {
  483. #clock-cells = <0x0>;
  484. compatible = "allwinner,sunxi-periph-clock";
  485. clock-output-names = "sdmmc0_bus";
  486. linux,phandle = <0x7c>;
  487. phandle = <0x7c>;
  488. };
  489.  
  490. sdmmc0_rst {
  491. #clock-cells = <0x0>;
  492. compatible = "allwinner,sunxi-periph-clock";
  493. clock-output-names = "sdmmc0_rst";
  494. linux,phandle = <0x7d>;
  495. phandle = <0x7d>;
  496. };
  497.  
  498. sdmmc1_mod {
  499. #clock-cells = <0x0>;
  500. compatible = "allwinner,sunxi-periph-clock";
  501. clock-output-names = "sdmmc1_mod";
  502. linux,phandle = <0x81>;
  503. phandle = <0x81>;
  504. };
  505.  
  506. sdmmc1_bus {
  507. #clock-cells = <0x0>;
  508. compatible = "allwinner,sunxi-periph-clock";
  509. clock-output-names = "sdmmc1_bus";
  510. linux,phandle = <0x82>;
  511. phandle = <0x82>;
  512. };
  513.  
  514. sdmmc1_rst {
  515. #clock-cells = <0x0>;
  516. compatible = "allwinner,sunxi-periph-clock";
  517. clock-output-names = "sdmmc1_rst";
  518. linux,phandle = <0x83>;
  519. phandle = <0x83>;
  520. };
  521.  
  522. sdmmc2_mod {
  523. #clock-cells = <0x0>;
  524. compatible = "allwinner,sunxi-periph-clock";
  525. clock-output-names = "sdmmc2_mod";
  526. linux,phandle = <0x76>;
  527. phandle = <0x76>;
  528. };
  529.  
  530. sdmmc2_bus {
  531. #clock-cells = <0x0>;
  532. compatible = "allwinner,sunxi-periph-clock";
  533. clock-output-names = "sdmmc2_bus";
  534. linux,phandle = <0x77>;
  535. phandle = <0x77>;
  536. };
  537.  
  538. sdmmc2_rst {
  539. #clock-cells = <0x0>;
  540. compatible = "allwinner,sunxi-periph-clock";
  541. clock-output-names = "sdmmc2_rst";
  542. linux,phandle = <0x78>;
  543. phandle = <0x78>;
  544. };
  545.  
  546. uart0 {
  547. #clock-cells = <0x0>;
  548. compatible = "allwinner,sunxi-periph-clock";
  549. clock-output-names = "uart0";
  550. linux,phandle = <0x1c>;
  551. phandle = <0x1c>;
  552. };
  553.  
  554. uart1 {
  555. #clock-cells = <0x0>;
  556. compatible = "allwinner,sunxi-periph-clock";
  557. clock-output-names = "uart1";
  558. linux,phandle = <0x1f>;
  559. phandle = <0x1f>;
  560. };
  561.  
  562. uart2 {
  563. #clock-cells = <0x0>;
  564. compatible = "allwinner,sunxi-periph-clock";
  565. clock-output-names = "uart2";
  566. linux,phandle = <0x22>;
  567. phandle = <0x22>;
  568. };
  569.  
  570. uart3 {
  571. #clock-cells = <0x0>;
  572. compatible = "allwinner,sunxi-periph-clock";
  573. clock-output-names = "uart3";
  574. linux,phandle = <0x25>;
  575. phandle = <0x25>;
  576. };
  577.  
  578. twi0 {
  579. #clock-cells = <0x0>;
  580. compatible = "allwinner,sunxi-periph-clock";
  581. clock-output-names = "twi0";
  582. linux,phandle = <0x28>;
  583. phandle = <0x28>;
  584. };
  585.  
  586. twi1 {
  587. #clock-cells = <0x0>;
  588. compatible = "allwinner,sunxi-periph-clock";
  589. clock-output-names = "twi1";
  590. linux,phandle = <0x2b>;
  591. phandle = <0x2b>;
  592. };
  593.  
  594. twi2 {
  595. #clock-cells = <0x0>;
  596. compatible = "allwinner,sunxi-periph-clock";
  597. clock-output-names = "twi2";
  598. linux,phandle = <0x2e>;
  599. phandle = <0x2e>;
  600. };
  601.  
  602. twi3 {
  603. #clock-cells = <0x0>;
  604. compatible = "allwinner,sunxi-periph-clock";
  605. clock-output-names = "twi3";
  606. linux,phandle = <0x31>;
  607. phandle = <0x31>;
  608. };
  609.  
  610. scr0 {
  611. #clock-cells = <0x0>;
  612. compatible = "allwinner,sunxi-periph-clock";
  613. clock-output-names = "scr0";
  614. linux,phandle = <0xac>;
  615. phandle = <0xac>;
  616. };
  617.  
  618. scr1 {
  619. #clock-cells = <0x0>;
  620. compatible = "allwinner,sunxi-periph-clock";
  621. clock-output-names = "scr1";
  622. linux,phandle = <0xb1>;
  623. phandle = <0xb1>;
  624. };
  625.  
  626. spi0 {
  627. #clock-cells = <0x0>;
  628. compatible = "allwinner,sunxi-periph-clock";
  629. clock-output-names = "spi0";
  630. linux,phandle = <0x67>;
  631. phandle = <0x67>;
  632. };
  633.  
  634. spi1 {
  635. #clock-cells = <0x0>;
  636. compatible = "allwinner,sunxi-periph-clock";
  637. clock-output-names = "spi1";
  638. linux,phandle = <0x6b>;
  639. phandle = <0x6b>;
  640. };
  641.  
  642. gmac {
  643. #clock-cells = <0x0>;
  644. compatible = "allwinner,sunxi-periph-clock";
  645. clock-output-names = "gmac";
  646. linux,phandle = <0xd1>;
  647. phandle = <0xd1>;
  648. };
  649.  
  650. sata {
  651. #clock-cells = <0x0>;
  652. compatible = "allwinner,sunxi-periph-clock";
  653. clock-output-names = "sata";
  654. };
  655.  
  656. sata_24m {
  657. #clock-cells = <0x0>;
  658. compatible = "allwinner,sunxi-periph-clock";
  659. clock-output-names = "sata_24m";
  660. };
  661.  
  662. ts {
  663. #clock-cells = <0x0>;
  664. compatible = "allwinner,sunxi-periph-clock";
  665. clock-output-names = "ts";
  666. linux,phandle = <0xba>;
  667. phandle = <0xba>;
  668. };
  669.  
  670. irtx {
  671. #clock-cells = <0x0>;
  672. compatible = "allwinner,sunxi-periph-clock";
  673. clock-output-names = "irtx";
  674. };
  675.  
  676. ths {
  677. #clock-cells = <0x0>;
  678. compatible = "allwinner,sunxi-periph-clock";
  679. clock-output-names = "ths";
  680. linux,phandle = <0xc3>;
  681. phandle = <0xc3>;
  682. };
  683.  
  684. i2s0 {
  685. #clock-cells = <0x0>;
  686. compatible = "allwinner,sunxi-periph-clock";
  687. clock-output-names = "i2s0";
  688. linux,phandle = <0x42>;
  689. phandle = <0x42>;
  690. };
  691.  
  692. i2s1 {
  693. #clock-cells = <0x0>;
  694. compatible = "allwinner,sunxi-periph-clock";
  695. clock-output-names = "i2s1";
  696. linux,phandle = <0x45>;
  697. phandle = <0x45>;
  698. };
  699.  
  700. i2s2 {
  701. #clock-cells = <0x0>;
  702. compatible = "allwinner,sunxi-periph-clock";
  703. clock-output-names = "i2s2";
  704. linux,phandle = <0x46>;
  705. phandle = <0x46>;
  706. };
  707.  
  708. i2s3 {
  709. #clock-cells = <0x0>;
  710. compatible = "allwinner,sunxi-periph-clock";
  711. clock-output-names = "i2s3";
  712. linux,phandle = <0x49>;
  713. phandle = <0x49>;
  714. };
  715.  
  716. spdif {
  717. #clock-cells = <0x0>;
  718. compatible = "allwinner,sunxi-periph-clock";
  719. clock-output-names = "spdif";
  720. linux,phandle = <0x4c>;
  721. phandle = <0x4c>;
  722. };
  723.  
  724. dmic {
  725. #clock-cells = <0x0>;
  726. compatible = "allwinner,sunxi-periph-clock";
  727. clock-output-names = "dmic";
  728. linux,phandle = <0x4f>;
  729. phandle = <0x4f>;
  730. };
  731.  
  732. ahub {
  733. #clock-cells = <0x0>;
  734. compatible = "allwinner,sunxi-periph-clock";
  735. clock-output-names = "ahub";
  736. linux,phandle = <0x52>;
  737. phandle = <0x52>;
  738. };
  739.  
  740. usbphy0 {
  741. #clock-cells = <0x0>;
  742. compatible = "allwinner,sunxi-periph-clock";
  743. clock-output-names = "usbphy0";
  744. linux,phandle = <0x34>;
  745. phandle = <0x34>;
  746. };
  747.  
  748. usbphy1 {
  749. #clock-cells = <0x0>;
  750. compatible = "allwinner,sunxi-periph-clock";
  751. clock-output-names = "usbphy1";
  752. linux,phandle = <0x3a>;
  753. phandle = <0x3a>;
  754. };
  755.  
  756. usbphy3 {
  757. #clock-cells = <0x0>;
  758. compatible = "allwinner,sunxi-periph-clock";
  759. clock-output-names = "usbphy3";
  760. linux,phandle = <0x3c>;
  761. phandle = <0x3c>;
  762. };
  763.  
  764. usbohci0 {
  765. #clock-cells = <0x0>;
  766. compatible = "allwinner,sunxi-periph-clock";
  767. clock-output-names = "usbohci0";
  768. linux,phandle = <0x37>;
  769. phandle = <0x37>;
  770. };
  771.  
  772. usbohci0_12m {
  773. #clock-cells = <0x0>;
  774. compatible = "allwinner,sunxi-periph-clock";
  775. clock-output-names = "usbohci0_12m";
  776. linux,phandle = <0x38>;
  777. phandle = <0x38>;
  778. };
  779.  
  780. usbohci3 {
  781. #clock-cells = <0x0>;
  782. compatible = "allwinner,sunxi-periph-clock";
  783. clock-output-names = "usbohci3";
  784. linux,phandle = <0x40>;
  785. phandle = <0x40>;
  786. };
  787.  
  788. usbohci3_12m {
  789. #clock-cells = <0x0>;
  790. compatible = "allwinner,sunxi-periph-clock";
  791. clock-output-names = "usbohci3_12m";
  792. linux,phandle = <0x41>;
  793. phandle = <0x41>;
  794. };
  795.  
  796. usbehci0 {
  797. #clock-cells = <0x0>;
  798. compatible = "allwinner,sunxi-periph-clock";
  799. clock-output-names = "usbehci0";
  800. linux,phandle = <0x36>;
  801. phandle = <0x36>;
  802. };
  803.  
  804. usbehci3 {
  805. #clock-cells = <0x0>;
  806. compatible = "allwinner,sunxi-periph-clock";
  807. clock-output-names = "usbehci3";
  808. linux,phandle = <0x3d>;
  809. phandle = <0x3d>;
  810. };
  811.  
  812. usb3_0_host {
  813. #clock-cells = <0x0>;
  814. compatible = "allwinner,sunxi-periph-clock";
  815. clock-output-names = "usb3_0_host";
  816. linux,phandle = <0x3b>;
  817. phandle = <0x3b>;
  818. };
  819.  
  820. usbotg {
  821. #clock-cells = <0x0>;
  822. compatible = "allwinner,sunxi-periph-clock";
  823. clock-output-names = "usbotg";
  824. linux,phandle = <0x35>;
  825. phandle = <0x35>;
  826. };
  827.  
  828. usbhsic {
  829. #clock-cells = <0x0>;
  830. compatible = "allwinner,sunxi-periph-clock";
  831. clock-output-names = "usbhsic";
  832. linux,phandle = <0x3e>;
  833. phandle = <0x3e>;
  834. };
  835.  
  836. pcieref {
  837. #clock-cells = <0x0>;
  838. compatible = "allwinner,sunxi-periph-clock";
  839. clock-output-names = "pcieref";
  840. linux,phandle = <0x6f>;
  841. phandle = <0x6f>;
  842. };
  843.  
  844. pciemaxi {
  845. #clock-cells = <0x0>;
  846. compatible = "allwinner,sunxi-periph-clock";
  847. assigned-clock-rates = <0xbebc200>;
  848. clock-output-names = "pciemaxi";
  849. linux,phandle = <0x70>;
  850. phandle = <0x70>;
  851. };
  852.  
  853. pcieaux {
  854. #clock-cells = <0x0>;
  855. compatible = "allwinner,sunxi-periph-clock";
  856. assigned-clock-rates = <0xf4240>;
  857. clock-output-names = "pcieaux";
  858. linux,phandle = <0x71>;
  859. phandle = <0x71>;
  860. };
  861.  
  862. pcie_bus {
  863. #clock-cells = <0x0>;
  864. compatible = "allwinner,sunxi-periph-clock";
  865. clock-output-names = "pcie_bus";
  866. linux,phandle = <0x72>;
  867. phandle = <0x72>;
  868. };
  869.  
  870. pcie_power {
  871. #clock-cells = <0x0>;
  872. compatible = "allwinner,sunxi-periph-clock";
  873. clock-output-names = "pcie_power";
  874. linux,phandle = <0x73>;
  875. phandle = <0x73>;
  876. };
  877.  
  878. pcie_rst {
  879. #clock-cells = <0x0>;
  880. compatible = "allwinner,sunxi-periph-clock";
  881. clock-output-names = "pcie_rst";
  882. linux,phandle = <0x74>;
  883. phandle = <0x74>;
  884. };
  885.  
  886. hdmi {
  887. #clock-cells = <0x0>;
  888. compatible = "allwinner,sunxi-periph-clock";
  889. assigned-clock-parents = <0x6>;
  890. clock-output-names = "hdmi";
  891. linux,phandle = <0x8a>;
  892. phandle = <0x8a>;
  893. };
  894.  
  895. hdmi_slow {
  896. #clock-cells = <0x0>;
  897. compatible = "allwinner,sunxi-periph-clock";
  898. clock-output-names = "hdmi_slow";
  899. linux,phandle = <0x8b>;
  900. phandle = <0x8b>;
  901. };
  902.  
  903. hdmi_cec {
  904. #clock-cells = <0x0>;
  905. compatible = "allwinner,sunxi-periph-clock";
  906. clock-output-names = "hdmi_cec";
  907. linux,phandle = <0x8d>;
  908. phandle = <0x8d>;
  909. };
  910.  
  911. display_top {
  912. #clock-cells = <0x0>;
  913. compatible = "allwinner,sunxi-periph-clock";
  914. clock-output-names = "display_top";
  915. linux,phandle = <0x87>;
  916. phandle = <0x87>;
  917. };
  918.  
  919. tcon_lcd {
  920. #clock-cells = <0x0>;
  921. compatible = "allwinner,sunxi-periph-clock";
  922. clock-output-names = "tcon_lcd";
  923. linux,phandle = <0x88>;
  924. phandle = <0x88>;
  925. };
  926.  
  927. tcon_tv {
  928. #clock-cells = <0x0>;
  929. compatible = "allwinner,sunxi-periph-clock";
  930. assigned-clock-parents = <0x6>;
  931. clock-output-names = "tcon_tv";
  932. linux,phandle = <0x89>;
  933. phandle = <0x89>;
  934. };
  935.  
  936. csi_misc {
  937. #clock-cells = <0x0>;
  938. compatible = "allwinner,sunxi-periph-clock";
  939. clock-output-names = "csi_misc";
  940. linux,phandle = <0x9d>;
  941. phandle = <0x9d>;
  942. };
  943.  
  944. csi_top {
  945. #clock-cells = <0x0>;
  946. compatible = "allwinner,sunxi-periph-clock";
  947. clock-output-names = "csi_top";
  948. linux,phandle = <0x99>;
  949. phandle = <0x99>;
  950. };
  951.  
  952. csi_master0 {
  953. #clock-cells = <0x0>;
  954. compatible = "allwinner,sunxi-periph-clock";
  955. clock-output-names = "csi_master0";
  956. linux,phandle = <0x9a>;
  957. phandle = <0x9a>;
  958. };
  959.  
  960. hdmi_hdcp {
  961. #clock-cells = <0x0>;
  962. compatible = "allwinner,sunxi-periph-clock";
  963. assigned-clock-parents = <0x3>;
  964. clock-output-names = "hdmi_hdcp";
  965. linux,phandle = <0x8c>;
  966. phandle = <0x8c>;
  967. };
  968.  
  969. pio {
  970. #clock-cells = <0x0>;
  971. compatible = "allwinner,sunxi-periph-clock";
  972. clock-output-names = "pio";
  973. linux,phandle = <0xb>;
  974. phandle = <0xb>;
  975. };
  976.  
  977. cpurcir {
  978. #clock-cells = <0x0>;
  979. compatible = "allwinner,sunxi-periph-cpus-clock";
  980. clock-output-names = "cpurcir";
  981. linux,phandle = <0x13>;
  982. phandle = <0x13>;
  983. };
  984.  
  985. losc_out {
  986. #clock-cells = <0x0>;
  987. compatible = "allwinner,sunxi-periph-cpus-clock";
  988. clock-output-names = "losc_out";
  989. linux,phandle = <0xda>;
  990. phandle = <0xda>;
  991. };
  992.  
  993. cpurcpus_pll {
  994. #clock-cells = <0x0>;
  995. compatible = "allwinner,sunxi-periph-cpus-clock";
  996. clock-output-names = "cpurcpus_pll";
  997. };
  998.  
  999. cpurcpus {
  1000. #clock-cells = <0x0>;
  1001. compatible = "allwinner,sunxi-periph-cpus-clock";
  1002. clock-output-names = "cpurcpus";
  1003. };
  1004.  
  1005. cpurahbs {
  1006. #clock-cells = <0x0>;
  1007. compatible = "allwinner,sunxi-periph-cpus-clock";
  1008. clock-output-names = "cpurahbs";
  1009. };
  1010.  
  1011. cpurapbs1 {
  1012. #clock-cells = <0x0>;
  1013. compatible = "allwinner,sunxi-periph-cpus-clock";
  1014. clock-output-names = "cpurapbs1";
  1015. };
  1016.  
  1017. cpurapbs2_pll {
  1018. #clock-cells = <0x0>;
  1019. compatible = "allwinner,sunxi-periph-cpus-clock";
  1020. clock-output-names = "cpurapbs2_pll";
  1021. };
  1022.  
  1023. cpurapbs2 {
  1024. #clock-cells = <0x0>;
  1025. compatible = "allwinner,sunxi-periph-cpus-clock";
  1026. clock-output-names = "cpurapbs2";
  1027. };
  1028.  
  1029. cpurpio {
  1030. #clock-cells = <0x0>;
  1031. compatible = "allwinner,sunxi-periph-cpus-clock";
  1032. clock-output-names = "cpurpio";
  1033. linux,phandle = <0xa>;
  1034. phandle = <0xa>;
  1035. };
  1036.  
  1037. spwm {
  1038. #clock-cells = <0x0>;
  1039. compatible = "allwinner,sunxi-periph-cpus-clock";
  1040. clock-output-names = "spwm";
  1041. linux,phandle = <0x95>;
  1042. phandle = <0x95>;
  1043. };
  1044.  
  1045. dcxo_out {
  1046. #clock-cells = <0x0>;
  1047. compatible = "allwinner,sunxi-periph-cpus-clock";
  1048. clock-output-names = "dcxo_out";
  1049. };
  1050. };
  1051.  
  1052. soc@03000000 {
  1053. compatible = "simple-bus";
  1054. #address-cells = <0x2>;
  1055. #size-cells = <0x2>;
  1056. ranges;
  1057. device_type = "soc";
  1058.  
  1059. pinctrl@07022000 {
  1060. compatible = "allwinner,sun50iw6p1-r-pinctrl";
  1061. reg = <0x0 0x7022000 0x0 0x400>;
  1062. interrupts = <0x0 0x69 0x4 0x0 0x6f 0x4>;
  1063. clocks = <0xa>;
  1064. device_type = "r_pio";
  1065. gpio-controller;
  1066. interrupt-controller;
  1067. #interrupt-cells = <0x2>;
  1068. #size-cells = <0x0>;
  1069. #gpio-cells = <0x6>;
  1070. linux,phandle = <0xdb>;
  1071. phandle = <0xdb>;
  1072.  
  1073. s_twi0@0 {
  1074. allwinner,pins = "PL0", "PL1";
  1075. allwinner,function = "s_twi0";
  1076. allwinner,muxsel = <0x3>;
  1077. allwinner,drive = <0x0>;
  1078. allwinner,pull = <0x1>;
  1079. linux,phandle = <0x15>;
  1080. phandle = <0x15>;
  1081. };
  1082.  
  1083. s_cir0@0 {
  1084. allwinner,pins = "PL9";
  1085. allwinner,function = "s_cir0";
  1086. allwinner,muxsel = <0x2>;
  1087. allwinner,drive = <0x2>;
  1088. allwinner,pull = <0x1>;
  1089. linux,phandle = <0x12>;
  1090. phandle = <0x12>;
  1091. };
  1092.  
  1093. twi_para@0 {
  1094. linux,phandle = <0xde>;
  1095. phandle = <0xde>;
  1096. allwinner,pins = "PL0", "PL1";
  1097. allwinner,function = "twi_para";
  1098. allwinner,pname = "twi_scl", "twi_sda";
  1099. allwinner,muxsel = <0x3>;
  1100. allwinner,pull = <0x1>;
  1101. allwinner,drive = <0x0>;
  1102. allwinner,data = <0xffffffff>;
  1103. };
  1104.  
  1105. pwm16@0 {
  1106. linux,phandle = <0x105>;
  1107. phandle = <0x105>;
  1108. allwinner,pins = "PL8";
  1109. allwinner,function = "pwm16";
  1110. allwinner,pname = "pwm_positive";
  1111. allwinner,muxsel = <0x2>;
  1112. allwinner,pull = <0x0>;
  1113. allwinner,drive = <0xffffffff>;
  1114. allwinner,data = <0xffffffff>;
  1115. };
  1116.  
  1117. pwm16@1 {
  1118. linux,phandle = <0x106>;
  1119. phandle = <0x106>;
  1120. allwinner,pins = "PL8";
  1121. allwinner,function = "pwm16";
  1122. allwinner,pname = "pwm_positive";
  1123. allwinner,muxsel = <0x7>;
  1124. allwinner,pull = <0x0>;
  1125. allwinner,drive = <0xffffffff>;
  1126. allwinner,data = <0xffffffff>;
  1127. };
  1128.  
  1129. s_uart0@0 {
  1130. linux,phandle = <0x10c>;
  1131. phandle = <0x10c>;
  1132. allwinner,pins = "PL2", "PL3";
  1133. allwinner,function = "s_uart0";
  1134. allwinner,pname = "s_uart0_tx", "s_uart0_rx";
  1135. allwinner,muxsel = <0x2>;
  1136. allwinner,pull = <0xffffffff>;
  1137. allwinner,drive = <0xffffffff>;
  1138. allwinner,data = <0xffffffff>;
  1139. };
  1140.  
  1141. s_rsb0@0 {
  1142. linux,phandle = <0x10d>;
  1143. phandle = <0x10d>;
  1144. allwinner,pins = "PL0", "PL1";
  1145. allwinner,function = "s_rsb0";
  1146. allwinner,pname = "s_rsb0_sck", "s_rsb0_sda";
  1147. allwinner,muxsel = <0x2>;
  1148. allwinner,pull = <0x1>;
  1149. allwinner,drive = <0x2>;
  1150. allwinner,data = <0xffffffff>;
  1151. };
  1152.  
  1153. s_jtag0@0 {
  1154. linux,phandle = <0x10e>;
  1155. phandle = <0x10e>;
  1156. allwinner,pins = "PL4", "PL5", "PL6", "PL7";
  1157. allwinner,function = "s_jtag0";
  1158. allwinner,pname = "s_jtag0_tms", "s_jtag0_tck", "s_jtag0_tdo", "s_jtag0_tdi";
  1159. allwinner,muxsel = <0x2>;
  1160. allwinner,pull = <0x1>;
  1161. allwinner,drive = <0x2>;
  1162. allwinner,data = <0xffffffff>;
  1163. };
  1164. };
  1165.  
  1166. pinctrl@0300b000 {
  1167. compatible = "allwinner,sun50iw6p1-pinctrl";
  1168. reg = <0x0 0x300b000 0x0 0x400>;
  1169. interrupts = <0x0 0x33 0x4 0x0 0x35 0x4 0x0 0x36 0x4 0x0 0x3b 0x4>;
  1170. device_type = "pio";
  1171. clocks = <0xb>;
  1172. gpio-controller;
  1173. interrupt-controller;
  1174. #interrupt-cells = <0x2>;
  1175. #size-cells = <0x0>;
  1176. #gpio-cells = <0x6>;
  1177. linux,phandle = <0x80>;
  1178. phandle = <0x80>;
  1179.  
  1180. twi3@1 {
  1181. allwinner,pins = "PB17", "PB18";
  1182. allwinner,function = "io_disabled";
  1183. allwinner,muxsel = <0x7>;
  1184. allwinner,drive = <0x1>;
  1185. allwinner,pull = <0x0>;
  1186. linux,phandle = <0x33>;
  1187. phandle = <0x33>;
  1188. };
  1189.  
  1190. ts0@0 {
  1191. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1192. allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7";
  1193. allwinner,function = "ts0";
  1194. allwinner,muxsel = <0x3>;
  1195. allwinner,drive = <0x1>;
  1196. allwinner,pull = <0x0>;
  1197. linux,phandle = <0xbb>;
  1198. phandle = <0xbb>;
  1199. };
  1200.  
  1201. ts0_sleep@0 {
  1202. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1203. allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7";
  1204. allwinner,function = "io_disabled";
  1205. allwinner,muxsel = <0x7>;
  1206. allwinner,drive = <0x1>;
  1207. allwinner,pull = <0x0>;
  1208. linux,phandle = <0xbf>;
  1209. phandle = <0xbf>;
  1210. };
  1211.  
  1212. ts1@0 {
  1213. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16";
  1214. allwinner,pname = "ts1_clk", "ts1_err", "ts1_sync", "ts1_dvld", "ts1_d0";
  1215. allwinner,function = "ts1";
  1216. allwinner,muxsel = <0x3>;
  1217. allwinner,drive = <0x1>;
  1218. allwinner,pull = <0x0>;
  1219. linux,phandle = <0xbc>;
  1220. phandle = <0xbc>;
  1221. };
  1222.  
  1223. ts1_sleep@0 {
  1224. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16";
  1225. allwinner,pname = "ts1_clk", "ts1_err", "ts1_sync", "ts1_dvld", "ts1_d0";
  1226. allwinner,function = "io_disabled";
  1227. allwinner,muxsel = <0x7>;
  1228. allwinner,drive = <0x1>;
  1229. allwinner,pull = <0x0>;
  1230. linux,phandle = <0xc0>;
  1231. phandle = <0xc0>;
  1232. };
  1233.  
  1234. ts2@0 {
  1235. allwinner,pins = "PD17", "PD18", "PD19", "PD20", "PD21";
  1236. allwinner,pname = "ts2_clk", "ts2_err", "ts2_sync", "ts2_dvld", "ts2_d0";
  1237. allwinner,function = "ts2";
  1238. allwinner,muxsel = <0x3>;
  1239. allwinner,drive = <0x1>;
  1240. allwinner,pull = <0x0>;
  1241. linux,phandle = <0xbd>;
  1242. phandle = <0xbd>;
  1243. };
  1244.  
  1245. ts2_sleep@0 {
  1246. allwinner,pins = "PD17", "PD18", "PD19", "PD20", "PD21";
  1247. allwinner,pname = "ts2_clk", "ts2_err", "ts2_sync", "ts2_dvld", "ts2_d0";
  1248. allwinner,function = "io_disabled";
  1249. allwinner,muxsel = <0x7>;
  1250. allwinner,drive = <0x1>;
  1251. allwinner,pull = <0x0>;
  1252. linux,phandle = <0xc1>;
  1253. phandle = <0xc1>;
  1254. };
  1255.  
  1256. ts3@0 {
  1257. allwinner,pins = "PD22", "PD23", "PD24", "PD25", "PD26";
  1258. allwinner,pname = "ts3_clk", "ts3_err", "ts3_sync", "ts3_dvld", "ts3_d0";
  1259. allwinner,function = "ts3";
  1260. allwinner,muxsel = <0x3>;
  1261. allwinner,drive = <0x1>;
  1262. allwinner,pull = <0x0>;
  1263. linux,phandle = <0xbe>;
  1264. phandle = <0xbe>;
  1265. };
  1266.  
  1267. ts3_sleep@0 {
  1268. allwinner,pins = "PD22", "PD23", "PD24", "PD25", "PD26";
  1269. allwinner,pname = "ts3_clk", "ts3_err", "ts3_sync", "ts3_dvld", "ts3_d0";
  1270. allwinner,function = "io_disabled";
  1271. allwinner,muxsel = <0x7>;
  1272. allwinner,drive = <0x1>;
  1273. allwinner,pull = <0x0>;
  1274. linux,phandle = <0xc2>;
  1275. phandle = <0xc2>;
  1276. };
  1277.  
  1278. sdc0@1 {
  1279. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1280. allwinner,function = "io_disabled";
  1281. allwinner,muxsel = <0x7>;
  1282. allwinner,drive = <0x1>;
  1283. allwinner,pull = <0x1>;
  1284. linux,phandle = <0x7f>;
  1285. phandle = <0x7f>;
  1286. };
  1287.  
  1288. sdc1@1 {
  1289. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1290. allwinner,function = "io_disabled";
  1291. allwinner,muxsel = <0x7>;
  1292. allwinner,drive = <0x1>;
  1293. allwinner,pull = <0x1>;
  1294. linux,phandle = <0x85>;
  1295. phandle = <0x85>;
  1296. };
  1297.  
  1298. sdc2@1 {
  1299. allwinner,pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  1300. allwinner,function = "io_disabled";
  1301. allwinner,muxsel = <0x7>;
  1302. allwinner,drive = <0x1>;
  1303. allwinner,pull = <0x1>;
  1304. linux,phandle = <0x7a>;
  1305. phandle = <0x7a>;
  1306. };
  1307.  
  1308. daudio0@0 {
  1309. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1310. allwinner,function = "pcm0";
  1311. allwinner,muxsel = <0x3>;
  1312. allwinner,drive = <0x1>;
  1313. allwinner,pull = <0x0>;
  1314. linux,phandle = <0x43>;
  1315. phandle = <0x43>;
  1316. };
  1317.  
  1318. daudio0_sleep@0 {
  1319. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1320. allwinner,function = "io_disabled";
  1321. allwinner,muxsel = <0x7>;
  1322. allwinner,drive = <0x1>;
  1323. allwinner,pull = <0x0>;
  1324. linux,phandle = <0x44>;
  1325. phandle = <0x44>;
  1326. };
  1327.  
  1328. daudio2@0 {
  1329. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1330. allwinner,function = "pcm2";
  1331. allwinner,muxsel = <0x2>;
  1332. allwinner,drive = <0x1>;
  1333. allwinner,pull = <0x0>;
  1334. linux,phandle = <0x47>;
  1335. phandle = <0x47>;
  1336. };
  1337.  
  1338. daudio2_sleep@0 {
  1339. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1340. allwinner,function = "io_disabled";
  1341. allwinner,muxsel = <0x7>;
  1342. allwinner,drive = <0x1>;
  1343. allwinner,pull = <0x0>;
  1344. linux,phandle = <0x48>;
  1345. phandle = <0x48>;
  1346. };
  1347.  
  1348. daudio3@0 {
  1349. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1350. allwinner,function = "pcm3";
  1351. allwinner,muxsel = <0x2>;
  1352. allwinner,driver = <0x1>;
  1353. allwinner,pull = <0x0>;
  1354. linux,phandle = <0x4a>;
  1355. phandle = <0x4a>;
  1356. };
  1357.  
  1358. daudio3_sleep@0 {
  1359. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1360. allwinner,function = "io_disabled";
  1361. allwinner,muxsel = <0x7>;
  1362. allwinner,driver = <0x1>;
  1363. allwinner,pull = <0x0>;
  1364. linux,phandle = <0x4b>;
  1365. phandle = <0x4b>;
  1366. };
  1367.  
  1368. spdif@0 {
  1369. allwinner,pins = "PH5", "PH6", "PH7";
  1370. allwinner,function = "spdif0";
  1371. allwinner,muxsel = <0x3>;
  1372. allwinner,drive = <0x1>;
  1373. allwinner,pull = <0x0>;
  1374. linux,phandle = <0x4d>;
  1375. phandle = <0x4d>;
  1376. };
  1377.  
  1378. spdif_sleep@0 {
  1379. allwinner,pins = "PH5", "PH6", "PH7";
  1380. allwinner,function = "io_disabled";
  1381. allwinner,muxsel = <0x7>;
  1382. allwinner,drive = <0x1>;
  1383. allwinner,pull = <0x0>;
  1384. linux,phandle = <0x4e>;
  1385. phandle = <0x4e>;
  1386. };
  1387.  
  1388. dmic@0 {
  1389. allwinner,pins = "PD14", "PD15", "PD16", "PD17", "PD18";
  1390. allwinner,function = "dmic";
  1391. allwinner,muxsel = <0x4>;
  1392. allwinner,driver = <0x1>;
  1393. allwinner,pull = <0x0>;
  1394. linux,phandle = <0x50>;
  1395. phandle = <0x50>;
  1396. };
  1397.  
  1398. dmic_sleep@0 {
  1399. allwinner,pins = "PD14", "PD15", "PD16", "PD17", "PD18";
  1400. allwinner,function = "io_disabled";
  1401. allwinner,muxsel = <0x7>;
  1402. allwinner,driver = <0x1>;
  1403. allwinner,pull = <0x0>;
  1404. linux,phandle = <0x51>;
  1405. phandle = <0x51>;
  1406. };
  1407.  
  1408. ahub_daudio0@0 {
  1409. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1410. allwinner,function = "pcm0";
  1411. allwinner,muxsel = <0x4>;
  1412. allwinner,driver = <0x1>;
  1413. allwinner,pull = <0x0>;
  1414. linux,phandle = <0x53>;
  1415. phandle = <0x53>;
  1416. };
  1417.  
  1418. ahub_daudio0_sleep@0 {
  1419. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4";
  1420. allwinner,function = "io_disabled";
  1421. allwinner,muxsel = <0x7>;
  1422. allwinner,driver = <0x1>;
  1423. allwinner,pull = <0x0>;
  1424. linux,phandle = <0x54>;
  1425. phandle = <0x54>;
  1426. };
  1427.  
  1428. ahub_daudio2@0 {
  1429. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1430. allwinner,function = "pcm2";
  1431. allwinner,muxsel = <0x3>;
  1432. allwinner,drive = <0x1>;
  1433. allwinner,pull = <0x0>;
  1434. linux,phandle = <0x55>;
  1435. phandle = <0x55>;
  1436. };
  1437.  
  1438. ahub_daudio2_sleep@0 {
  1439. allwinner,pins = "PG10", "PG11", "PG12", "PG13", "PG14";
  1440. allwinner,function = "io_disabled";
  1441. allwinner,muxsel = <0x7>;
  1442. allwinner,drive = <0x1>;
  1443. allwinner,pull = <0x0>;
  1444. linux,phandle = <0x56>;
  1445. phandle = <0x56>;
  1446. };
  1447.  
  1448. ahub_daudio3@0 {
  1449. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1450. allwinner,function = "pcm3";
  1451. allwinner,muxsel = <0x4>;
  1452. allwinner,driver = <0x1>;
  1453. allwinner,pull = <0x0>;
  1454. linux,phandle = <0x57>;
  1455. phandle = <0x57>;
  1456. };
  1457.  
  1458. ahub_daudio3_sleep@0 {
  1459. allwinner,pins = "PB12", "PB13", "PB14", "PB15", "PB16";
  1460. allwinner,function = "io_disabled";
  1461. allwinner,muxsel = <0x7>;
  1462. allwinner,driver = <0x1>;
  1463. allwinner,pull = <0x0>;
  1464. linux,phandle = <0x58>;
  1465. phandle = <0x58>;
  1466. };
  1467.  
  1468. csi0@1 {
  1469. allwinner,pins = "PD0", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1470. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7";
  1471. allwinner,function = "io_disabled";
  1472. allwinner,muxsel = <0x7>;
  1473. allwinner,drive = <0x1>;
  1474. allwinner,pull = <0x0>;
  1475. allwinner,data = <0x0>;
  1476. linux,phandle = <0xa1>;
  1477. phandle = <0xa1>;
  1478. };
  1479.  
  1480. csi_mclk0@0 {
  1481. allwinner,pins = "PD1";
  1482. allwinner,pname = "csi_mclk0";
  1483. allwinner,function = "csi_mclk0";
  1484. allwinner,muxsel = <0x4>;
  1485. allwinner,drive = <0x1>;
  1486. allwinner,pull = <0x0>;
  1487. allwinner,data = <0x0>;
  1488. linux,phandle = <0x9b>;
  1489. phandle = <0x9b>;
  1490. };
  1491.  
  1492. csi_mclk0@1 {
  1493. allwinner,pins = "PD1";
  1494. allwinner,pname = "csi_mclk0";
  1495. allwinner,function = "io_disabled";
  1496. allwinner,muxsel = <0x7>;
  1497. allwinner,drive = <0x1>;
  1498. allwinner,pull = <0x0>;
  1499. allwinner,data = <0x0>;
  1500. linux,phandle = <0x9c>;
  1501. phandle = <0x9c>;
  1502. };
  1503.  
  1504. csi_cci0@0 {
  1505. allwinner,pins = "PD12", "PD13";
  1506. allwinner,pname = "csi_cci0_sck", "csi_cci0_sda";
  1507. allwinner,function = "csi_cci0";
  1508. allwinner,muxsel = <0x4>;
  1509. allwinner,drive = <0x1>;
  1510. allwinner,pull = <0x0>;
  1511. allwinner,data = <0x0>;
  1512. linux,phandle = <0x9e>;
  1513. phandle = <0x9e>;
  1514. };
  1515.  
  1516. csi_cci0@1 {
  1517. allwinner,pins = "PD12", "PD13";
  1518. allwinner,pname = "csi_cci0_sck", "csi_cci0_sda";
  1519. allwinner,function = "io_disabled";
  1520. allwinner,muxsel = <0x7>;
  1521. allwinner,drive = <0x1>;
  1522. allwinner,pull = <0x0>;
  1523. allwinner,data = <0x0>;
  1524. linux,phandle = <0x9f>;
  1525. phandle = <0x9f>;
  1526. };
  1527.  
  1528. scr0@0 {
  1529. allwinner,pins = "PG13", "PG14", "PG10", "PG11", "PG12";
  1530. allwinner,pname = "scr0_rst", "scr0_det", "scr0_vccen", "scr0_sck", "scr0_sda";
  1531. allwinner,function = "sim0";
  1532. allwinner,muxsel = <0x4>;
  1533. allwinner,drive = <0x0>;
  1534. allwinner,pull = <0x1>;
  1535. linux,phandle = <0xae>;
  1536. phandle = <0xae>;
  1537. };
  1538.  
  1539. scr0@1 {
  1540. allwinner,pins = "PG8", "PG9";
  1541. allwinner,pname = "scr0_vppen", "scr0_vppp";
  1542. allwinner,function = "sim0";
  1543. allwinner,muxsel = <0x4>;
  1544. allwinner,drive = <0x0>;
  1545. allwinner,pull = <0x1>;
  1546. linux,phandle = <0xaf>;
  1547. phandle = <0xaf>;
  1548. };
  1549.  
  1550. scr0@2 {
  1551. allwinner,pins = "PG8", "PG9", "PG10", "PG11", "PG12", "PG13", "PG14";
  1552. allwinner,function = "io_disabled";
  1553. allwinner,muxsel = <0x7>;
  1554. allwinner,drive = <0x0>;
  1555. allwinner,pull = <0x0>;
  1556. linux,phandle = <0xb0>;
  1557. phandle = <0xb0>;
  1558. };
  1559.  
  1560. scr1@0 {
  1561. allwinner,pins = "PH5", "PH6", "PH2", "PH3", "PH4";
  1562. allwinner,pname = "scr1_rst", "scr1_det", "scr1_vccen", "scr1_sck", "scr1_sda";
  1563. allwinner,function = "sim1";
  1564. allwinner,muxsel = <0x5>;
  1565. allwinner,drive = <0x1>;
  1566. allwinner,pull = <0x1>;
  1567. linux,phandle = <0xb2>;
  1568. phandle = <0xb2>;
  1569. };
  1570.  
  1571. scr1@1 {
  1572. allwinner,pins = "PH0", "PH1";
  1573. allwinner,pname = "scr1_vppen", "scr1_vppp";
  1574. allwinner,function = "sim1";
  1575. allwinner,muxsel = <0x5>;
  1576. allwinner,drive = <0x1>;
  1577. allwinner,pull = <0x1>;
  1578. linux,phandle = <0xb3>;
  1579. phandle = <0xb3>;
  1580. };
  1581.  
  1582. scr1@2 {
  1583. allwinner,pins = "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6";
  1584. allwinner,function = "io_disabled";
  1585. allwinner,muxsel = <0x7>;
  1586. allwinner,drive = <0x1>;
  1587. allwinner,pull = <0x0>;
  1588. linux,phandle = <0xb4>;
  1589. phandle = <0xb4>;
  1590. };
  1591.  
  1592. nand0@2 {
  1593. allwinner,pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1594. allwinner,function = "io_disabled";
  1595. allwinner,muxsel = <0x7>;
  1596. allwinner,drive = <0x1>;
  1597. allwinner,pull = <0x0>;
  1598. linux,phandle = <0xb9>;
  1599. phandle = <0xb9>;
  1600. };
  1601.  
  1602. hdmi@1 {
  1603. allwinner,pins = "PH8", "PH9";
  1604. allwinner,function = "io_disabled";
  1605. allwinner,muxsel = <0x7>;
  1606. allwinner,drive = <0x1>;
  1607. allwinner,pull = <0x0>;
  1608. linux,phandle = <0x8f>;
  1609. phandle = <0x8f>;
  1610. };
  1611.  
  1612. hdmi@2 {
  1613. allwinner,pins = "PH10";
  1614. allwinner,function = "cec0";
  1615. allwinner,muxsel = <0x2>;
  1616. allwinner,drive = <0x1>;
  1617. allwinner,pull = <0x0>;
  1618. linux,phandle = <0x90>;
  1619. phandle = <0x90>;
  1620. };
  1621.  
  1622. hdmi@3 {
  1623. allwinner,pins = "PH10";
  1624. allwinner,function = "io_disabled";
  1625. allwinner,muxsel = <0x7>;
  1626. allwinner,drive = <0x1>;
  1627. allwinner,pull = <0x0>;
  1628. linux,phandle = <0x91>;
  1629. phandle = <0x91>;
  1630. };
  1631.  
  1632. ac200@2 {
  1633. allwinner,pins = "PB0";
  1634. allwinner,function = "ccir_clk";
  1635. allwinner,muxsel = <0x2>;
  1636. allwinner,drive = <0x1>;
  1637. allwinner,pull = <0x0>;
  1638. linux,phandle = <0x97>;
  1639. phandle = <0x97>;
  1640. };
  1641.  
  1642. ac200@3 {
  1643. allwinner,pins = "PB0";
  1644. allwinner,function = "io_disabled";
  1645. allwinner,muxsel = <0x7>;
  1646. allwinner,drive = <0x1>;
  1647. allwinner,pull = <0x0>;
  1648. linux,phandle = <0x98>;
  1649. phandle = <0x98>;
  1650. };
  1651.  
  1652. card0_boot_para@0 {
  1653. linux,phandle = <0xdc>;
  1654. phandle = <0xdc>;
  1655. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1656. allwinner,function = "card0_boot_para";
  1657. allwinner,pname = "sdc_d1", "sdc_d0", "sdc_clk", "sdc_cmd", "sdc_d3", "sdc_d2";
  1658. allwinner,muxsel = <0x2>;
  1659. allwinner,pull = <0x1>;
  1660. allwinner,drive = <0x2>;
  1661. allwinner,data = <0xffffffff>;
  1662. };
  1663.  
  1664. card2_boot_para@0 {
  1665. linux,phandle = <0xdd>;
  1666. phandle = <0xdd>;
  1667. allwinner,pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  1668. allwinner,function = "card2_boot_para";
  1669. allwinner,pname = "sdc_ds", "sdc_clk", "sdc_cmd", "sdc_d0", "sdc_d1", "sdc_d2", "sdc_d3", "sdc_d4", "sdc_d5", "sdc_d6", "sdc_d7", "sdc_emmc_rst";
  1670. allwinner,muxsel = <0x3>;
  1671. allwinner,pull = <0x1>;
  1672. allwinner,drive = <0x3>;
  1673. allwinner,data = <0xffffffff>;
  1674. };
  1675.  
  1676. uart_para@0 {
  1677. linux,phandle = <0xdf>;
  1678. phandle = <0xdf>;
  1679. allwinner,pins = "PH0", "PH1";
  1680. allwinner,function = "uart_para";
  1681. allwinner,pname = "uart_debug_tx", "uart_debug_rx";
  1682. allwinner,muxsel = <0x2>;
  1683. allwinner,pull = <0x1>;
  1684. allwinner,drive = <0xffffffff>;
  1685. allwinner,data = <0xffffffff>;
  1686. };
  1687.  
  1688. jtag_para@0 {
  1689. linux,phandle = <0xe0>;
  1690. phandle = <0xe0>;
  1691. allwinner,pins = "PD23", "PD24", "PD25", "PD26";
  1692. allwinner,function = "jtag_para";
  1693. allwinner,pname = "jtag_ms", "jtag_ck", "jtag_do", "jtag_di";
  1694. allwinner,muxsel = <0x5>;
  1695. allwinner,pull = <0xffffffff>;
  1696. allwinner,drive = <0xffffffff>;
  1697. allwinner,data = <0xffffffff>;
  1698. };
  1699.  
  1700. gmac0@0 {
  1701. linux,phandle = <0xe1>;
  1702. phandle = <0xe1>;
  1703. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13", "PD19", "PD20", "PD21";
  1704. allwinner,function = "gmac0";
  1705. allwinner,pname = "gmac_rxd3", "gmac_rxd2", "gmac_rxd1", "gmac_rxd0", "gmac_rxck", "gmac_rxctl", "gmac_txd3", "gmac_txd2", "gmac_txd1", "gmac_txd0", "gmac_txck", "gmac_txctl", "gmac_clkin", "gmac_mdc", "gmac_mdio", "gmac_ephyrst";
  1706. allwinner,muxsel = <0x5>;
  1707. allwinner,pull = <0xffffffff>;
  1708. allwinner,drive = <0x3>;
  1709. allwinner,data = <0xffffffff>;
  1710. };
  1711.  
  1712. twi0@0 {
  1713. linux,phandle = <0xe2>;
  1714. phandle = <0xe2>;
  1715. allwinner,pins = "PD25", "PD26";
  1716. allwinner,function = "twi0";
  1717. allwinner,pname = "twi0_scl", "twi0_sda";
  1718. allwinner,muxsel = <0x2>;
  1719. allwinner,pull = <0xffffffff>;
  1720. allwinner,drive = <0xffffffff>;
  1721. allwinner,data = <0xffffffff>;
  1722. };
  1723.  
  1724. twi0@1 {
  1725. linux,phandle = <0xe3>;
  1726. phandle = <0xe3>;
  1727. allwinner,pins = "PD25", "PD26";
  1728. allwinner,function = "twi0";
  1729. allwinner,pname = "twi0_scl", "twi0_sda";
  1730. allwinner,muxsel = <0x7>;
  1731. allwinner,pull = <0xffffffff>;
  1732. allwinner,drive = <0xffffffff>;
  1733. allwinner,data = <0xffffffff>;
  1734. };
  1735.  
  1736. twi1@0 {
  1737. linux,phandle = <0xe4>;
  1738. phandle = <0xe4>;
  1739. allwinner,pins = "PH5", "PH6";
  1740. allwinner,function = "twi1";
  1741. allwinner,pname = "twi1_scl", "twi1_sda";
  1742. allwinner,muxsel = <0x4>;
  1743. allwinner,pull = <0xffffffff>;
  1744. allwinner,drive = <0xffffffff>;
  1745. allwinner,data = <0xffffffff>;
  1746. };
  1747.  
  1748. twi1@1 {
  1749. linux,phandle = <0xe5>;
  1750. phandle = <0xe5>;
  1751. allwinner,pins = "PH5", "PH6";
  1752. allwinner,function = "twi1";
  1753. allwinner,pname = "twi1_scl", "twi1_sda";
  1754. allwinner,muxsel = <0x7>;
  1755. allwinner,pull = <0xffffffff>;
  1756. allwinner,drive = <0xffffffff>;
  1757. allwinner,data = <0xffffffff>;
  1758. };
  1759.  
  1760. twi2@0 {
  1761. linux,phandle = <0xe6>;
  1762. phandle = <0xe6>;
  1763. allwinner,pins = "PD23", "PD24";
  1764. allwinner,function = "twi2";
  1765. allwinner,pname = "twi2_scl", "twi2_sda";
  1766. allwinner,muxsel = <0x2>;
  1767. allwinner,pull = <0xffffffff>;
  1768. allwinner,drive = <0xffffffff>;
  1769. allwinner,data = <0xffffffff>;
  1770. };
  1771.  
  1772. twi2@1 {
  1773. linux,phandle = <0xe7>;
  1774. phandle = <0xe7>;
  1775. allwinner,pins = "PD23", "PD24";
  1776. allwinner,function = "twi2";
  1777. allwinner,pname = "twi2_scl", "twi2_sda";
  1778. allwinner,muxsel = <0x7>;
  1779. allwinner,pull = <0xffffffff>;
  1780. allwinner,drive = <0xffffffff>;
  1781. allwinner,data = <0xffffffff>;
  1782. };
  1783.  
  1784. twi3@0 {
  1785. linux,phandle = <0xe8>;
  1786. phandle = <0xe8>;
  1787. allwinner,pins = "PB17", "PB18";
  1788. allwinner,function = "twi3";
  1789. allwinner,pname = "twi3_scl", "twi3_sda";
  1790. allwinner,muxsel = <0x2>;
  1791. allwinner,pull = <0xffffffff>;
  1792. allwinner,drive = <0xffffffff>;
  1793. allwinner,data = <0xffffffff>;
  1794. };
  1795.  
  1796. uart0@0 {
  1797. linux,phandle = <0xe9>;
  1798. phandle = <0xe9>;
  1799. allwinner,pins = "PH0", "PH1";
  1800. allwinner,function = "uart0";
  1801. allwinner,pname = "uart0_tx", "uart0_rx";
  1802. allwinner,muxsel = <0x2>;
  1803. allwinner,pull = <0x1>;
  1804. allwinner,drive = <0xffffffff>;
  1805. allwinner,data = <0xffffffff>;
  1806. };
  1807.  
  1808. uart0@1 {
  1809. linux,phandle = <0xea>;
  1810. phandle = <0xea>;
  1811. allwinner,pins = "PH0", "PH1";
  1812. allwinner,function = "uart0";
  1813. allwinner,pname = "uart0_tx", "uart0_rx";
  1814. allwinner,muxsel = <0x7>;
  1815. allwinner,pull = <0x1>;
  1816. allwinner,drive = <0xffffffff>;
  1817. allwinner,data = <0xffffffff>;
  1818. };
  1819.  
  1820. uart1@0 {
  1821. linux,phandle = <0xeb>;
  1822. phandle = <0xeb>;
  1823. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  1824. allwinner,function = "uart1";
  1825. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  1826. allwinner,muxsel = <0x2>;
  1827. allwinner,pull = <0x1>;
  1828. allwinner,drive = <0xffffffff>;
  1829. allwinner,data = <0xffffffff>;
  1830. };
  1831.  
  1832. uart1@1 {
  1833. linux,phandle = <0xec>;
  1834. phandle = <0xec>;
  1835. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  1836. allwinner,function = "uart1";
  1837. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  1838. allwinner,muxsel = <0x7>;
  1839. allwinner,pull = <0x1>;
  1840. allwinner,drive = <0xffffffff>;
  1841. allwinner,data = <0xffffffff>;
  1842. };
  1843.  
  1844. uart2@0 {
  1845. linux,phandle = <0xed>;
  1846. phandle = <0xed>;
  1847. allwinner,pins = "PD19", "PD20", "PD21", "PD22";
  1848. allwinner,function = "uart2";
  1849. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  1850. allwinner,muxsel = <0x4>;
  1851. allwinner,pull = <0x1>;
  1852. allwinner,drive = <0xffffffff>;
  1853. allwinner,data = <0xffffffff>;
  1854. };
  1855.  
  1856. uart2@1 {
  1857. linux,phandle = <0xee>;
  1858. phandle = <0xee>;
  1859. allwinner,pins = "PD19", "PD20", "PD21", "PD22";
  1860. allwinner,function = "uart2";
  1861. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  1862. allwinner,muxsel = <0x7>;
  1863. allwinner,pull = <0x1>;
  1864. allwinner,drive = <0xffffffff>;
  1865. allwinner,data = <0xffffffff>;
  1866. };
  1867.  
  1868. uart3@0 {
  1869. linux,phandle = <0xef>;
  1870. phandle = <0xef>;
  1871. allwinner,pins = "PD23", "PD24", "PD25", "PD26";
  1872. allwinner,function = "uart3";
  1873. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1874. allwinner,muxsel = <0x4>;
  1875. allwinner,pull = <0x1>;
  1876. allwinner,drive = <0xffffffff>;
  1877. allwinner,data = <0xffffffff>;
  1878. };
  1879.  
  1880. uart3@1 {
  1881. linux,phandle = <0xf0>;
  1882. phandle = <0xf0>;
  1883. allwinner,pins = "PD23", "PD24", "PD25", "PD26";
  1884. allwinner,function = "uart3";
  1885. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1886. allwinner,muxsel = <0x7>;
  1887. allwinner,pull = <0x1>;
  1888. allwinner,drive = <0xffffffff>;
  1889. allwinner,data = <0xffffffff>;
  1890. };
  1891.  
  1892. spi0@0 {
  1893. linux,phandle = <0xf1>;
  1894. phandle = <0xf1>;
  1895. allwinner,pins = "PC5";
  1896. allwinner,function = "spi0";
  1897. allwinner,pname = "spi0_cs0";
  1898. allwinner,muxsel = <0x4>;
  1899. allwinner,pull = <0x1>;
  1900. allwinner,drive = <0xffffffff>;
  1901. allwinner,data = <0xffffffff>;
  1902. };
  1903.  
  1904. spi0@1 {
  1905. linux,phandle = <0xf2>;
  1906. phandle = <0xf2>;
  1907. allwinner,pins = "PC0", "PC2", "PC3";
  1908. allwinner,function = "spi0";
  1909. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1910. allwinner,muxsel = <0x4>;
  1911. allwinner,pull = <0xffffffff>;
  1912. allwinner,drive = <0xffffffff>;
  1913. allwinner,data = <0xffffffff>;
  1914. };
  1915.  
  1916. spi0@2 {
  1917. linux,phandle = <0xf3>;
  1918. phandle = <0xf3>;
  1919. allwinner,pins = "PC5";
  1920. allwinner,function = "spi0";
  1921. allwinner,pname = "spi0_cs0";
  1922. allwinner,muxsel = <0x7>;
  1923. allwinner,pull = <0x1>;
  1924. allwinner,drive = <0xffffffff>;
  1925. allwinner,data = <0xffffffff>;
  1926. };
  1927.  
  1928. spi0@3 {
  1929. linux,phandle = <0xf4>;
  1930. phandle = <0xf4>;
  1931. allwinner,pins = "PC0", "PC2", "PC3";
  1932. allwinner,function = "spi0";
  1933. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1934. allwinner,muxsel = <0x7>;
  1935. allwinner,pull = <0xffffffff>;
  1936. allwinner,drive = <0xffffffff>;
  1937. allwinner,data = <0xffffffff>;
  1938. };
  1939.  
  1940. spi1@0 {
  1941. linux,phandle = <0xf5>;
  1942. phandle = <0xf5>;
  1943. allwinner,pins = "PH3";
  1944. allwinner,function = "spi1";
  1945. allwinner,pname = "spi1_cs0";
  1946. allwinner,muxsel = <0x2>;
  1947. allwinner,pull = <0x1>;
  1948. allwinner,drive = <0xffffffff>;
  1949. allwinner,data = <0xffffffff>;
  1950. };
  1951.  
  1952. spi1@1 {
  1953. linux,phandle = <0xf6>;
  1954. phandle = <0xf6>;
  1955. allwinner,pins = "PH4", "PH5", "PH6";
  1956. allwinner,function = "spi1";
  1957. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1958. allwinner,muxsel = <0x2>;
  1959. allwinner,pull = <0xffffffff>;
  1960. allwinner,drive = <0xffffffff>;
  1961. allwinner,data = <0xffffffff>;
  1962. };
  1963.  
  1964. spi1@2 {
  1965. linux,phandle = <0xf7>;
  1966. phandle = <0xf7>;
  1967. allwinner,pins = "PH3";
  1968. allwinner,function = "spi1";
  1969. allwinner,pname = "spi1_cs0";
  1970. allwinner,muxsel = <0x7>;
  1971. allwinner,pull = <0x1>;
  1972. allwinner,drive = <0xffffffff>;
  1973. allwinner,data = <0xffffffff>;
  1974. };
  1975.  
  1976. spi1@3 {
  1977. linux,phandle = <0xf8>;
  1978. phandle = <0xf8>;
  1979. allwinner,pins = "PH4", "PH5", "PH6";
  1980. allwinner,function = "spi1";
  1981. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1982. allwinner,muxsel = <0x7>;
  1983. allwinner,pull = <0xffffffff>;
  1984. allwinner,drive = <0xffffffff>;
  1985. allwinner,data = <0xffffffff>;
  1986. };
  1987.  
  1988. nand0@0 {
  1989. linux,phandle = <0xfa>;
  1990. phandle = <0xfa>;
  1991. allwinner,pins = "PC0", "PC1", "PC2", "PC4", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  1992. allwinner,function = "nand0";
  1993. allwinner,pname = "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs";
  1994. allwinner,muxsel = <0x2>;
  1995. allwinner,pull = <0x0>;
  1996. allwinner,drive = <0x1>;
  1997. allwinner,data = <0xffffffff>;
  1998. };
  1999.  
  2000. nand0@1 {
  2001. linux,phandle = <0xfb>;
  2002. phandle = <0xfb>;
  2003. allwinner,pins = "PC15", "PC3", "PC5", "PC16";
  2004. allwinner,function = "nand0";
  2005. allwinner,pname = "nand0_ce1", "nand0_ce0", "nand0_rb0", "nand0_rb1";
  2006. allwinner,muxsel = <0x2>;
  2007. allwinner,pull = <0x1>;
  2008. allwinner,drive = <0x1>;
  2009. allwinner,data = <0xffffffff>;
  2010. };
  2011.  
  2012. lcd0@0 {
  2013. linux,phandle = <0xfc>;
  2014. phandle = <0xfc>;
  2015. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
  2016. allwinner,function = "lcd0";
  2017. allwinner,pname = "lcdd0", "lcdd1", "lcdd2", "lcdd3", "lcdd4", "lcdd5", "lcdd6", "lcdd7", "lcdd8", "lcdd9";
  2018. allwinner,muxsel = <0x3>;
  2019. allwinner,pull = <0x0>;
  2020. allwinner,drive = <0xffffffff>;
  2021. allwinner,data = <0xffffffff>;
  2022. };
  2023.  
  2024. lcd0@1 {
  2025. linux,phandle = <0xfd>;
  2026. phandle = <0xfd>;
  2027. allwinner,pins = "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21";
  2028. allwinner,function = "lcd0";
  2029. allwinner,pname = "lcdd0", "lcdd1", "lcdd2", "lcdd3", "lcdd4", "lcdd5", "lcdd6", "lcdd7", "lcdd8", "lcdd9";
  2030. allwinner,muxsel = <0x7>;
  2031. allwinner,pull = <0x0>;
  2032. allwinner,drive = <0xffffffff>;
  2033. allwinner,data = <0xffffffff>;
  2034. };
  2035.  
  2036. hdmi@0 {
  2037. linux,phandle = <0xfe>;
  2038. phandle = <0xfe>;
  2039. allwinner,pins = "PH8", "PH9", "PH10";
  2040. allwinner,function = "hdmi";
  2041. allwinner,pname = "ddc_scl", "ddc_sda", "cec_io";
  2042. allwinner,muxsel = <0x2>;
  2043. allwinner,pull = <0xffffffff>;
  2044. allwinner,drive = <0x1>;
  2045. allwinner,data = <0xffffffff>;
  2046. };
  2047.  
  2048. ac200@0 {
  2049. linux,phandle = <0xff>;
  2050. phandle = <0xff>;
  2051. allwinner,pins = "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11";
  2052. allwinner,function = "ac200";
  2053. allwinner,pname = "ccir_clk", "ccir_de", "ccir_hs", "ccir_vs", "ccir_do0", "ccir_do1", "ccir_do2", "ccir_do3", "ccir_do4", "ccir_do5", "ccir_do6", "ccir_do7";
  2054. allwinner,muxsel = <0x2>;
  2055. allwinner,pull = <0x0>;
  2056. allwinner,drive = <0xffffffff>;
  2057. allwinner,data = <0xffffffff>;
  2058. };
  2059.  
  2060. ac200@1 {
  2061. linux,phandle = <0x100>;
  2062. phandle = <0x100>;
  2063. allwinner,pins = "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11";
  2064. allwinner,function = "ac200";
  2065. allwinner,pname = "ccir_de", "ccir_hs", "ccir_vs", "ccir_do0", "ccir_do1", "ccir_do2", "ccir_do3", "ccir_do4", "ccir_do5", "ccir_do6", "ccir_do7";
  2066. allwinner,muxsel = <0x7>;
  2067. allwinner,pull = <0x0>;
  2068. allwinner,drive = <0xffffffff>;
  2069. allwinner,data = <0xffffffff>;
  2070. };
  2071.  
  2072. pwm0@0 {
  2073. linux,phandle = <0x101>;
  2074. phandle = <0x101>;
  2075. allwinner,pins = "PD22";
  2076. allwinner,function = "pwm0";
  2077. allwinner,pname = "pwm_positive";
  2078. allwinner,muxsel = <0x2>;
  2079. allwinner,pull = <0x0>;
  2080. allwinner,drive = <0xffffffff>;
  2081. allwinner,data = <0xffffffff>;
  2082. };
  2083.  
  2084. pwm0@1 {
  2085. linux,phandle = <0x102>;
  2086. phandle = <0x102>;
  2087. allwinner,pins = "PD22";
  2088. allwinner,function = "pwm0";
  2089. allwinner,pname = "pwm_positive";
  2090. allwinner,muxsel = <0x7>;
  2091. allwinner,pull = <0x0>;
  2092. allwinner,drive = <0xffffffff>;
  2093. allwinner,data = <0xffffffff>;
  2094. };
  2095.  
  2096. pwm1@0 {
  2097. linux,phandle = <0x103>;
  2098. phandle = <0x103>;
  2099. allwinner,pins = "PB19";
  2100. allwinner,function = "pwm1";
  2101. allwinner,pname = "pwm_positive";
  2102. allwinner,muxsel = <0x2>;
  2103. allwinner,pull = <0x0>;
  2104. allwinner,drive = <0xffffffff>;
  2105. allwinner,data = <0xffffffff>;
  2106. };
  2107.  
  2108. pwm1@1 {
  2109. linux,phandle = <0x104>;
  2110. phandle = <0x104>;
  2111. allwinner,pins = "PB19";
  2112. allwinner,function = "pwm1";
  2113. allwinner,pname = "pwm_positive";
  2114. allwinner,muxsel = <0x7>;
  2115. allwinner,pull = <0x0>;
  2116. allwinner,drive = <0xffffffff>;
  2117. allwinner,data = <0xffffffff>;
  2118. };
  2119.  
  2120. csi0@0 {
  2121. linux,phandle = <0x107>;
  2122. phandle = <0x107>;
  2123. allwinner,pins = "PD0", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", "PD12", "PD13";
  2124. allwinner,function = "csi0";
  2125. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  2126. allwinner,muxsel = <0x4>;
  2127. allwinner,pull = <0xffffffff>;
  2128. allwinner,drive = <0xffffffff>;
  2129. allwinner,data = <0xffffffff>;
  2130. };
  2131.  
  2132. csi0@2 {
  2133. linux,phandle = <0x108>;
  2134. phandle = <0x108>;
  2135. allwinner,pins = "PD1";
  2136. allwinner,function = "csi0";
  2137. allwinner,pname = "csi0_mck";
  2138. allwinner,muxsel = <0x4>;
  2139. allwinner,pull = <0x0>;
  2140. allwinner,drive = <0x1>;
  2141. allwinner,data = <0x0>;
  2142. };
  2143.  
  2144. sdc0@0 {
  2145. linux,phandle = <0x109>;
  2146. phandle = <0x109>;
  2147. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  2148. allwinner,function = "sdc0";
  2149. allwinner,pname = "sdc0_d1", "sdc0_d0", "sdc0_clk", "sdc0_cmd", "sdc0_d3", "sdc0_d2";
  2150. allwinner,muxsel = <0x2>;
  2151. allwinner,pull = <0x1>;
  2152. allwinner,drive = <0x2>;
  2153. allwinner,data = <0xffffffff>;
  2154. };
  2155.  
  2156. sdc1@0 {
  2157. linux,phandle = <0x10a>;
  2158. phandle = <0x10a>;
  2159. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  2160. allwinner,function = "sdc1";
  2161. allwinner,pname = "sdc1_clk", "sdc1_cmd", "sdc1_d0", "sdc1_d1", "sdc1_d2", "sdc1_d3";
  2162. allwinner,muxsel = <0x2>;
  2163. allwinner,pull = <0x1>;
  2164. allwinner,drive = <0x3>;
  2165. allwinner,data = <0xffffffff>;
  2166. };
  2167.  
  2168. sdc2@0 {
  2169. linux,phandle = <0x10b>;
  2170. phandle = <0x10b>;
  2171. allwinner,pins = "PC1", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14";
  2172. allwinner,function = "sdc2";
  2173. allwinner,pname = "sdc2_ds", "sdc2_clk", "sdc2_cmd", "sdc2_d0", "sdc2_d1", "sdc2_d2", "sdc2_d3", "sdc2_d4", "sdc2_d5", "sdc2_d6", "sdc2_d7", "sdc2_emmc_rst";
  2174. allwinner,muxsel = <0x3>;
  2175. allwinner,pull = <0x1>;
  2176. allwinner,drive = <0x3>;
  2177. allwinner,data = <0xffffffff>;
  2178. };
  2179.  
  2180. Vdevice@0 {
  2181. linux,phandle = <0x10f>;
  2182. phandle = <0x10f>;
  2183. allwinner,pins = "PH9", "PH10";
  2184. allwinner,function = "Vdevice";
  2185. allwinner,pname = "Vdevice_0", "Vdevice_1";
  2186. allwinner,muxsel = <0x5>;
  2187. allwinner,pull = <0x1>;
  2188. allwinner,drive = <0x2>;
  2189. allwinner,data = <0xffffffff>;
  2190. };
  2191. };
  2192.  
  2193. dma-controller@03002000 {
  2194. compatible = "allwinner,sun50i-dma";
  2195. reg = <0x0 0x3002000 0x0 0x1000>;
  2196. interrupts = <0x0 0x2b 0x4>;
  2197. clocks = <0xc>;
  2198. #dma-cells = <0x1>;
  2199. };
  2200.  
  2201. mbus-controller@04002000 {
  2202. compatible = "allwinner,sun50i-mbus";
  2203. reg = <0x0 0x4002000 0x0 0x1000>;
  2204. #mbus-cells = <0x1>;
  2205. };
  2206.  
  2207. arisc {
  2208. compatible = "allwinner,sunxi-arisc";
  2209. #address-cells = <0x2>;
  2210. #size-cells = <0x2>;
  2211. clocks = <0xd 0xe 0x7 0x2>;
  2212. clock-names = "losc", "iosc", "hosc", "pll_periph0";
  2213. powchk_used = <0x0>;
  2214. power_reg = <0x2309621>;
  2215. system_power = <0x32>;
  2216. };
  2217.  
  2218. arisc_space {
  2219. compatible = "allwinner,arisc_space";
  2220. space1 = <0x48040000 0x0 0x14000>;
  2221. space2 = <0x48100000 0x18000 0x4000>;
  2222. space3 = <0x48104000 0x0 0x1000>;
  2223. space4 = <0x48105000 0x0 0x1000>;
  2224. };
  2225.  
  2226. standby_space {
  2227. compatible = "allwinner,standby_space";
  2228. space1 = <0x40020000 0x0 0x800>;
  2229. };
  2230.  
  2231. msgbox@03003000 {
  2232. compatible = "allwinner,msgbox";
  2233. clocks = <0xf>;
  2234. clock-names = "clk_msgbox";
  2235. reg = <0x0 0x3003000 0x0 0x1000>;
  2236. interrupts = <0x0 0x27 0x1>;
  2237. status = "okay";
  2238. };
  2239.  
  2240. hwspinlock@3004000 {
  2241. compatible = "allwinner,sunxi-hwspinlock";
  2242. clocks = <0x10 0x11>;
  2243. clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
  2244. reg = <0x0 0x3004000 0x0 0x1000>;
  2245. num-locks = <0x8>;
  2246. status = "okay";
  2247. };
  2248.  
  2249. s_cir@07040000 {
  2250. compatible = "allwinner,s_cir";
  2251. reg = <0x0 0x7040000 0x0 0x400>;
  2252. interrupts = <0x0 0x6d 0x4>;
  2253. pinctrl-names = "default";
  2254. pinctrl-0 = <0x12>;
  2255. clocks = <0x7 0x13>;
  2256. supply = [00];
  2257. supply_vol = [00];
  2258. status = "okay";
  2259. device_type = "s_cir0";
  2260. ir_protocol_used = <0x0>;
  2261. ir_power_key_code0 = <0x57>;
  2262. ir_addr_code0 = <0x9f00>;
  2263. ir_power_key_code1 = <0x1a>;
  2264. ir_addr_code1 = <0xfb04>;
  2265. ir_power_key_code2 = <0x14>;
  2266. ir_addr_code2 = <0x7f80>;
  2267. ir_power_key_code3 = <0x15>;
  2268. ir_addr_code3 = <0x7f80>;
  2269. ir_power_key_code4 = <0xb>;
  2270. ir_addr_code4 = <0xf708>;
  2271. ir_power_key_code5 = <0x3>;
  2272. ir_addr_code5 = <0xef>;
  2273. ir_power_key_code6 = <0xdc>;
  2274. ir_addr_code6 = <0x4cb3>;
  2275. ir_power_key_code7 = <0xa>;
  2276. ir_addr_code7 = <0x7748>;
  2277. ir_power_key_code8 = <0x45>;
  2278. ir_addr_code8 = <0xbd02>;
  2279. ir_power_key_code9 = <0x4d>;
  2280. ir_addr_code9 = <0xde21>;
  2281. ir_power_key_code10 = <0x18>;
  2282. ir_addr_code10 = <0xfe01>;
  2283. ir_power_key_code11 = <0x18>;
  2284. ir_addr_code11 = <0xff00>;
  2285. ir_power_key_code12 = <0x4d>;
  2286. ir_addr_code12 = <0xff40>;
  2287. ir_power_key_code13 = <0x88>;
  2288. ir_addr_code13 = <0xdd22>;
  2289. ir_power_key_code14 = <0xd>;
  2290. ir_addr_code14 = <0xbc00>;
  2291. ir_power_key_code15 = <0xd>;
  2292. ir_addr_code15 = <0xfc00>;
  2293. ir_power_key_code16 = <0x51>;
  2294. ir_addr_code16 = <0x7f80>;
  2295. rc5_ir_power_key_code0 = <0x1>;
  2296. rc5_ir_addr_code0 = <0x4>;
  2297. };
  2298.  
  2299. s_uart@7080000 {
  2300. compatible = "allwinner,s_uart";
  2301. reg = <0x0 0x7080000 0x0 0xd0>;
  2302. interrupts = <0x0 0x6a 0x4>;
  2303. pinctrl-names = "default";
  2304. status = "disabled";
  2305. device_type = "s_uart0";
  2306. pinctrl-0 = <0x10c>;
  2307. };
  2308.  
  2309. s_twi@1f03400 {
  2310. compatible = "allwinner,s_twi";
  2311. reg = <0x0 0x1f02400 0x0 0x20>;
  2312. interrupts = <0x0 0x2c 0x4>;
  2313. pinctrl-names = "default";
  2314. pinctrl-0 = <0x15>;
  2315. status = "okay";
  2316. };
  2317.  
  2318. s_jtag0 {
  2319. compatible = "allwinner,s_jtag";
  2320. pinctrl-names = "default";
  2321. status = "disabled";
  2322. device_type = "s_jtag0";
  2323. pinctrl-0 = <0x10e>;
  2324. };
  2325.  
  2326. box_start_os0 {
  2327. compatible = "allwinner,box_start_os";
  2328. start_type = <0x1>;
  2329. irkey_used = <0x1>;
  2330. pmukey_used = <0x1>;
  2331. pmukey_num = <0x0>;
  2332. led_power = <0x0>;
  2333. led_state = <0x0>;
  2334. status = "okay";
  2335. device_type = "box_start_os";
  2336. };
  2337.  
  2338. timer@03009000 {
  2339. compatible = "allwinner,sunxi-timer";
  2340. device_type = "timer";
  2341. reg = <0x0 0x3009000 0x0 0x400>;
  2342. interrupts = <0x0 0x30 0x4>;
  2343. clock-frequency = <0x16e3600>;
  2344. timer-prescale = <0x10>;
  2345. };
  2346.  
  2347. rtc@07000000 {
  2348. compatible = "allwinner,sun50iw6-rtc";
  2349. device_type = "rtc";
  2350. reg = <0x0 0x7000000 0x0 0x200>;
  2351. interrupts = <0x0 0x65 0x4>;
  2352. gpr_offset = <0x100>;
  2353. gpr_len = <0x8>;
  2354. };
  2355.  
  2356. watchdog@030090a0 {
  2357. compatible = "allwinner,sun50i-wdt";
  2358. reg = <0x0 0x30090a0 0x0 0x20>;
  2359. interrupts = <0x0 0x32 0x4>;
  2360. };
  2361.  
  2362. ve@01c0e000 {
  2363. compatible = "allwinner,sunxi-cedar-ve";
  2364. reg = <0x0 0x1c0e000 0x0 0x1000 0x0 0x3000000 0x0 0x10 0x0 0x3001000 0x0 0x1000>;
  2365. interrupts = <0x0 0x59 0x4>;
  2366. clocks = <0x17 0x18>;
  2367. iommus = <0x19 0x3 0x1>;
  2368. };
  2369.  
  2370. vp9@01c00000 {
  2371. compatible = "allwinner,sunxi-google-vp9";
  2372. reg = <0x0 0x1c00000 0x0 0x1000 0x0 0x3000000 0x0 0x10 0x0 0x3001000 0x0 0x1000>;
  2373. interrupts = <0x0 0x5a 0x4>;
  2374. clocks = <0x17 0x1a>;
  2375. #clocks = <0x1b 0x1a>;
  2376. iommus = <0x19 0x5 0x1>;
  2377. };
  2378.  
  2379. uart@05000000 {
  2380. compatible = "allwinner,sun50i-uart";
  2381. device_type = "uart0";
  2382. reg = <0x0 0x5000000 0x0 0x400>;
  2383. interrupts = <0x0 0x0 0x4>;
  2384. clocks = <0x1c>;
  2385. pinctrl-names = "default", "sleep";
  2386. uart0_port = <0x0>;
  2387. uart0_type = <0x2>;
  2388. status = "okay";
  2389. pinctrl-0 = <0xe9>;
  2390. pinctrl-1 = <0xea>;
  2391. };
  2392.  
  2393. uart@05000400 {
  2394. compatible = "allwinner,sun50i-uart";
  2395. device_type = "uart1";
  2396. reg = <0x0 0x5000400 0x0 0x400>;
  2397. interrupts = <0x0 0x1 0x4>;
  2398. clocks = <0x1f>;
  2399. pinctrl-names = "default", "sleep";
  2400. uart1_port = <0x1>;
  2401. uart1_type = <0x4>;
  2402. status = "okay";
  2403. pinctrl-0 = <0xeb>;
  2404. uart1_bt = <0x1>;
  2405. pinctrl-1 = <0xec>;
  2406. };
  2407.  
  2408. uart@05000800 {
  2409. compatible = "allwinner,sun50i-uart";
  2410. device_type = "uart2";
  2411. reg = <0x0 0x5000800 0x0 0x400>;
  2412. interrupts = <0x0 0x2 0x4>;
  2413. clocks = <0x22>;
  2414. pinctrl-names = "default", "sleep";
  2415. uart2_port = <0x2>;
  2416. uart2_type = <0x4>;
  2417. status = "disabled";
  2418. pinctrl-0 = <0xed>;
  2419. pinctrl-1 = <0xee>;
  2420. };
  2421.  
  2422. uart@05000c00 {
  2423. compatible = "allwinner,sun50i-uart";
  2424. device_type = "uart3";
  2425. reg = <0x0 0x5000c00 0x0 0x400>;
  2426. interrupts = <0x0 0x3 0x4>;
  2427. clocks = <0x25>;
  2428. pinctrl-names = "default", "sleep";
  2429. uart3_port = <0x3>;
  2430. uart3_type = <0x4>;
  2431. status = "disabled";
  2432. pinctrl-0 = <0xef>;
  2433. pinctrl-1 = <0xf0>;
  2434. };
  2435.  
  2436. twi@0x05002000 {
  2437. #address-cells = <0x1>;
  2438. #size-cells = <0x0>;
  2439. compatible = "allwinner,sun50i-twi";
  2440. device_type = "twi0";
  2441. reg = <0x0 0x5002000 0x0 0x400>;
  2442. interrupts = <0x0 0x4 0x4>;
  2443. clocks = <0x28>;
  2444. clock-frequency = <0x61a80>;
  2445. pinctrl-names = "default", "sleep";
  2446. status = "disabled";
  2447. pinctrl-0 = <0xe2>;
  2448. pinctrl-1 = <0xe3>;
  2449. };
  2450.  
  2451. twi@0x05002400 {
  2452. #address-cells = <0x1>;
  2453. #size-cells = <0x0>;
  2454. compatible = "allwinner,sun50i-twi";
  2455. device_type = "twi1";
  2456. reg = <0x0 0x5002400 0x0 0x400>;
  2457. interrupts = <0x0 0x5 0x4>;
  2458. clocks = <0x2b>;
  2459. clock-frequency = <0x30d40>;
  2460. pinctrl-names = "default", "sleep";
  2461. status = "disabled";
  2462. pinctrl-0 = <0xe4>;
  2463. pinctrl-1 = <0xe5>;
  2464. };
  2465.  
  2466. twi@0x05002800 {
  2467. #address-cells = <0x1>;
  2468. #size-cells = <0x0>;
  2469. compatible = "allwinner,sun50i-twi";
  2470. device_type = "twi2";
  2471. reg = <0x0 0x5002800 0x0 0x400>;
  2472. interrupts = <0x0 0x6 0x4>;
  2473. clocks = <0x2e>;
  2474. clock-frequency = <0x30d40>;
  2475. pinctrl-names = "default", "sleep";
  2476. status = "disabled";
  2477. pinctrl-0 = <0xe6>;
  2478. pinctrl-1 = <0xe7>;
  2479. };
  2480.  
  2481. twi@0x05002c00 {
  2482. #address-cells = <0x1>;
  2483. #size-cells = <0x0>;
  2484. compatible = "allwinner,sun50i-twi";
  2485. device_type = "twi3";
  2486. reg = <0x0 0x5002c00 0x0 0x400>;
  2487. interrupts = <0x0 0x7 0x4>;
  2488. clocks = <0x31>;
  2489. clock-frequency = <0x30d40>;
  2490. pinctrl-names = "default", "sleep";
  2491. pinctrl-1 = <0x33>;
  2492. status = "okay";
  2493. pinctrl-0 = <0xe8>;
  2494. };
  2495.  
  2496. usbc0@0 {
  2497. device_type = "usbc0";
  2498. compatible = "allwinner,sunxi-otg-manager";
  2499. usb_port_type = <0x1>;
  2500. usb_detect_type = <0x1>;
  2501. usb_host_init_state = <0x1>;
  2502. usb_regulator_io = "nocare";
  2503. usb_wakeup_suspend = <0x0>;
  2504. usb_luns = <0x3>;
  2505. usb_serial_unique = <0x0>;
  2506. usb_serial_number = "20080411";
  2507. rndis_wceis = <0x1>;
  2508. status = "okay";
  2509. usb_detect_mode = <0x0>;
  2510. usb_id_gpio;
  2511. usb_det_vbus_gpio;
  2512. usb_drv_vbus_gpio = <0xdb 0xb 0x5 0x1 0x0 0xffffffff 0x1>;
  2513. };
  2514.  
  2515. udc-controller@0x05100000 {
  2516. compatible = "allwinner,sunxi-udc";
  2517. reg = <0x0 0x5100000 0x0 0x1000 0x0 0x0 0x0 0x100>;
  2518. interrupts = <0x0 0x17 0x4>;
  2519. clocks = <0x34 0x35>;
  2520. status = "okay";
  2521. };
  2522.  
  2523. ehci0-controller@0x05101000 {
  2524. compatible = "allwinner,sunxi-ehci0";
  2525. reg = <0x0 0x5101000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2526. interrupts = <0x0 0x18 0x4>;
  2527. clocks = <0x34 0x36>;
  2528. hci_ctrl_no = <0x0>;
  2529. status = "okay";
  2530. };
  2531.  
  2532. ohci0-controller@0x05101400 {
  2533. compatible = "allwinner,sunxi-ohci0";
  2534. reg = <0x0 0x5101000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2535. interrupts = <0x0 0x19 0x4>;
  2536. clocks = <0x34 0x37 0x38 0x39 0x7 0xd>;
  2537. hci_ctrl_no = <0x0>;
  2538. status = "okay";
  2539. };
  2540.  
  2541. usbc1@0 {
  2542. device_type = "usbc1";
  2543. usb_host_init_state = <0x1>;
  2544. usb_regulator_io = "nocare";
  2545. usb_wakeup_suspend = <0x0>;
  2546. status = "okay";
  2547. usb_drv_vbus_gpio = <0xdb 0xb 0x5 0x1 0x0 0xffffffff 0x1>;
  2548. };
  2549.  
  2550. xhci-controller@0x05200000 {
  2551. compatible = "allwinner,sunxi-xhci";
  2552. reg = <0x0 0x5200000 0x0 0xfffff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2553. interrupts = <0x0 0x1a 0x4>;
  2554. clocks = <0x3a 0x3b>;
  2555. hci_ctrl_no = <0x1>;
  2556. status = "okay";
  2557. };
  2558.  
  2559. usbc2@0 {
  2560. device_type = "usbc2";
  2561. usb_host_init_state = <0x1>;
  2562. usb_regulator_io = "nocare";
  2563. usb_wakeup_suspend = <0x0>;
  2564. status = "disabled";
  2565. usb_drv_vbus_gpio;
  2566. };
  2567.  
  2568. ehci3-controller@0x05311000 {
  2569. compatible = "allwinner,sunxi-ehci3";
  2570. reg = <0x0 0x5311000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2571. interrupts = <0x0 0x1c 0x4>;
  2572. clocks = <0x3c 0x3d 0x3e 0x3e 0x3f>;
  2573. hci_ctrl_no = <0x3>;
  2574. status = "okay";
  2575. };
  2576.  
  2577. ohci3-controller@0x05311400 {
  2578. compatible = "allwinner,sunxi-ohci3";
  2579. reg = <0x0 0x5311000 0x0 0xfff 0x0 0x0 0x0 0x100 0x0 0x5100000 0x0 0x1000>;
  2580. interrupts = <0x0 0x1d 0x4>;
  2581. clocks = <0x3c 0x40 0x41 0x39 0x7 0xd>;
  2582. hci_ctrl_no = <0x3>;
  2583. status = "okay";
  2584. };
  2585.  
  2586. ac200_codec {
  2587. compatible = "allwinner,ac200_codec";
  2588. status = "okay";
  2589. device_type = "ac200_codec";
  2590. gpio-spk = <0xdb 0xb 0x6 0x1 0x1 0xffffffff 0xffffffff>;
  2591. };
  2592.  
  2593. daudio@0x05090000 {
  2594. compatible = "allwinner,sunxi-daudio";
  2595. reg = <0x0 0x5090000 0x0 0x74>;
  2596. clocks = <0x4 0x42>;
  2597. pinctrl-names = "default", "sleep";
  2598. pinctrl-0 = <0x43>;
  2599. pinctrl-1 = <0x44>;
  2600. pcm_lrck_period = <0x20>;
  2601. slot_width_select = <0x20>;
  2602. daudio_master = <0x4>;
  2603. audio_format = <0x1>;
  2604. signal_inversion = <0x1>;
  2605. tdm_config = <0x1>;
  2606. frametype = <0x0>;
  2607. tdm_num = <0x0>;
  2608. mclk_div = <0x0>;
  2609. status = "disabled";
  2610. linux,phandle = <0x59>;
  2611. phandle = <0x59>;
  2612. device_type = "daudio0";
  2613. };
  2614.  
  2615. daudio@0x05091000 {
  2616. compatible = "allwinner,sunxi-tdmhdmi";
  2617. reg = <0x0 0x5091000 0x0 0x74>;
  2618. clocks = <0x4 0x45>;
  2619. status = "okay";
  2620. linux,phandle = <0x5b>;
  2621. phandle = <0x5b>;
  2622. device_type = "audiohdmi";
  2623. };
  2624.  
  2625. daudio@0x05092000 {
  2626. compatible = "allwinner,sunxi-daudio";
  2627. reg = <0x0 0x5092000 0x0 0x74>;
  2628. clocks = <0x4 0x46>;
  2629. pinctrl-names = "default", "sleep";
  2630. pinctrl-0 = <0x47>;
  2631. pinctrl-1 = <0x48>;
  2632. pcm_lrck_period = <0x40>;
  2633. slot_width_select = <0x20>;
  2634. daudio_master = <0x4>;
  2635. audio_format = <0x4>;
  2636. signal_inversion = <0x3>;
  2637. tdm_config = <0x1>;
  2638. frametype = <0x0>;
  2639. tdm_num = <0x2>;
  2640. mclk_div = <0x1>;
  2641. status = "okay";
  2642. linux,phandle = <0x5d>;
  2643. phandle = <0x5d>;
  2644. device_type = "daudio2";
  2645. };
  2646.  
  2647. daudio@0x0508f000 {
  2648. compatible = "allwinner,sunxi-daudio";
  2649. reg = <0x0 0x508f000 0x0 0x74>;
  2650. clocks = <0x4 0x49>;
  2651. pinctrl-names = "default", "sleep";
  2652. pinctrl-0 = <0x4a>;
  2653. pinctrl-1 = <0x4b>;
  2654. pcm_lrck_period = <0x20>;
  2655. slot_width_select = <0x20>;
  2656. daudio_master = <0x4>;
  2657. audio_format = <0x1>;
  2658. signal_inversion = <0x1>;
  2659. tdm_config = <0x1>;
  2660. frametype = <0x0>;
  2661. tdm_num = <0x3>;
  2662. mclk_div = <0x1>;
  2663. status = "okay";
  2664. linux,phandle = <0x5f>;
  2665. phandle = <0x5f>;
  2666. device_type = "daudio3";
  2667. };
  2668.  
  2669. spdif-controller@0x05093000 {
  2670. compatible = "allwinner,sunxi-spdif";
  2671. reg = <0x0 0x5093000 0x0 0x40>;
  2672. clocks = <0x4 0x4c>;
  2673. pinctrl-names = "default", "sleep";
  2674. pinctrl-0 = <0x4d>;
  2675. pinctrl-1 = <0x4e>;
  2676. status = "okay";
  2677. linux,phandle = <0x61>;
  2678. phandle = <0x61>;
  2679. device_type = "spdif";
  2680. };
  2681.  
  2682. dmic-controller@0x05095000 {
  2683. compatible = "allwinner,sunxi-dmic";
  2684. reg = <0x0 0x5095000 0x0 0x50>;
  2685. clocks = <0x4 0x4f>;
  2686. pinctrl-names = "default", "sleep";
  2687. pinctrl-0 = <0x50>;
  2688. pinctrl-1 = <0x51>;
  2689. status = "disabled";
  2690. linux,phandle = <0x62>;
  2691. phandle = <0x62>;
  2692. device_type = "dmic";
  2693. };
  2694.  
  2695. cpudai0-controller@0x05097000 {
  2696. compatible = "allwinner,sunxi-ahub-cpudai";
  2697. reg = <0x0 0x5097000 0x0 0xadf>;
  2698. id = <0x0>;
  2699. status = "okay";
  2700. linux,phandle = <0x63>;
  2701. phandle = <0x63>;
  2702. };
  2703.  
  2704. cpudai1-controller@0x05097000 {
  2705. compatible = "allwinner,sunxi-ahub-cpudai";
  2706. reg = <0x0 0x5097000 0x0 0xadf>;
  2707. id = <0x1>;
  2708. status = "okay";
  2709. linux,phandle = <0x64>;
  2710. phandle = <0x64>;
  2711. };
  2712.  
  2713. cpudai2-controller@0x05097000 {
  2714. compatible = "allwinner,sunxi-ahub-cpudai";
  2715. reg = <0x0 0x5097000 0x0 0xadf>;
  2716. id = <0x2>;
  2717. status = "okay";
  2718. linux,phandle = <0x65>;
  2719. phandle = <0x65>;
  2720. };
  2721.  
  2722. ahub_codec@0x05097000 {
  2723. compatible = "allwinner,sunxi-ahub";
  2724. reg = <0x0 0x5097000 0x0 0xadf>;
  2725. clocks = <0x4 0x52>;
  2726. status = "okay";
  2727. linux,phandle = <0x66>;
  2728. phandle = <0x66>;
  2729. };
  2730.  
  2731. ahub_daudio0@0x05097000 {
  2732. compatible = "allwinner,sunxi-ahub-daudio";
  2733. reg = <0x0 0x5097000 0x0 0xadf>;
  2734. clocks = <0x4 0x52>;
  2735. pinctrl-names = "default", "sleep";
  2736. pinctrl-0 = <0x53>;
  2737. pinctrl-1 = <0x54>;
  2738. pinconfig = <0x1>;
  2739. frametype = <0x0>;
  2740. pcm_lrck_period = <0x20>;
  2741. slot_width_select = <0x20>;
  2742. daudio_master = <0x4>;
  2743. audio_format = <0x1>;
  2744. signal_inversion = <0x1>;
  2745. tdm_config = <0x1>;
  2746. tdm_num = <0x0>;
  2747. mclk_div = <0x0>;
  2748. status = "disable";
  2749. linux,phandle = <0x5a>;
  2750. phandle = <0x5a>;
  2751. };
  2752.  
  2753. ahub_daudio1@0x05097000 {
  2754. compatible = "allwinner,sunxi-ahub-daudio";
  2755. reg = <0x0 0x5097000 0x0 0xadf>;
  2756. clocks = <0x4 0x52>;
  2757. pinconfig = <0x0>;
  2758. frametype = <0x0>;
  2759. pcm_lrck_period = <0x20>;
  2760. slot_width_select = <0x20>;
  2761. daudio_master = <0x4>;
  2762. audio_format = <0x1>;
  2763. signal_inversion = <0x1>;
  2764. tdm_config = <0x1>;
  2765. tdm_num = <0x1>;
  2766. mclk_div = <0x0>;
  2767. status = "okay";
  2768. linux,phandle = <0x5c>;
  2769. phandle = <0x5c>;
  2770. };
  2771.  
  2772. ahub_daudio2@0x05097000 {
  2773. compatible = "allwinner,sunxi-ahub-daudio";
  2774. reg = <0x0 0x5097000 0x0 0xadf>;
  2775. clocks = <0x4 0x52>;
  2776. pinctrl-names = "default", "sleep";
  2777. pinctrl-0 = <0x55>;
  2778. pinctrl-1 = <0x56>;
  2779. pinconfig = <0x1>;
  2780. frametype = <0x0>;
  2781. pcm_lrck_period = <0x20>;
  2782. slot_width_select = <0x20>;
  2783. daudio_master = <0x4>;
  2784. audio_format = <0x1>;
  2785. signal_inversion = <0x1>;
  2786. tdm_config = <0x1>;
  2787. tdm_num = <0x2>;
  2788. mclk_div = <0x0>;
  2789. status = "okay";
  2790. linux,phandle = <0x5e>;
  2791. phandle = <0x5e>;
  2792. };
  2793.  
  2794. ahub_daudio3@0x05097000 {
  2795. compatible = "allwinner,sunxi-ahub-daudio";
  2796. reg = <0x0 0x5097000 0x0 0xadf>;
  2797. clocks = <0x4 0x52>;
  2798. pinctrl-names = "default", "sleep";
  2799. pinctrl-0 = <0x57>;
  2800. pinctrl-1 = <0x58>;
  2801. pinconfig = <0x1>;
  2802. frametype = <0x0>;
  2803. pcm_lrck_period = <0x20>;
  2804. slot_width_select = <0x20>;
  2805. daudio_master = <0x4>;
  2806. audio_format = <0x1>;
  2807. signal_inversion = <0x1>;
  2808. tdm_config = <0x1>;
  2809. tdm_num = <0x3>;
  2810. mclk_div = <0x4>;
  2811. status = "okay";
  2812. linux,phandle = <0x60>;
  2813. phandle = <0x60>;
  2814. };
  2815.  
  2816. sound@0 {
  2817. compatible = "allwinner,sunxi-daudio0-machine";
  2818. sunxi,daudio-controller = <0x59>;
  2819. sunxi,cpudai-controller = <0x5a>;
  2820. status = "disabled";
  2821. device_type = "snddaudio0";
  2822. };
  2823.  
  2824. sound@1 {
  2825. compatible = "allwinner,sunxi-hdmi-machine";
  2826. sunxi,hdmi-controller = <0x5b>;
  2827. sunxi,cpudai-controller = <0x5c>;
  2828. status = "okay";
  2829. device_type = "sndhdmi";
  2830. };
  2831.  
  2832. sound@2 {
  2833. compatible = "allwinner,sunxi-daudio2-machine";
  2834. sunxi,daudio-controller = <0x5d>;
  2835. sunxi,cpudai-controller = <0x5e>;
  2836. status = "okay";
  2837. device_type = "snddaudio2";
  2838. };
  2839.  
  2840. sound@3 {
  2841. compatible = "allwinner,sunxi-daudio3-machine";
  2842. sunxi,daudio-controller = <0x5f>;
  2843. sunxi,cpudai-controller = <0x60>;
  2844. sunxi,snddaudio-codec = "acx00-codec";
  2845. sunxi,snddaudio-codec-dai = "acx00-dai";
  2846. status = "okay";
  2847. device_type = "snddaudio3";
  2848. };
  2849.  
  2850. sound@4 {
  2851. compatible = "allwinner,sunxi-spdif-machine";
  2852. sunxi,spdif-controller = <0x61>;
  2853. status = "okay";
  2854. device_type = "sndspdif";
  2855. };
  2856.  
  2857. sound@5 {
  2858. compatible = "allwinner,sunxi-dmic-machine";
  2859. sunxi,dmic-controller = <0x62>;
  2860. status = "disabled";
  2861. device_type = "snddmic";
  2862. };
  2863.  
  2864. sound@6 {
  2865. compatible = "allwinner,sunxi-ahub-machine";
  2866. sunxi,cpudai-controller0 = <0x63>;
  2867. sunxi,cpudai-controller1 = <0x64>;
  2868. sunxi,cpudai-controller2 = <0x65>;
  2869. sunxi,audio-codec = <0x66>;
  2870. status = "okay";
  2871. };
  2872.  
  2873. spi@05010000 {
  2874. #address-cells = <0x1>;
  2875. #size-cells = <0x0>;
  2876. compatible = "allwinner,sun50i-spi";
  2877. device_type = "spi0";
  2878. reg = <0x0 0x5010000 0x0 0x1000>;
  2879. interrupts = <0x0 0xa 0x4>;
  2880. clocks = <0x2 0x67>;
  2881. clock-frequency = <0x5f5e100>;
  2882. pinctrl-names = "default", "sleep";
  2883. spi0_cs_number = <0x1>;
  2884. spi0_cs_bitmap = <0x1>;
  2885. status = "disabled";
  2886. pinctrl-0 = <0xf1 0xf2>;
  2887. pinctrl-1 = <0xf3 0xf4>;
  2888. };
  2889.  
  2890. spi@05011000 {
  2891. #address-cells = <0x1>;
  2892. #size-cells = <0x0>;
  2893. compatible = "allwinner,sun50i-spi";
  2894. device_type = "spi1";
  2895. reg = <0x0 0x5011000 0x0 0x1000>;
  2896. interrupts = <0x0 0xb 0x4>;
  2897. clocks = <0x2 0x6b>;
  2898. clock-frequency = <0x5f5e100>;
  2899. pinctrl-names = "default", "sleep";
  2900. spi1_cs_number = <0x1>;
  2901. spi1_cs_bitmap = <0x1>;
  2902. status = "disabled";
  2903. pinctrl-0 = <0xf5 0xf6>;
  2904. pinctrl-1 = <0xf7 0xf8>;
  2905. };
  2906.  
  2907. pcie@0x05400000 {
  2908. #address-cells = <0x3>;
  2909. #size-cells = <0x2>;
  2910. compatible = "allwinner,sun50i-pcie";
  2911. reg = <0x0 0x5400000 0x0 0x2000 0x0 0x5410000 0x0 0x10000>;
  2912. reg-names = "dbi", "config";
  2913. device_type = "pci";
  2914. ranges = <0x800 0x0 0x5410000 0x0 0x5410000 0x0 0x10000 0x81000000 0x0 0x0 0x0 0x5600000 0x0 0x10000 0x82000000 0x0 0x50100000 0x0 0x5500000 0x0 0x800000>;
  2915. num-lanes = <0x1>;
  2916. interrupts = <0x0 0x7f 0x4 0x0 0x7e 0x4>;
  2917. interrupt-names = "msi";
  2918. clocks = <0x6f 0x70 0x71 0x72 0x73 0x74>;
  2919. #interrupt-cells = <0x1>;
  2920. interrupt-map-mask = <0x0 0x0 0x0 0x0>;
  2921. interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x7f 0x4>;
  2922. status = "okay";
  2923. pcie_rest = <0x80 0x6 0x3 0x1 0xffffffff 0xffffffff 0xffffffff>;
  2924. pcie_power = <0xdb 0xb 0x8 0x1 0xffffffff 0xffffffff 0xffffffff>;
  2925. pcie_reg = <0xdb 0xc 0x3 0x1 0xffffffff 0xffffffff 0xffffffff>;
  2926. pcie_iodvdd = <0x708>;
  2927. pcie_speed_gen = <0x2>;
  2928. pcie_vdd = "vdd_pcie";
  2929. pcie_vdd_vol = <0xdbba0>;
  2930. pcie_vcc = "vcc-pcie";
  2931. pcie_vcc_vol = <0x1b7740>;
  2932. pcie_vcc_slot = "vcc-pcie-slot";
  2933. pcie_vcc_slot_vol = <0x325aa0>;
  2934. };
  2935.  
  2936. sdmmc@04022000 {
  2937. compatible = "allwinner,sunxi-mmc-v4p6x";
  2938. device_type = "sdc2";
  2939. reg = <0x0 0x4022000 0x0 0x1000>;
  2940. interrupts = <0x0 0x25 0x104>;
  2941. clocks = <0x7 0x75 0x76 0x77 0x78>;
  2942. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2943. pinctrl-names = "default", "sleep";
  2944. pinctrl-1 = <0x7a>;
  2945. bus-width = <0x8>;
  2946. max-frequency = <0x8f0d180>;
  2947. sdc_tm4_sm0_freq0 = <0x0>;
  2948. sdc_tm4_sm0_freq1 = <0x0>;
  2949. sdc_tm4_sm1_freq0 = <0x0>;
  2950. sdc_tm4_sm1_freq1 = <0x0>;
  2951. sdc_tm4_sm2_freq0 = <0x0>;
  2952. sdc_tm4_sm2_freq1 = <0x0>;
  2953. sdc_tm4_sm3_freq0 = <0x5000000>;
  2954. sdc_tm4_sm3_freq1 = <0x405>;
  2955. sdc_tm4_sm4_freq0 = <0x50000>;
  2956. sdc_tm4_sm4_freq1 = <0x408>;
  2957. status = "okay";
  2958. non-removable;
  2959. pinctrl-0 = <0x10b>;
  2960. cd-gpios;
  2961. sunxi-power-save-mode;
  2962. sunxi-dis-signal-vol-sw;
  2963. mmc-ddr-1_8v;
  2964. mmc-hs200-1_8v;
  2965. mmc-hs400-1_8v;
  2966. vmmc = "vcc-emmcv";
  2967. vqmmc = "vcc-emmcvq18";
  2968. vdmmc = "none";
  2969. };
  2970.  
  2971. sdmmc@04020000 {
  2972. compatible = "allwinner,sunxi-mmc-v4p1x";
  2973. device_type = "sdc0";
  2974. reg = <0x0 0x4020000 0x0 0x1000>;
  2975. interrupts = <0x0 0x23 0x104>;
  2976. clocks = <0x7 0x75 0x7b 0x7c 0x7d>;
  2977. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2978. pinctrl-names = "default", "sleep";
  2979. pinctrl-1 = <0x7f>;
  2980. max-frequency = <0x2faf080>;
  2981. bus-width = <0x4>;
  2982. status = "okay";
  2983. pinctrl-0 = <0x109>;
  2984. cd-gpios = <0x80 0x5 0x6 0x0 0x1 0x2 0xffffffff>;
  2985. sunxi-power-save-mode;
  2986. sunxi-dis-signal-vol-sw;
  2987. vmmc = "vcc-sdcv";
  2988. vqmmc = "vcc-sdcvq33";
  2989. vdmmc = "vcc-sdcvd";
  2990. ctl-spec-caps = <0x80>;
  2991. };
  2992.  
  2993. sdmmc@04021000 {
  2994. compatible = "allwinner,sunxi-mmc-v4p1x";
  2995. device_type = "sdc1";
  2996. reg = <0x0 0x4021000 0x0 0x1000>;
  2997. interrupts = <0x0 0x24 0x104>;
  2998. clocks = <0x7 0x75 0x81 0x82 0x83>;
  2999. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  3000. pinctrl-names = "default", "sleep";
  3001. pinctrl-1 = <0x85>;
  3002. max-frequency = <0x8f0d180>;
  3003. bus-width = <0x4>;
  3004. sunxi-dly-52M-ddr4 = <0x1 0x0 0x0 0x0 0x2>;
  3005. sunxi-dly-104M = <0x1 0x0 0x0 0x0 0x1>;
  3006. sunxi-dly-208M = <0x1 0x0 0x0 0x0 0x1>;
  3007. status = "okay";
  3008. pinctrl-0 = <0x10a>;
  3009. sd-uhs-sdr50;
  3010. sd-uhs-ddr50;
  3011. sd-uhs-sdr104;
  3012. cap-sdio-irq;
  3013. keep-power-in-suspend;
  3014. ignore-pm-notify;
  3015. };
  3016.  
  3017. disp@01000000 {
  3018. compatible = "allwinner,sunxi-disp";
  3019. reg = <0x0 0x1000000 0x0 0x1400000 0x0 0x6510000 0x0 0x100 0x0 0x6511000 0x0 0x800 0x0 0x6515000 0x0 0x800>;
  3020. interrupts = <0x0 0x41 0x104 0x0 0x42 0x104>;
  3021. clocks = <0x86 0x87 0x88 0x89>;
  3022. boot_disp = <0x0>;
  3023. fb_base = <0x0>;
  3024. iommus = <0x19 0x0 0x0>;
  3025. status = "okay";
  3026. device_type = "disp";
  3027. disp_init_enable = <0x1>;
  3028. disp_mode = <0x0>;
  3029. screen0_output_type = <0x3>;
  3030. screen0_output_mode = <0xa>;
  3031. screen0_output_format = <0x1>;
  3032. screen0_output_bits = <0x0>;
  3033. screen0_output_eotf = <0x4>;
  3034. screen0_output_cs = <0x101>;
  3035. screen0_output_dvi_hdmi = <0x2>;
  3036. screen0_output_range = <0x2>;
  3037. screen0_output_scan = <0x0>;
  3038. screen0_output_aspect_ratio = <0x8>;
  3039. screen1_output_type = <0x3>;
  3040. screen1_output_mode = <0x2>;
  3041. screen1_output_format = <0x1>;
  3042. screen1_output_bits = <0x0>;
  3043. screen1_output_eotf = <0x4>;
  3044. screen1_output_cs = <0x104>;
  3045. screen1_output_dvi_hdmi = <0x2>;
  3046. screen1_output_range = <0x2>;
  3047. screen1_output_scan = <0x0>;
  3048. screen1_output_aspect_ratio = <0x8>;
  3049. dev0_output_type = <0x4>;
  3050. dev0_output_mode = <0xa>;
  3051. dev0_screen_id = <0x0>;
  3052. dev0_do_hpd = <0x1>;
  3053. dev1_output_type = <0x2>;
  3054. dev1_output_mode = <0xb>;
  3055. dev1_screen_id = <0x1>;
  3056. dev1_do_hpd = <0x1>;
  3057. dev2_output_type = <0x0>;
  3058. def_output_dev = <0x0>;
  3059. hdmi_mode_check = <0x1>;
  3060. fb0_format = <0x0>;
  3061. fb0_width = <0x500>;
  3062. fb0_height = <0x2d0>;
  3063. fb1_format = <0x0>;
  3064. fb1_width = <0x0>;
  3065. fb1_height = <0x0>;
  3066. disp_para_zone = <0x1>;
  3067. };
  3068.  
  3069. lcd0@01c0c000 {
  3070. compatible = "allwinner,sunxi-lcd0";
  3071. pinctrl-names = "active", "sleep";
  3072. status = "okay";
  3073. device_type = "lcd0";
  3074. lcd_used = <0x0>;
  3075. lcd_driver_name = "default_lcd";
  3076. lcd_backlight = <0x32>;
  3077. lcd_if = <0x3>;
  3078. lcd_x = <0x500>;
  3079. lcd_y = <0x320>;
  3080. lcd_width = <0x96>;
  3081. lcd_height = <0x5e>;
  3082. lcd_dclk_freq = <0x46>;
  3083. lcd_pwm_used = <0x1>;
  3084. lcd_pwm_ch = <0x0>;
  3085. lcd_pwm_freq = <0xc350>;
  3086. lcd_pwm_pol = <0x1>;
  3087. lcd_pwm_max_limit = <0xff>;
  3088. lcd_hbp = <0x14>;
  3089. lcd_ht = <0x58a>;
  3090. lcd_hspw = <0xa>;
  3091. lcd_vbp = <0xa>;
  3092. lcd_vt = <0x32e>;
  3093. lcd_vspw = <0x5>;
  3094. lcd_lvds_if = <0x0>;
  3095. lcd_lvds_colordepth = <0x1>;
  3096. lcd_lvds_mode = <0x0>;
  3097. lcd_frm = <0x1>;
  3098. lcd_hv_clk_phase = <0x0>;
  3099. lcd_hv_sync_polarity = <0x0>;
  3100. lcd_gamma_en = <0x0>;
  3101. lcd_bright_curve_en = <0x0>;
  3102. lcd_cmap_en = <0x0>;
  3103. lcd_bl_en = <0x80 0x3 0x17 0x1 0x0 0xffffffff 0x1>;
  3104. lcd_bl_en_power = "none";
  3105. lcd_power = "vcc-lcd-0";
  3106. lcd_fix_power = "vcc-dsi-33";
  3107. pinctrl-0 = <0xfc>;
  3108. lcd_pin_power = "vcc-pd";
  3109. pinctrl-1 = <0xfd>;
  3110. };
  3111.  
  3112. hdmi@06000000 {
  3113. compatible = "allwinner,sunxi-hdmi";
  3114. reg = <0x0 0x6000000 0x0 0x100000>;
  3115. interrupts = <0x0 0x40 0x0>;
  3116. clocks = <0x8a 0x8b 0x8c 0x8d>;
  3117. pinctrl-names = "ddc_active", "ddc_sleep", "cec_active", "cec_sleep";
  3118. pinctrl-1 = <0x8f>;
  3119. pinctrl-2 = <0x90>;
  3120. pinctrl-3 = <0x91>;
  3121. status = "okay";
  3122. device_type = "hdmi";
  3123. hdmi_hdcp_enable = <0x0>;
  3124. hdmi_hdcp22_enable = <0x0>;
  3125. hdmi_cts_compatibility = <0x0>;
  3126. hdmi_cec_support = <0x1>;
  3127. hdmi_cec_super_standby = <0x1>;
  3128. hdmi_skip_bootedid = <0x1>;
  3129. pinctrl-0 = <0xfe>;
  3130. ddc_en_io_ctrl = <0x1>;
  3131. ddc_io_ctrl = <0x80 0x7 0x2 0x1 0xffffffff 0xffffffff 0x0>;
  3132. };
  3133.  
  3134. tv0@01c94000 {
  3135. compatible = "allwinner,sunxi-tv";
  3136. reg = <0x0 0x1e40000 0x0 0x1000>;
  3137. status = "disabled";
  3138. device_type = "tv0";
  3139. dac_src0 = <0x0>;
  3140. dac_type0 = <0x0>;
  3141. interface = <0x1>;
  3142. };
  3143.  
  3144. tr@01000000 {
  3145. compatible = "allwinner,sun50i-tr";
  3146. reg = <0x0 0x1000000 0x0 0x200bc>;
  3147. interrupts = <0x0 0x60 0x104>;
  3148. clocks = <0x86>;
  3149. status = "okay";
  3150. };
  3151.  
  3152. pwm@0300a000 {
  3153. compatible = "allwinner,sunxi-pwm";
  3154. reg = <0x0 0x300a000 0x0 0x3c>;
  3155. clocks = <0x92>;
  3156. pwm-number = <0x2>;
  3157. pwm-base = <0x0>;
  3158. pwms = <0x93 0x94>;
  3159. };
  3160.  
  3161. pwm0@0300a000 {
  3162. compatible = "allwinner,sunxi-pwm0";
  3163. pinctrl-names = "active", "sleep";
  3164. reg_base = <0x300a000>;
  3165. reg_busy_offset = <0x0>;
  3166. reg_busy_shift = <0x1c>;
  3167. reg_enable_offset = <0x0>;
  3168. reg_enable_shift = <0x4>;
  3169. reg_clk_gating_offset = <0x0>;
  3170. reg_clk_gating_shift = <0x6>;
  3171. reg_bypass_offset = <0x0>;
  3172. reg_bypass_shift = <0x9>;
  3173. reg_pulse_start_offset = <0x0>;
  3174. reg_pulse_start_shift = <0x8>;
  3175. reg_mode_offset = <0x0>;
  3176. reg_mode_shift = <0x7>;
  3177. reg_polarity_offset = <0x0>;
  3178. reg_polarity_shift = <0x5>;
  3179. reg_period_offset = <0x4>;
  3180. reg_period_shift = <0x10>;
  3181. reg_period_width = <0x10>;
  3182. reg_active_offset = <0x4>;
  3183. reg_active_shift = <0x0>;
  3184. reg_active_width = <0x10>;
  3185. reg_prescal_offset = <0x0>;
  3186. reg_prescal_shift = <0x0>;
  3187. reg_prescal_width = <0x4>;
  3188. linux,phandle = <0x93>;
  3189. phandle = <0x93>;
  3190. device_type = "pwm0";
  3191. pwm_used = <0x1>;
  3192. pinctrl-0 = <0x101>;
  3193. pinctrl-1 = <0x102>;
  3194. };
  3195.  
  3196. pwm1@0300a000 {
  3197. compatible = "allwinner,sunxi-pwm1";
  3198. pinctrl-names = "active", "sleep";
  3199. reg_base = <0x300a000>;
  3200. reg_busy_offset = <0x0>;
  3201. reg_busy_shift = <0x1d>;
  3202. reg_enable_offset = <0x0>;
  3203. reg_enable_shift = <0x13>;
  3204. reg_clk_gating_offset = <0x0>;
  3205. reg_clk_gating_shift = <0x15>;
  3206. reg_bypass_offset = <0x0>;
  3207. reg_bypass_shift = <0x18>;
  3208. reg_pulse_start_offset = <0x0>;
  3209. reg_pulse_start_shift = <0x17>;
  3210. reg_mode_offset = <0x0>;
  3211. reg_mode_shift = <0x16>;
  3212. reg_polarity_offset = <0x0>;
  3213. reg_polarity_shift = <0x14>;
  3214. reg_period_offset = <0x8>;
  3215. reg_period_shift = <0x10>;
  3216. reg_period_width = <0x10>;
  3217. reg_active_offset = <0x8>;
  3218. reg_active_shift = <0x0>;
  3219. reg_active_width = <0x10>;
  3220. reg_prescal_offset = <0x0>;
  3221. reg_prescal_shift = <0xf>;
  3222. reg_prescal_width = <0x4>;
  3223. linux,phandle = <0x94>;
  3224. phandle = <0x94>;
  3225. device_type = "pwm1";
  3226. pwm_used = <0x1>;
  3227. pinctrl-0 = <0x103>;
  3228. pinctrl-1 = <0x104>;
  3229. };
  3230.  
  3231. s_pwm@07020c00 {
  3232. compatible = "allwinner,sunxi-s_pwm";
  3233. reg = <0x0 0x7020c00 0x0 0x3c>;
  3234. clocks = <0x95>;
  3235. pwm-number = <0x1>;
  3236. pwm-base = <0x10>;
  3237. pwms = <0x96>;
  3238. };
  3239.  
  3240. spwm0@07020c00 {
  3241. compatible = "allwinner,sunxi-pwm16";
  3242. pinctrl-names = "active", "sleep";
  3243. reg_base = <0x7020c00>;
  3244. reg_busy_offset = <0x0>;
  3245. reg_busy_shift = <0x1c>;
  3246. reg_enable_offset = <0x0>;
  3247. reg_enable_shift = <0x4>;
  3248. reg_clk_gating_offset = <0x0>;
  3249. reg_clk_gating_shift = <0x6>;
  3250. reg_bypass_offset = <0x0>;
  3251. reg_bypass_shift = <0x9>;
  3252. reg_pulse_start_offset = <0x0>;
  3253. reg_pulse_start_shift = <0x8>;
  3254. reg_mode_offset = <0x0>;
  3255. reg_mode_shift = <0x7>;
  3256. reg_polarity_offset = <0x0>;
  3257. reg_polarity_shift = <0x5>;
  3258. reg_period_offset = <0x4>;
  3259. reg_period_shift = <0x10>;
  3260. reg_period_width = <0x10>;
  3261. reg_active_offset = <0x4>;
  3262. reg_active_shift = <0x0>;
  3263. reg_active_width = <0x10>;
  3264. reg_prescal_offset = <0x0>;
  3265. reg_prescal_shift = <0x0>;
  3266. reg_prescal_width = <0x4>;
  3267. linux,phandle = <0x96>;
  3268. phandle = <0x96>;
  3269. };
  3270.  
  3271. boot_disp {
  3272. compatible = "allwinner,boot_disp";
  3273. device_type = "boot_disp";
  3274. auto_hpd = <0x1>;
  3275. output_disp = <0x0>;
  3276. output_type = <0x3>;
  3277. output_mode = <0xb>;
  3278. hdmi_channel = <0x0>;
  3279. hdmi_mode = <0x4>;
  3280. };
  3281.  
  3282. ac200 {
  3283. compatible = "allwinner,sunxi-ac200";
  3284. clocks = <0x88>;
  3285. pinctrl-names = "active", "sleep", "ccir_clk_active", "ccir_clk_sleep";
  3286. pinctrl-2 = <0x97>;
  3287. pinctrl-3 = <0x98>;
  3288. status = "okay";
  3289. device_type = "ac200";
  3290. tv_used = <0x1>;
  3291. tv_module_name = "tv_ac200";
  3292. tv_twi_used = <0x1>;
  3293. tv_twi_id = <0x3>;
  3294. tv_twi_addr = <0x10>;
  3295. tv_pwm_ch = <0x1>;
  3296. tv_clk_div = <0x5>;
  3297. tv_regulator_name = "vcc-audio-33";
  3298. pinctrl-0 = <0xff>;
  3299. pinctrl-1 = <0x100>;
  3300. };
  3301.  
  3302. vind@0 {
  3303. compatible = "allwinner,sunxi-vin-media", "simple-bus";
  3304. #address-cells = <0x2>;
  3305. #size-cells = <0x2>;
  3306. ranges;
  3307. device_id = <0x0>;
  3308. reg = <0x0 0x6620000 0x0 0x1000>;
  3309. clocks = <0x99 0x2 0x9a 0x7 0x2>;
  3310. pinctrl-names = "mclk0-default", "mclk0-sleep";
  3311. pinctrl-0 = <0x9b>;
  3312. pinctrl-1 = <0x9c>;
  3313. status = "okay";
  3314.  
  3315. cci@0x0662e000 {
  3316. compatible = "allwinner,sunxi-csi_cci";
  3317. reg = <0x0 0x662e000 0x0 0x1000>;
  3318. interrupts = <0x0 0x48 0x4>;
  3319. clocks = <0x9d>;
  3320. pinctrl-names = "default", "sleep";
  3321. pinctrl-0 = <0x9e>;
  3322. pinctrl-1 = <0x9f>;
  3323. device_id = <0x0>;
  3324. status = "okay";
  3325. };
  3326.  
  3327. csi@0x06621000 {
  3328. device_type = "csi0";
  3329. compatible = "allwinner,sunxi-csi";
  3330. reg = <0x0 0x6621000 0x0 0x1000>;
  3331. interrupts = <0x0 0x46 0x4>;
  3332. pinctrl-names = "default", "sleep";
  3333. pinctrl-1 = <0xa1>;
  3334. device_id = <0x0>;
  3335. iommus = <0x19 0x4 0x1>;
  3336. status = "disabled";
  3337. csi0_sensor_list = <0x0>;
  3338. pinctrl-0 = <0x107 0x108>;
  3339.  
  3340. csi0_dev0 {
  3341. device_type = "csi0_dev0";
  3342. status = "disabled";
  3343. csi0_dev0_mname = "ov5640";
  3344. csi0_dev0_twi_addr = <0x78>;
  3345. csi0_dev0_pos = "rear";
  3346. csi0_dev0_isp_used = <0x1>;
  3347. csi0_dev0_fmt = <0x0>;
  3348. csi0_dev0_stby_mode = <0x0>;
  3349. csi0_dev0_vflip = <0x0>;
  3350. csi0_dev0_hflip = <0x0>;
  3351. csi0_dev0_iovdd = "iovdd-csi";
  3352. csi0_dev0_iovdd_vol = <0x2ab980>;
  3353. csi0_dev0_avdd = "avdd-csi";
  3354. csi0_dev0_avdd_vol = <0x2ab980>;
  3355. csi0_dev0_dvdd = "dvdd-csi-18";
  3356. csi0_dev0_dvdd_vol = <0x16e360>;
  3357. csi0_dev0_afvdd = "afvcc-csi";
  3358. csi0_dev0_afvdd_vol = <0x2ab980>;
  3359. csi0_dev0_power_en;
  3360. csi0_dev0_reset = <0x80 0x4 0xe 0x1 0x0 0x1 0x0>;
  3361. csi0_dev0_pwdn = <0x80 0x4 0xf 0x1 0x0 0x1 0x0>;
  3362. csi0_dev0_flash_used = <0x0>;
  3363. csi0_dev0_flash_type = <0x2>;
  3364. csi0_dev0_flash_en;
  3365. csi0_dev0_flash_mode;
  3366. csi0_dev0_flvdd;
  3367. csi0_dev0_flvdd_vol;
  3368. csi0_dev0_af_pwdn;
  3369. csi0_dev0_act_used = <0x0>;
  3370. csi0_dev0_act_name = "ad5820_act";
  3371. csi0_dev0_act_slave = <0x18>;
  3372. };
  3373.  
  3374. csi0_dev1 {
  3375. device_type = "csi0_dev1";
  3376. status = "disabled";
  3377. csi0_dev1_mname;
  3378. csi0_dev1_twi_addr = <0x78>;
  3379. csi0_dev1_pos = "rear";
  3380. csi0_dev1_isp_used = <0x1>;
  3381. csi0_dev1_fmt = <0x0>;
  3382. csi0_dev1_stby_mode = <0x0>;
  3383. csi0_dev1_vflip = <0x0>;
  3384. csi0_dev1_hflip = <0x0>;
  3385. csi0_dev1_iovdd = "iovdd-csi";
  3386. csi0_dev1_iovdd_vol = <0x2ab980>;
  3387. csi0_dev1_avdd = "avdd-csi";
  3388. csi0_dev1_avdd_vol = <0x2ab980>;
  3389. csi0_dev1_dvdd = "dvdd-csi-18";
  3390. csi0_dev1_dvdd_vol = <0x16e360>;
  3391. csi0_dev1_afvdd = "afvcc-csi";
  3392. csi0_dev1_afvdd_vol = <0x2ab980>;
  3393. csi0_dev1_power_en;
  3394. csi0_dev1_reset;
  3395. csi0_dev1_pwdn;
  3396. csi0_dev1_flash_used = <0x0>;
  3397. csi0_dev1_flash_type = <0x2>;
  3398. csi0_dev1_flash_en;
  3399. csi0_dev1_flash_mode;
  3400. csi0_dev1_flvdd;
  3401. csi0_dev1_flvdd_vol;
  3402. csi0_dev1_af_pwdn;
  3403. csi0_dev1_act_used = <0x0>;
  3404. csi0_dev1_act_name = "ad5820_act";
  3405. csi0_dev1_act_slave = <0x18>;
  3406. };
  3407. };
  3408.  
  3409. csi@1 {
  3410. device_type = "csi1";
  3411. compatible = "allwinner,sunxi-csi";
  3412. device_id = <0x1>;
  3413. iommus = <0x19 0x4 0x1>;
  3414. status = "disabled";
  3415. };
  3416.  
  3417. mipi@0 {
  3418. compatible = "allwinner,sunxi-mipi";
  3419. device_id = <0x0>;
  3420. status = "disabled";
  3421. };
  3422.  
  3423. mipi@1 {
  3424. compatible = "allwinner,sunxi-mipi";
  3425. device_id = <0x1>;
  3426. status = "disabled";
  3427. };
  3428.  
  3429. isp@0 {
  3430. compatible = "allwinner,sunxi-isp";
  3431. reg = <0x0 0x2100000 0x0 0x800>;
  3432. interrupts = <0x0 0x56 0x4>;
  3433. device_id = <0x0>;
  3434. iommus = <0x19 0x4 0x1>;
  3435. status = "okay";
  3436. linux,phandle = <0xa4>;
  3437. phandle = <0xa4>;
  3438. };
  3439.  
  3440. isp@1 {
  3441. compatible = "allwinner,sunxi-isp";
  3442. reg = <0x0 0x2100800 0x0 0x800>;
  3443. device_id = <0x1>;
  3444. iommus = <0x19 0x4 0x1>;
  3445. status = "disabled";
  3446. linux,phandle = <0xa5>;
  3447. phandle = <0xa5>;
  3448. };
  3449.  
  3450. scaler@0x02101000 {
  3451. compatible = "allwinner,sunxi-scaler";
  3452. reg = <0x0 0x2101000 0x0 0x400>;
  3453. device_id = <0x0>;
  3454. iommus = <0x19 0x4 0x1>;
  3455. status = "okay";
  3456. };
  3457.  
  3458. scaler@0x02101400 {
  3459. compatible = "allwinner,sunxi-scaler";
  3460. reg = <0x0 0x2101400 0x0 0x400>;
  3461. device_id = <0x1>;
  3462. iommus = <0x19 0x4 0x1>;
  3463. status = "okay";
  3464. };
  3465.  
  3466. scaler@2 {
  3467. compatible = "allwinner,sunxi-scaler";
  3468. device_id = <0x2>;
  3469. iommus = <0x19 0x4 0x1>;
  3470. status = "disabled";
  3471. };
  3472.  
  3473. scaler@3 {
  3474. compatible = "allwinner,sunxi-scaler";
  3475. device_id = <0x3>;
  3476. iommus = <0x19 0x4 0x1>;
  3477. status = "disabled";
  3478. };
  3479.  
  3480. actuator@0 {
  3481. device_type = "actuator0";
  3482. compatible = "allwinner,sunxi-actuator";
  3483. actuator0_name = "ad5820_act";
  3484. actuator0_slave = <0x18>;
  3485. actuator0_af_pwdn;
  3486. actuator0_afvdd = "afvcc-csi";
  3487. actuator0_afvdd_vol = <0x2ab980>;
  3488. status = "disabled";
  3489. linux,phandle = <0xa3>;
  3490. phandle = <0xa3>;
  3491. };
  3492.  
  3493. flash@0 {
  3494. device_type = "flash0";
  3495. compatible = "allwinner,sunxi-flash";
  3496. flash0_type = <0x2>;
  3497. flash0_en;
  3498. flash0_mode;
  3499. flash0_flvdd = [00];
  3500. flash0_flvdd_vol;
  3501. device_id = <0x0>;
  3502. status = "disabled";
  3503. linux,phandle = <0xa2>;
  3504. phandle = <0xa2>;
  3505. };
  3506.  
  3507. sensor@0 {
  3508. device_type = "sensor0";
  3509. sensor0_mname = "ov5640";
  3510. sensor0_twi_cci_id = <0x0>;
  3511. sensor0_twi_addr = <0x78>;
  3512. sensor0_pos = "rear";
  3513. sensor0_isp_used = <0x0>;
  3514. sensor0_fmt = <0x0>;
  3515. sensor0_stby_mode = <0x0>;
  3516. sensor0_vflip = <0x0>;
  3517. sensor0_hflip = <0x0>;
  3518. sensor0_iovdd = "iovdd-csi";
  3519. sensor0_iovdd_vol = <0x2ab980>;
  3520. sensor0_avdd = "avdd-csi";
  3521. sensor0_avdd_vol = <0x2ab980>;
  3522. sensor0_dvdd = "dvdd-csi-18";
  3523. sensor0_dvdd_vol = <0x16e360>;
  3524. sensor0_power_en;
  3525. sensor0_reset = <0x80 0x4 0xe 0x1 0x0 0x1 0x0>;
  3526. sensor0_pwdn = <0x80 0x4 0x10 0x1 0x0 0x1 0x0>;
  3527. flash_handle = <0xa2>;
  3528. act_handle = <0xa3>;
  3529. status = "okay";
  3530. linux,phandle = <0xa6>;
  3531. phandle = <0xa6>;
  3532. };
  3533.  
  3534. sensor@1 {
  3535. device_type = "sensor1";
  3536. sensor1_mname = "ov5647";
  3537. sensor1_twi_cci_id = <0x0>;
  3538. sensor1_twi_addr = <0x6c>;
  3539. sensor1_pos = "front";
  3540. sensor1_isp_used = <0x0>;
  3541. sensor1_fmt = <0x0>;
  3542. sensor1_stby_mode = <0x0>;
  3543. sensor1_vflip = <0x0>;
  3544. sensor1_hflip = <0x0>;
  3545. sensor1_iovdd = "iovdd-csi";
  3546. sensor1_iovdd_vol = <0x2ab980>;
  3547. sensor1_avdd = "avdd-csi";
  3548. sensor1_avdd_vol = <0x2ab980>;
  3549. sensor1_dvdd = "dvdd-csi-18";
  3550. sensor1_dvdd_vol = <0x16e360>;
  3551. sensor1_power_en;
  3552. sensor1_reset = <0x80 0x4 0xe 0x1 0x0 0x1 0x0>;
  3553. sensor1_pwdn = <0x80 0x4 0xf 0x1 0x0 0x1 0x0>;
  3554. flash_handle;
  3555. act_handle;
  3556. status = "okay";
  3557. linux,phandle = <0xa7>;
  3558. phandle = <0xa7>;
  3559. };
  3560.  
  3561. vinc@0x06623000 {
  3562. device_type = "vinc0";
  3563. compatible = "allwinner,sunxi-vin-core";
  3564. reg = <0x0 0x6623000 0x0 0x100>;
  3565. interrupts = <0x0 0x43 0x4>;
  3566. vinc0_csi_sel = <0x0>;
  3567. vinc0_mipi_sel = <0xff>;
  3568. vinc0_isp_sel = <0x0>;
  3569. vinc0_sensor_sel = <0x0>;
  3570. vinc0_sensor_list = <0x0>;
  3571. isp_handle = <0xa4 0xa5>;
  3572. sensor_handle = <0xa6 0xa7>;
  3573. device_id = <0x0>;
  3574. iommus = <0x19 0x4 0x1>;
  3575. status = "okay";
  3576. };
  3577.  
  3578. vinc@0x06623100 {
  3579. device_type = "vinc1";
  3580. compatible = "allwinner,sunxi-vin-core";
  3581. reg = <0x0 0x6623100 0x0 0x100>;
  3582. interrupts = <0x0 0x44 0x4>;
  3583. vinc1_csi_sel = <0x0>;
  3584. vinc1_mipi_sel = <0xff>;
  3585. vinc1_isp_sel = <0x0>;
  3586. vinc1_sensor_sel = <0x1>;
  3587. vinc1_sensor_list = <0x0>;
  3588. isp_handle = <0xa4 0xa5>;
  3589. sensor_handle = <0xa6 0xa7>;
  3590. device_id = <0x1>;
  3591. iommus = <0x19 0x4 0x1>;
  3592. status = "okay";
  3593. };
  3594. };
  3595.  
  3596. vdevice@0 {
  3597. compatible = "allwinner,sun50i-vdevice";
  3598. device_type = "Vdevice";
  3599. pinctrl-names = "default";
  3600. test-gpios = <0x80 0x1 0x0 0x1 0x2 0x2 0x1>;
  3601. status = "disabled";
  3602. pinctrl-0 = <0x10f>;
  3603. };
  3604.  
  3605. emce@01905000 {
  3606. compatible = "allwinner,sunxi-emce";
  3607. device_name = "emce";
  3608. reg = <0x0 0x1905000 0x0 0x100>;
  3609. clock-frequency = <0x11e1a300>;
  3610. clocks = <0xa9 0x1b>;
  3611. };
  3612.  
  3613. ce@1904000 {
  3614. compatible = "allwinner,sunxi-ce";
  3615. device_name = "ce";
  3616. reg = <0x0 0x1904000 0x0 0xa0 0x0 0x1904800 0x0 0xa0>;
  3617. interrupts = <0x0 0x57 0xff01 0x0 0x58 0xff01>;
  3618. clock-frequency = <0x11e1a300>;
  3619. clocks = <0xaa 0x1b>;
  3620. };
  3621.  
  3622. deinterlace@0x01420000 {
  3623. #address-cells = <0x1>;
  3624. #size-cells = <0x0>;
  3625. compatible = "allwinner,sunxi-deinterlace";
  3626. reg = <0x0 0x1420000 0x0 0x20c>;
  3627. interrupts = <0x0 0x4f 0x4>;
  3628. clocks = <0xab 0x2>;
  3629. iommus = <0x19 0x2 0x1>;
  3630. status = "okay";
  3631. device_type = "di";
  3632. };
  3633.  
  3634. smartcard@0x05005000 {
  3635. #address-cells = <0x1>;
  3636. #size-cells = <0x0>;
  3637. compatible = "allwinner,sunxi-scr";
  3638. device_type = "scr0";
  3639. reg = <0x0 0x5005000 0x0 0x400>;
  3640. interrupts = <0x0 0x8 0x4>;
  3641. clocks = <0xac 0xad>;
  3642. clock-frequency = <0x16e3600>;
  3643. pinctrl-names = "default", "sleep";
  3644. pinctrl-0 = <0xae 0xaf>;
  3645. pinctrl-1 = <0xb0>;
  3646. status = "disabled";
  3647. };
  3648.  
  3649. smartcard@0x05005400 {
  3650. #address-cells = <0x1>;
  3651. #size-cells = <0x0>;
  3652. compatible = "allwinner,sunxi-scr";
  3653. device_type = "scr1";
  3654. reg = <0x0 0x5005400 0x0 0x400>;
  3655. interrupts = <0x0 0x9 0x4>;
  3656. clocks = <0xb1 0xad>;
  3657. clock-frequency = <0x16e3600>;
  3658. pinctrl-names = "default", "sleep";
  3659. pinctrl-0 = <0xb2 0xb3>;
  3660. pinctrl-1 = <0xb4>;
  3661. status = "disabled";
  3662. };
  3663.  
  3664. pmu@0 {
  3665. interrupts = <0x0 0x60 0x4>;
  3666. status = "okay";
  3667. device_type = "pmu0";
  3668. compatible = "axp806";
  3669. pmu_id = <0x3>;
  3670. pmu_irq_wakeup = <0x1>;
  3671. pmu_hot_shutdown = <0x1>;
  3672.  
  3673. powerkey@0 {
  3674. status = "okay";
  3675. device_type = "powerkey0";
  3676. compatible = "axp806-powerkey";
  3677. pmu_powkey_off_time = <0x1770>;
  3678. pmu_powkey_off_func = <0x0>;
  3679. pmu_powkey_off_en = <0x1>;
  3680. pmu_powkey_long_time = <0x5dc>;
  3681. pmu_powkey_on_time = <0x3e8>;
  3682. };
  3683.  
  3684. regulator@0 {
  3685. status = "okay";
  3686. device_type = "regulator0";
  3687. compatible = "axp806-regulator";
  3688. regulator_count = <0x10>;
  3689. regulator1 = "axp806_dcdca none vdd-cpua";
  3690. regulator2 = "axp806_dcdcb none";
  3691. regulator3 = "axp806_dcdcc none vdd-gpu";
  3692. regulator4 = "axp806_dcdcd none vdd-sys vdd-hdmi vdd-pcie vdd-usb";
  3693. regulator5 = "axp806_dcdce none vcc-dram";
  3694. regulator6 = "axp806_aldo1 none vcc-pl vcc-led vcc-ir vcc-pg vcc-pm vcc-ts";
  3695. regulator7 = "axp806_aldo2 none ac-ldoin vcc-audio-33 vcc-ephy usb-dvdd vcc-tv";
  3696. regulator8 = "axp806_aldo3 none vcc-pcie-slot";
  3697. regulator9 = "axp806_bldo1 none vdd-dram-18 vdd-bias vcc-pll";
  3698. regulator10 = "axp806_bldo2 none vcc-emmc-18 vcc-pcie vdd-efuse vcc-hdmi vcc-emmcvq18";
  3699. regulator11 = "axp806_bldo3 none";
  3700. regulator12 = "axp806_bldo4 none";
  3701. regulator13 = "axp806_cldo1 none vcc-io vcc-nand vcc-card vcc-pd vcc-usb vcc-uart vcc-jtagx vcc-emmc-33 vcc-camera-33 vcc-emmcv vcc-sdcv vcc-sdcvq33 vcc-sdcvd";
  3702. regulator14 = "axp806_cldo2 none";
  3703. regulator15 = "axp806_cldo3 none vcc-wifi";
  3704. regulator16 = "axp806_sw none";
  3705. };
  3706.  
  3707. axp_gpio@0 {
  3708. gpio-controller;
  3709. #size-cells = <0x0>;
  3710. #gpio-cells = <0x6>;
  3711. status = "okay";
  3712. device_type = "axp_pio";
  3713. linux,phandle = <0xf9>;
  3714. phandle = <0xf9>;
  3715. };
  3716.  
  3717. charger@0 {
  3718. status = "disabled";
  3719. device_type = "charger0";
  3720. pmu_bat_unused = <0x1>;
  3721. pmu_pwroff_vol = <0xce4>;
  3722. power_start = <0x0>;
  3723. };
  3724. };
  3725.  
  3726. nmi@0x01f00c00 {
  3727. #address-cells = <0x1>;
  3728. #size-cells = <0x0>;
  3729. compatible = "allwinner,sunxi-nmi";
  3730. reg = <0x0 0x1f00c00 0x0 0x50>;
  3731. nmi_irq_ctrl = <0xc>;
  3732. nmi_irq_en = <0x40>;
  3733. nmi_irq_status = <0x10>;
  3734. nmi_irq_mask = <0x50>;
  3735. status = "okay";
  3736. };
  3737.  
  3738. nand0@04011000 {
  3739. compatible = "allwinner,sun50iw6-nand";
  3740. device_type = "nand0";
  3741. reg = <0x0 0x4011000 0x0 0x1000>;
  3742. interrupts = <0x0 0x22 0x4>;
  3743. clocks = <0x1b 0xb5 0xb6>;
  3744. pinctrl-names = "default", "sleep";
  3745. pinctrl-1 = <0xb9>;
  3746. nand0_regulator1 = "vcc-nand";
  3747. nand0_regulator2 = "none";
  3748. nand0_cache_level = <0x55aaaa55>;
  3749. nand0_flush_cache_num = <0x55aaaa55>;
  3750. nand0_capacity_level = <0x55aaaa55>;
  3751. nand0_id_number_ctl = <0x55aaaa55>;
  3752. nand0_print_level = <0x55aaaa55>;
  3753. nand0_p0 = <0x55aaaa55>;
  3754. nand0_p1 = <0x55aaaa55>;
  3755. nand0_p2 = <0x55aaaa55>;
  3756. nand0_p3 = <0x55aaaa55>;
  3757. status = "okay";
  3758. nand0_support_2ch = <0x0>;
  3759. pinctrl-0 = <0xfa 0xfb>;
  3760. };
  3761.  
  3762. ts0@05060000 {
  3763. compatible = "allwinner,sun50i-tsc";
  3764. device_type = "ts0";
  3765. reg = <0x0 0x5060000 0x0 0x1000>;
  3766. interrupts = <0x0 0xe 0x4>;
  3767. clocks = <0x2 0xba>;
  3768. clock-frequency = <0x7270e00>;
  3769. pinctrl-names = "ts0-default", "ts1-default", "ts2-default", "ts3-default", "ts0-sleep", "ts1-sleep", "ts2-sleep", "ts3-sleep";
  3770. pinctrl-0 = <0xbb>;
  3771. pinctrl-1 = <0xbc>;
  3772. pinctrl-2 = <0xbd>;
  3773. pinctrl-3 = <0xbe>;
  3774. pinctrl-4 = <0xbf>;
  3775. pinctrl-5 = <0xc0>;
  3776. pinctrl-6 = <0xc1>;
  3777. pinctrl-7 = <0xc2>;
  3778. ts0config = <0x1>;
  3779. ts1config = <0x0>;
  3780. ts2config = <0x0>;
  3781. ts3config = <0x0>;
  3782. status = "okay";
  3783. };
  3784.  
  3785. thermal_sensor {
  3786. compatible = "allwinner,thermal_sensor";
  3787. reg = <0x0 0x5070400 0x0 0x400>;
  3788. interrupts = <0x0 0xf 0x0>;
  3789. clocks = <0x7 0xc3>;
  3790. sensor_num = <0x2>;
  3791. combine_num = <0x2>;
  3792. alarm_low_temp = <0x69>;
  3793. alarm_high_temp = <0x6e>;
  3794. alarm_temp_hysteresis = <0xf>;
  3795. shut_temp = <0x73>;
  3796. status = "okay";
  3797.  
  3798. ths_combine0 {
  3799. compatible = "allwinner,ths_combine0";
  3800. #thermal-sensor-cells = <0x1>;
  3801. combine_sensor_num = <0x1>;
  3802. combine_sensor_type = "cpu";
  3803. combine_sensor_temp_type = "max";
  3804. combine_sensor_id = <0x0>;
  3805. linux,phandle = <0xc4>;
  3806. phandle = <0xc4>;
  3807. };
  3808.  
  3809. ths_combine1 {
  3810. compatible = "allwinner,ths_combine1";
  3811. #thermal-sensor-cells = <0x1>;
  3812. combine_sensor_num = <0x1>;
  3813. combine_sensor_type = "gpu";
  3814. combine_sensor_temp_type = "max";
  3815. combine_sensor_id = <0x1>;
  3816. linux,phandle = <0xcc>;
  3817. phandle = <0xcc>;
  3818. };
  3819. };
  3820.  
  3821. cpu_budget_cool {
  3822. device_type = "cpu_budget_cool";
  3823. compatible = "allwinner,budget_cooling";
  3824. #cooling-cells = <0x2>;
  3825. status = "okay";
  3826. state_cnt = <0x7>;
  3827. cluster_num = <0x1>;
  3828. state0 = <0x1b7740 0x4>;
  3829. state1 = <0x16b480 0x4>;
  3830. state2 = <0x142440 0x3>;
  3831. state3 = <0x107ac0 0x2>;
  3832. state4 = <0xd8cc0 0x1>;
  3833. state5 = <0xafc80 0x1>;
  3834. state6 = <0x75300 0x1>;
  3835. linux,phandle = <0xc6>;
  3836. phandle = <0xc6>;
  3837. };
  3838.  
  3839. gpu_cooling {
  3840. compatible = "allwinner,gpu_cooling";
  3841. reg = <0x0 0x0 0x0 0x0>;
  3842. #cooling-cells = <0x2>;
  3843. status = "okay";
  3844. state_cnt = <0x4>;
  3845. state0 = <0x0>;
  3846. state1 = <0x1>;
  3847. state2 = <0x2>;
  3848. state3 = <0x3>;
  3849. linux,phandle = <0xce>;
  3850. phandle = <0xce>;
  3851. };
  3852.  
  3853. thermal-zones {
  3854.  
  3855. cpu_thermal_zone {
  3856. polling-delay-passive = <0x3e8>;
  3857. polling-delay = <0x3e8>;
  3858. thermal-sensors = <0xc4 0x0>;
  3859.  
  3860. trips {
  3861.  
  3862. t0 {
  3863. temperature = <0x3c>;
  3864. type = "passive";
  3865. hysteresis = <0x0>;
  3866. linux,phandle = <0xc5>;
  3867. phandle = <0xc5>;
  3868. };
  3869.  
  3870. t1 {
  3871. temperature = <0x5a>;
  3872. type = "passive";
  3873. hysteresis = <0x0>;
  3874. linux,phandle = <0xc7>;
  3875. phandle = <0xc7>;
  3876. };
  3877.  
  3878. t2 {
  3879. temperature = <0x5f>;
  3880. type = "passive";
  3881. hysteresis = <0x0>;
  3882. linux,phandle = <0xc8>;
  3883. phandle = <0xc8>;
  3884. };
  3885.  
  3886. t3 {
  3887. temperature = <0x64>;
  3888. type = "passive";
  3889. hysteresis = <0x0>;
  3890. linux,phandle = <0xc9>;
  3891. phandle = <0xc9>;
  3892. };
  3893.  
  3894. t4 {
  3895. temperature = <0x69>;
  3896. type = "passive";
  3897. hysteresis = <0x0>;
  3898. linux,phandle = <0xca>;
  3899. phandle = <0xca>;
  3900. };
  3901.  
  3902. t5 {
  3903. temperature = <0x6e>;
  3904. type = "passive";
  3905. hysteresis = <0x0>;
  3906. linux,phandle = <0xcb>;
  3907. phandle = <0xcb>;
  3908. };
  3909.  
  3910. t6 {
  3911. temperature = <0x73>;
  3912. type = "critical";
  3913. hysteresis = <0x0>;
  3914. };
  3915. };
  3916.  
  3917. cooling-maps {
  3918.  
  3919. bind0 {
  3920. contribution = <0x0>;
  3921. trip = <0xc5>;
  3922. cooling-device = <0xc6 0x1 0x1>;
  3923. };
  3924.  
  3925. bind1 {
  3926. contribution = <0x0>;
  3927. trip = <0xc7>;
  3928. cooling-device = <0xc6 0x2 0x2>;
  3929. };
  3930.  
  3931. bind2 {
  3932. contribution = <0x0>;
  3933. trip = <0xc8>;
  3934. cooling-device = <0xc6 0x3 0x3>;
  3935. };
  3936.  
  3937. bind3 {
  3938. contribution = <0x0>;
  3939. trip = <0xc9>;
  3940. cooling-device = <0xc6 0x4 0x4>;
  3941. };
  3942.  
  3943. bind4 {
  3944. contribution = <0x0>;
  3945. trip = <0xca>;
  3946. cooling-device = <0xc6 0x5 0x5>;
  3947. };
  3948.  
  3949. bind5 {
  3950. contribution = <0x0>;
  3951. trip = <0xcb>;
  3952. cooling-device = <0xc6 0x6 0x6>;
  3953. };
  3954. };
  3955. };
  3956.  
  3957. gpu_thermal_zone {
  3958. polling-delay-passive = <0x3e8>;
  3959. polling-delay = <0x7d0>;
  3960. thermal-sensors = <0xcc 0x1>;
  3961.  
  3962. trips {
  3963.  
  3964. t0 {
  3965. temperature = <0x5f>;
  3966. type = "passive";
  3967. hysteresis = <0x0>;
  3968. linux,phandle = <0xcd>;
  3969. phandle = <0xcd>;
  3970. };
  3971.  
  3972. t1 {
  3973. temperature = <0x64>;
  3974. type = "passive";
  3975. hysteresis = <0x0>;
  3976. linux,phandle = <0xcf>;
  3977. phandle = <0xcf>;
  3978. };
  3979.  
  3980. t2 {
  3981. temperature = <0x69>;
  3982. type = "passive";
  3983. hysteresis = <0x0>;
  3984. linux,phandle = <0xd0>;
  3985. phandle = <0xd0>;
  3986. };
  3987.  
  3988. t3 {
  3989. temperature = <0x73>;
  3990. type = "critical";
  3991. hysteresis = <0x0>;
  3992. };
  3993. };
  3994.  
  3995. cooling-maps {
  3996.  
  3997. bind0 {
  3998. contribution = <0x0>;
  3999. trip = <0xcd>;
  4000. cooling-device = <0xce 0x1 0x1>;
  4001. };
  4002.  
  4003. bind1 {
  4004. contribution = <0x0>;
  4005. trip = <0xcf>;
  4006. cooling-device = <0xce 0x2 0x2>;
  4007. };
  4008.  
  4009. bind2 {
  4010. contribution = <0x0>;
  4011. trip = <0xd0>;
  4012. cooling-device = <0xce 0x3 0x3>;
  4013. };
  4014. };
  4015. };
  4016. };
  4017.  
  4018. keyboard {
  4019. compatible = "allwinner,keyboard_1200mv";
  4020. reg = <0x0 0x5070800 0x0 0x400>;
  4021. interrupts = <0x0 0x10 0x0>;
  4022. status = "okay";
  4023. key_cnt = <0x5>;
  4024. key0 = <0x73 0x73>;
  4025. key1 = <0xeb 0x72>;
  4026. key2 = <0x14a 0x8b>;
  4027. key3 = <0x1a4 0x1c>;
  4028. key4 = <0x208 0x66>;
  4029. };
  4030.  
  4031. eth@05020000 {
  4032. compatible = "allwinner,sunxi-gmac";
  4033. reg = <0x0 0x5020000 0x0 0x10000 0x0 0x3000030 0x0 0x4>;
  4034. interrupts = <0x0 0xc 0x4>;
  4035. interrupt-names = "gmacirq";
  4036. clocks = <0xd1>;
  4037. clock-names = "gmac";
  4038. pinctrl-names = "default";
  4039. phy-mode = "rgmii";
  4040. tx-delay = <0x0>;
  4041. rx-delay = <0x0>;
  4042. phy-rst;
  4043. gmac-power0 = "vcc-io";
  4044. gmac-power1 = "axp806_aldo3";
  4045. status = "okay";
  4046. device_type = "gmac0";
  4047. pinctrl-0 = <0xe1>;
  4048. gmac-power2;
  4049. };
  4050.  
  4051. product {
  4052. device_type = "product";
  4053. version = "100";
  4054. machine = "petrel-p1";
  4055. };
  4056.  
  4057. platform {
  4058. device_type = "platform";
  4059. eraseflag = <0x1>;
  4060. };
  4061.  
  4062. target {
  4063. device_type = "target";
  4064. boot_clock = <0x528>;
  4065. storage_type = <0xffffffff>;
  4066. burn_key = <0x0>;
  4067. dragonboard_test = <0x0>;
  4068. power_mode = <0x0>;
  4069. advert_enable = <0x0>;
  4070. };
  4071.  
  4072. secure {
  4073. device_type = "secure";
  4074. dram_region_mbytes = <0x50>;
  4075. drm_region_mbytes = <0x0>;
  4076. drm_region_start_mbytes = <0x0>;
  4077. };
  4078.  
  4079. power_sply {
  4080. device_type = "power_sply";
  4081. dcdca_vol = <0xf4628>;
  4082. dcdcd_vol = <0xf4628>;
  4083. aldo2_vol = <0xf4f24>;
  4084. aldo3_vol = <0xf4f24>;
  4085. bldo2_vol = <0xf4948>;
  4086. cldo1_vol = <0xf4f24>;
  4087. cldo2_vol = <0xf4f24>;
  4088. cldo3_vol = <0xf4f24>;
  4089. };
  4090.  
  4091. gpio_bias {
  4092. device_type = "gpio_bias";
  4093. pc_bias = "axp806:bldo2:1800";
  4094. pg_bias = "axp806:bldo3:1800";
  4095. };
  4096.  
  4097. ir_boot_recovery {
  4098. device_type = "ir_boot_recovery";
  4099. status = "disabled";
  4100. ir_work_mode = <0x1>;
  4101. ir_press_times = <0x1>;
  4102. ir_detect_time = <0x7d0>;
  4103. ir_recovery_key_code0 = <0x57>;
  4104. ir_addr_code0 = <0x9f00>;
  4105. };
  4106.  
  4107. card_boot {
  4108. device_type = "card_boot";
  4109. logical_start = <0xa000>;
  4110. sprite_gpio0 = <0xdb 0xb 0x4 0x1 0xffffffff 0xffffffff 0x1>;
  4111. next_work = <0x3>;
  4112. };
  4113.  
  4114. key_boot_recovery {
  4115. device_type = "key_boot_recovery";
  4116. status = "okay";
  4117. press_mode_enable = <0x0>;
  4118. key_work_mode = <0x1>;
  4119. short_press_mode = <0x0>;
  4120. long_press_mode = <0x1>;
  4121. key_press_time = <0x7d0>;
  4122. recovery_key = <0xdb 0xb 0x2 0x0 0xffffffff 0xffffffff 0xffffffff>;
  4123. };
  4124.  
  4125. boot_init_gpio {
  4126. device_type = "boot_init_gpio";
  4127. status = "okay";
  4128. gpio0 = <0xdb 0xb 0x7 0x1 0xffffffff 0xffffffff 0x1>;
  4129. gpio1 = <0x80 0x0 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4130. gpio2 = <0x80 0x7 0x2 0x1 0xffffffff 0xffffffff 0x1>;
  4131. };
  4132.  
  4133. pm_para {
  4134. device_type = "pm_para";
  4135. standby_mode = <0x1>;
  4136. };
  4137.  
  4138. card0_boot_para {
  4139. device_type = "card0_boot_para";
  4140. card_ctrl = <0x0>;
  4141. card_high_speed = <0x1>;
  4142. card_line = <0x4>;
  4143. pinctrl-0 = <0xdc>;
  4144. };
  4145.  
  4146. card2_boot_para {
  4147. device_type = "card2_boot_para";
  4148. card_ctrl = <0x2>;
  4149. card_high_speed = <0x1>;
  4150. card_line = <0x8>;
  4151. pinctrl-0 = <0xdd>;
  4152. sdc_ex_dly_used = <0x2>;
  4153. sdc_io_1v8 = <0x1>;
  4154. sdc_tm4_hs400_max_freq = <0x64>;
  4155. sdc_tm4_hs200_max_freq = <0x96>;
  4156. };
  4157.  
  4158. twi_para {
  4159. device_type = "twi_para";
  4160. twi_port = <0x0>;
  4161. pinctrl-0 = <0xde>;
  4162. };
  4163.  
  4164. uart_para {
  4165. device_type = "uart_para";
  4166. uart_debug_port = <0x0>;
  4167. pinctrl-0 = <0xdf>;
  4168. };
  4169.  
  4170. jtag_para {
  4171. device_type = "jtag_para";
  4172. jtag_enable = <0x1>;
  4173. pinctrl-0 = <0xe0>;
  4174. };
  4175.  
  4176. clock {
  4177. device_type = "clock";
  4178. pll4 = <0x12c>;
  4179. pll6 = <0x258>;
  4180. pll8 = <0x168>;
  4181. pll9 = <0x129>;
  4182. pll10 = <0x108>;
  4183. };
  4184.  
  4185. rtp_para {
  4186. device_type = "rtp_para";
  4187. rtp_used = <0x0>;
  4188. rtp_screen_size = <0x5>;
  4189. rtp_regidity_level = <0x5>;
  4190. rtp_press_threshold_enable = <0x0>;
  4191. rtp_press_threshold = <0x1f40>;
  4192. rtp_sensitive_level = <0xf>;
  4193. rtp_exchange_x_y_flag = <0x0>;
  4194. };
  4195.  
  4196. ctp {
  4197. device_type = "ctp";
  4198. compatible = "allwinner,sun50i-ctp-para";
  4199. status = "disabled";
  4200. ctp_twi_id = <0x0>;
  4201. ctp_twi_addr = <0x5d>;
  4202. ctp_screen_max_x = <0x500>;
  4203. ctp_screen_max_y = <0x320>;
  4204. ctp_revert_x_flag = <0x1>;
  4205. ctp_revert_y_flag = <0x1>;
  4206. ctp_exchange_x_y_flag = <0x1>;
  4207. ctp_int_port = <0x80 0x7 0x4 0x6 0xffffffff 0xffffffff 0xffffffff>;
  4208. ctp_wakeup = <0x80 0x7 0x8 0x1 0xffffffff 0xffffffff 0x1>;
  4209. ctp_power_ldo = "vcc-ctp";
  4210. ctp_power_ldo_vol = <0xce4>;
  4211. ctp_power_io;
  4212. };
  4213.  
  4214. ctp_list {
  4215. device_type = "ctp_list";
  4216. compatible = "allwinner,sun50i-ctp-list";
  4217. ctp_det_used = <0x0>;
  4218. ft5x_ts = <0x1>;
  4219. gt82x = <0x1>;
  4220. gslX680 = <0x1>;
  4221. gt9xx_ts = <0x0>;
  4222. gt9xxnew_ts = <0x1>;
  4223. gt811 = <0x1>;
  4224. zet622x = <0x1>;
  4225. aw5306_ts = <0x1>;
  4226. };
  4227.  
  4228. tkey_para {
  4229. device_type = "tkey_para";
  4230. tkey_used = <0x0>;
  4231. tkey_twi_id;
  4232. tkey_twi_addr;
  4233. tkey_int;
  4234. };
  4235.  
  4236. motor_para {
  4237. device_type = "motor_para";
  4238. motor_used = <0x1>;
  4239. motor_shake = <0xf9 0xfffe 0x3 0x1 0xffffffff 0xffffffff 0x1>;
  4240. };
  4241.  
  4242. esm {
  4243. device_type = "esm";
  4244. esm_img_size_addr = <0x0>;
  4245. esm_img_buff_addr = <0x0>;
  4246. };
  4247.  
  4248. pwm16 {
  4249. device_type = "pwm16";
  4250. s_pwm0_used = <0x0>;
  4251. pinctrl-0 = <0x105>;
  4252. pinctrl-1 = <0x106>;
  4253. };
  4254.  
  4255. tvout_para {
  4256. device_type = "tvout_para";
  4257. tvout_used;
  4258. tvout_channel_num;
  4259. tv_en;
  4260. };
  4261.  
  4262. tvin_para {
  4263. device_type = "tvin_para";
  4264. tvin_used;
  4265. tvin_channel_num;
  4266. };
  4267.  
  4268. smc {
  4269. device_type = "smc";
  4270. smc_used;
  4271. smc_rst;
  4272. smc_vppen;
  4273. smc_vppp;
  4274. smc_det;
  4275. smc_vccen;
  4276. smc_sck;
  4277. smc_sda;
  4278. };
  4279.  
  4280. gpio_para {
  4281. device_type = "gpio_para";
  4282. compatible = "allwinner,sunxi-init-gpio";
  4283. gpio_used = <0x1>;
  4284. gpio_num = <0x3>;
  4285. gpio_pin_1 = <0xdb 0xb 0x4 0x1 0xffffffff 0xffffffff 0x1>;
  4286. gpio_pin_2 = <0xdb 0xb 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4287. gpio_pin_3 = <0xdb 0xb 0x7 0x1 0xffffffff 0xffffffff 0x0>;
  4288. normal_led = "gpio_pin_1";
  4289. standby_led = "gpio_pin_2";
  4290. network_led = "gpio_pin_3";
  4291. easy_light_used = <0x1>;
  4292. normal_led_light = <0x1>;
  4293. standby_led_light = <0x1>;
  4294. network_led_light = <0x1>;
  4295. };
  4296.  
  4297. usbc3 {
  4298. device_type = "usbc3";
  4299. status = "disabled";
  4300. usb_drv_vbus_gpio;
  4301. usb_host_init_state = <0x1>;
  4302. usb_regulator_io = "nocare";
  4303. usb_wakeup_suspend = <0x0>;
  4304. };
  4305.  
  4306. serial_feature {
  4307. device_type = "serial_feature";
  4308. sn_filename = "sn.txt";
  4309. };
  4310.  
  4311. gsensor {
  4312. device_type = "gsensor";
  4313. compatible = "allwinner,sun50i-gsensor-para";
  4314. status = "disabled";
  4315. gsensor_twi_id = <0x1>;
  4316. gsensor_twi_addr = <0x18>;
  4317. gsensor_int1 = <0x80 0x0 0x9 0x6 0x1 0xffffffff 0xffffffff>;
  4318. gsensor_int2;
  4319. gsensor_vcc_io = "vcc-deviceio";
  4320. gsensor_vcc_io_val = <0xc1c>;
  4321. };
  4322.  
  4323. gsensor_list_para {
  4324. device_type = "gsensor_list_para";
  4325. compatible = "allwinner,sun50i-gsensor-list-para";
  4326. gsensor_det_used = <0x0>;
  4327. lsm9ds0_acc_mag = <0x1>;
  4328. bma250 = <0x1>;
  4329. mma8452 = <0x1>;
  4330. mma7660 = <0x1>;
  4331. mma865x = <0x1>;
  4332. afa750 = <0x1>;
  4333. lis3de_acc = <0x1>;
  4334. lis3dh_acc = <0x1>;
  4335. kxtik = <0x1>;
  4336. dmard10 = <0x0>;
  4337. dmard06 = <0x1>;
  4338. mxc622x = <0x1>;
  4339. fxos8700 = <0x1>;
  4340. lsm303d = <0x0>;
  4341. };
  4342.  
  4343. 3g_para {
  4344. device_type = "3g_para";
  4345. 3g_used = <0x0>;
  4346. 3g_usbc_num = <0x2>;
  4347. 3g_uart_num = <0x0>;
  4348. bb_vbat = <0xdb 0xb 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4349. bb_host_wake = <0xdb 0xc 0x0 0x1 0xffffffff 0xffffffff 0x0>;
  4350. bb_on = <0xdb 0xc 0x1 0x1 0xffffffff 0xffffffff 0x0>;
  4351. bb_pwr_on = <0xdb 0xc 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4352. bb_wake = <0xdb 0xc 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  4353. bb_rf_dis = <0xdb 0xc 0x5 0x1 0xffffffff 0xffffffff 0x0>;
  4354. bb_rst = <0xdb 0xc 0x6 0x1 0xffffffff 0xffffffff 0x0>;
  4355. 3g_int;
  4356. };
  4357.  
  4358. gy_para {
  4359. device_type = "gy_para";
  4360. compatible = "allwinner,sun50i-gyr_sensors-para";
  4361. gy_used = <0x0>;
  4362. gy_twi_id = <0x2>;
  4363. gy_twi_addr = <0x6a>;
  4364. gy_int1 = <0x80 0x0 0xa 0x6 0x1 0xffffffff 0xffffffff>;
  4365. gy_int2;
  4366. };
  4367.  
  4368. gy_list_para {
  4369. device_type = "gy_list_para";
  4370. compatible = "allwinner,sun50i-gyr_sensors-list-para";
  4371. gy_det_used = <0x1>;
  4372. lsm9ds0_gyr = <0x1>;
  4373. l3gd20_gyr = <0x0>;
  4374. bmg160_gyr = <0x1>;
  4375. };
  4376.  
  4377. ls_para {
  4378. device_type = "ls_para";
  4379. compatible = "allwinner,sun50i-lsensors-para";
  4380. ls_used = <0x0>;
  4381. ls_twi_id = <0x2>;
  4382. ls_twi_addr = <0x23>;
  4383. ls_int = <0x80 0x0 0xc 0x6 0x1 0xffffffff 0xffffffff>;
  4384. };
  4385.  
  4386. ls_list_para {
  4387. device_type = "ls_list_para";
  4388. compatible = "allwinner,sun50i-lsensors-list-para";
  4389. ls_det_used = <0x1>;
  4390. ltr_501als = <0x1>;
  4391. jsa1212 = <0x0>;
  4392. jsa1127 = <0x1>;
  4393. };
  4394.  
  4395. compass_para {
  4396. device_type = "compass_para";
  4397. compatible = "allwinner,sun50i-compass-para";
  4398. compass_used = <0x0>;
  4399. compass_twi_id = <0x2>;
  4400. compass_twi_addr = <0xd>;
  4401. compass_int = <0x80 0x0 0xb 0x6 0x1 0xffffffff 0xffffffff>;
  4402. };
  4403.  
  4404. compass_list_para {
  4405. device_type = "compass_list_para";
  4406. compatible = "allwinner,sun50i-compass-list-para";
  4407. compass_det_used = <0x1>;
  4408. lsm9ds0 = <0x1>;
  4409. lsm303d = <0x0>;
  4410. akm8963 = <0x1>;
  4411. };
  4412.  
  4413. s_rsb0 {
  4414. device_type = "s_rsb0";
  4415. status = "disabled";
  4416. pinctrl-0 = <0x10d>;
  4417. };
  4418.  
  4419. box_standby_led {
  4420. device_type = "box_standby_led";
  4421. gpio0 = <0xdb 0xb 0x7 0x1 0xffffffff 0xffffffff 0x0>;
  4422. gpio1 = <0xdb 0xb 0x3 0x1 0xffffffff 0xffffffff 0x1>;
  4423. gpio2 = <0xdb 0xb 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  4424. };
  4425.  
  4426. gpio_power_key {
  4427. device_type = "gpio_power_key";
  4428. compatible = "allwinner,sunxi-gpio-power-key";
  4429. status = "disabled";
  4430. key_io = <0xdb 0xb 0x5 0x0 0xffffffff 0xffffffff 0x0>;
  4431. trigger_mode = <0x1>;
  4432. };
  4433. };
  4434.  
  4435. aliases {
  4436. serial0 = "/soc@03000000/uart@05000000", "/soc@03000000/uart@05000000";
  4437. serial1 = "/soc@03000000/uart@05000400", "/soc@03000000/uart@05000400";
  4438. serial2 = "/soc@03000000/uart@05000800", "/soc@03000000/uart@05000800";
  4439. serial3 = "/soc@03000000/uart@05000c00", "/soc@03000000/uart@05000c00";
  4440. twi0 = "/soc@03000000/twi@0x05002000", "/soc@03000000/twi@0x05002000";
  4441. twi1 = "/soc@03000000/twi@0x05002400", "/soc@03000000/twi@0x05002400";
  4442. twi2 = "/soc@03000000/twi@0x05002800", "/soc@03000000/twi@0x05002800";
  4443. twi3 = "/soc@03000000/twi@0x05002c00", "/soc@03000000/twi@0x05002c00";
  4444. spi0 = "/soc@03000000/spi@05010000", "/soc@03000000/spi@05010000";
  4445. spi1 = "/soc@03000000/spi@05011000", "/soc@03000000/spi@05011000";
  4446. pcie = "/soc@03000000/pcie@0x05400000", "/soc@03000000/pcie@0x05400000";
  4447. scr0 = "/soc@03000000/smartcard@0x05005000", "/soc@03000000/smartcard@0x05005000";
  4448. scr1 = "/soc@03000000/smartcard@0x05005400", "/soc@03000000/smartcard@0x05005400";
  4449. gmac0 = "/soc@03000000/eth@05020000", "/soc@03000000/eth@05020000";
  4450. global_timer0 = "/soc@03000000/timer@03009000", "/soc@03000000/timer@03009000";
  4451. mmc0 = "/soc@03000000/sdmmc@04020000", "/soc@03000000/sdmmc@04020000";
  4452. mmc2 = "/soc@03000000/sdmmc@04022000", "/soc@03000000/sdmmc@04022000";
  4453. nand0 = "/soc@03000000/nand0@04011000", "/soc@03000000/nand0@04011000";
  4454. disp = "/soc@03000000/disp@01000000", "/soc@03000000/disp@01000000";
  4455. lcd0 = "/soc@03000000/lcd0@01c0c000", "/soc@03000000/lcd0@01c0c000";
  4456. hdmi = "/soc@03000000/hdmi@06000000", "/soc@03000000/hdmi@06000000";
  4457. pwm = "/soc@03000000/pwm@0300a000", "/soc@03000000/pwm@0300a000";
  4458. pwm0 = "/soc@03000000/pwm0@0300a000", "/soc@03000000/pwm0@0300a000";
  4459. pwm1 = "/soc@03000000/pwm1@0300a000", "/soc@03000000/pwm1@0300a000";
  4460. tv0 = "/soc@03000000/tv0@01c94000", "/soc@03000000/tv0@01c94000";
  4461. s_pwm = "/soc@03000000/s_pwm@07020c00", "/soc@03000000/s_pwm@07020c00";
  4462. spwm0 = "/soc@03000000/spwm0@07020c00", "/soc@03000000/spwm0@07020c00";
  4463. boot_disp = "/soc@03000000/boot_disp", "/soc@03000000/boot_disp";
  4464. charger0 = "/soc@03000000/pmu@0/charger@0", "/soc@03000000/pmu@0/charger@0";
  4465. regulator0 = "/soc@03000000/pmu@0/regulator@0", "/soc@03000000/pmu@0/regulator@0";
  4466. };
  4467.  
  4468. chosen {
  4469. bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  4470. linux,initrd-start = <0x0 0x0>;
  4471. linux,initrd-end = <0x0 0x0>;
  4472. };
  4473.  
  4474. cpus {
  4475. #address-cells = <0x2>;
  4476. #size-cells = <0x0>;
  4477.  
  4478. cpu@0 {
  4479. device_type = "cpu";
  4480. compatible = "arm,cortex-a53", "arm,armv8";
  4481. reg = <0x0 0x0>;
  4482. enable-method = "psci";
  4483. cpufreq_tbl = <0x75300 0xafc80 0xc7380 0xd8cc0 0x107ac0 0x142440 0x16b480 0x1b7740>;
  4484. clock-latency = <0x1e8480>;
  4485. clock-frequency = <0x4ead9a00>;
  4486. cpu-idle-states = <0xd3 0xd4 0xd5>;
  4487. };
  4488.  
  4489. cpu@1 {
  4490. device_type = "cpu";
  4491. compatible = "arm,cortex-a53", "arm,armv8";
  4492. reg = <0x0 0x1>;
  4493. enable-method = "psci";
  4494. clock-frequency = <0x4ead9a00>;
  4495. cpu-idle-states = <0xd3 0xd4 0xd5>;
  4496. };
  4497.  
  4498. cpu@2 {
  4499. device_type = "cpu";
  4500. compatible = "arm,cortex-a53", "arm,armv8";
  4501. reg = <0x0 0x2>;
  4502. enable-method = "psci";
  4503. clock-frequency = <0x4ead9a00>;
  4504. cpu-idle-states = <0xd3 0xd4 0xd5>;
  4505. };
  4506.  
  4507. cpu@3 {
  4508. device_type = "cpu";
  4509. compatible = "arm,cortex-a53", "arm,armv8";
  4510. reg = <0x0 0x3>;
  4511. enable-method = "psci";
  4512. clock-frequency = <0x4ead9a00>;
  4513. cpu-idle-states = <0xd3 0xd4 0xd5>;
  4514. };
  4515.  
  4516. idle-states {
  4517. entry-method = "arm,psci";
  4518.  
  4519. cpu-sleep-0 {
  4520. compatible = "arm,idle-state";
  4521. arm,psci-suspend-param = <0x10000>;
  4522. entry-latency-us = <0xfa0>;
  4523. exit-latency-us = <0x2710>;
  4524. min-residency-us = <0x3a98>;
  4525. linux,phandle = <0xd3>;
  4526. phandle = <0xd3>;
  4527. };
  4528.  
  4529. cluster-sleep-0 {
  4530. compatible = "arm,idle-state";
  4531. arm,psci-suspend-param = <0x1010000>;
  4532. entry-latency-us = <0xc350>;
  4533. exit-latency-us = <0x186a0>;
  4534. min-residency-us = <0x3d090>;
  4535. linux,phandle = <0xd4>;
  4536. phandle = <0xd4>;
  4537. };
  4538.  
  4539. sys-sleep-0 {
  4540. compatible = "arm,idle-state";
  4541. arm,psci-suspend-param = <0x2010000>;
  4542. entry-latency-us = <0x186a0>;
  4543. exit-latency-us = <0x1e8480>;
  4544. min-residency-us = <0x44aa20>;
  4545. linux,phandle = <0xd5>;
  4546. phandle = <0xd5>;
  4547. };
  4548. };
  4549. };
  4550.  
  4551. psci {
  4552. compatible = "arm,psci-0.2";
  4553. method = "smc";
  4554. psci_version = <0x84000000>;
  4555. cpu_suspend = <0xc4000001>;
  4556. cpu_off = <0x84000002>;
  4557. cpu_on = <0xc4000003>;
  4558. affinity_info = <0xc4000004>;
  4559. migrate = <0xc4000005>;
  4560. migrate_info_type = <0x84000006>;
  4561. migrate_info_up_cpu = <0xc4000007>;
  4562. system_off = <0x84000008>;
  4563. system_reset = <0x84000009>;
  4564. };
  4565.  
  4566. n_brom {
  4567. compatible = "allwinner,n-brom";
  4568. reg = <0x0 0x0 0x0 0xa000>;
  4569. };
  4570.  
  4571. s_brom {
  4572. compatible = "allwinner,s-brom";
  4573. reg = <0x0 0x0 0x0 0x10000>;
  4574. };
  4575.  
  4576. sram_ctrl {
  4577. device_type = "sram_ctrl";
  4578. compatible = "allwinner,sram_ctrl";
  4579. reg = <0x0 0x3000000 0x0 0x100>;
  4580. };
  4581.  
  4582. sram_a1 {
  4583. compatible = "allwinner,sram_a1";
  4584. reg = <0x0 0x20000 0x0 0x8000>;
  4585. };
  4586.  
  4587. sram_a2 {
  4588. compatible = "allwinner,sram_a2";
  4589. reg = <0x0 0x100000 0x0 0x14000>;
  4590. };
  4591.  
  4592. prcm {
  4593. compatible = "allwinner,prcm";
  4594. reg = <0x0 0x1f01400 0x0 0x400>;
  4595. };
  4596.  
  4597. cpuscfg {
  4598. compatible = "allwinner,cpuscfg";
  4599. reg = <0x0 0x1f01c00 0x0 0x400>;
  4600. };
  4601.  
  4602. ion {
  4603. compatible = "allwinner,sunxi-ion";
  4604.  
  4605. system {
  4606. type = <0x0>;
  4607. };
  4608.  
  4609. system_contig {
  4610. type = <0x1>;
  4611. };
  4612.  
  4613. cma {
  4614. type = <0x4>;
  4615. };
  4616.  
  4617. secure {
  4618. type = <0x6>;
  4619. };
  4620. };
  4621.  
  4622. dram {
  4623. compatible = "allwinner,dram";
  4624. clocks = <0xd6>;
  4625. clock-names = "pll_ddr";
  4626. dram_clk = <0x0>;
  4627. dram_type = <0x7>;
  4628. dram_zq = <0x3b3bfb>;
  4629. dram_odt_en = <0x31>;
  4630. dram_para1 = <0x30fa>;
  4631. dram_para2 = <0x4000000>;
  4632. dram_mr0 = <0x1c70>;
  4633. dram_mr1 = <0x40>;
  4634. dram_mr2 = <0x18>;
  4635. dram_mr3 = <0x1>;
  4636. dram_tpr0 = <0x48a192>;
  4637. dram_tpr1 = <0x1b1a94b>;
  4638. dram_tpr2 = <0x61043>;
  4639. dram_tpr3 = <0x78787896>;
  4640. dram_tpr4 = <0x0>;
  4641. dram_tpr5 = <0x0>;
  4642. dram_tpr6 = "\t\t\t";
  4643. dram_tpr7 = <0x4d462a3e>;
  4644. dram_tpr8 = <0x0>;
  4645. dram_tpr9 = <0x0>;
  4646. dram_tpr10 = <0x0>;
  4647. dram_tpr11 = <0x440000>;
  4648. dram_tpr12 = <0x0>;
  4649. dram_tpr13 = <0x0>;
  4650. device_type = "dram";
  4651. dram_mr4 = <0x0>;
  4652. dram_mr5 = <0x400>;
  4653. dram_mr6 = <0x848>;
  4654. };
  4655.  
  4656. memory@40000000 {
  4657. device_type = "memory";
  4658. reg = <0x0 0x40000000 0x0 0x20000000>;
  4659. };
  4660.  
  4661. interrupt-controller@03020000 {
  4662. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  4663. #interrupt-cells = <0x3>;
  4664. #address-cells = <0x0>;
  4665. device_type = "gic";
  4666. interrupt-controller;
  4667. reg = <0x0 0x3021000 0x0 0x1000 0x0 0x3022000 0x0 0x2000 0x0 0x3024000 0x0 0x2000 0x0 0x3026000 0x0 0x2000>;
  4668. interrupts = <0x1 0x9 0xf04>;
  4669. linux,phandle = <0x1>;
  4670. phandle = <0x1>;
  4671. };
  4672.  
  4673. sunxi-sid@03006000 {
  4674. compatible = "allwinner,sunxi-sid";
  4675. device_type = "sid";
  4676. reg = <0x0 0x3006000 0x0 0x1000>;
  4677. };
  4678.  
  4679. sunxi-chipid@03006200 {
  4680. compatible = "allwinner,sunxi-chipid";
  4681. device_type = "chipid";
  4682. reg = <0x0 0x3006200 0x0 0x200>;
  4683. };
  4684.  
  4685. timer {
  4686. compatible = "arm,armv8-timer";
  4687. interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
  4688. clock-frequency = <0x16e3600>;
  4689. };
  4690.  
  4691. pmu {
  4692. compatible = "arm,armv8-pmuv3";
  4693. interrupts = <0x0 0x8c 0x4 0x0 0x8d 0x4 0x0 0x8e 0x4 0x0 0x8f 0x4>;
  4694. };
  4695.  
  4696. dvfs_table {
  4697. compatible = "allwinner,dvfs_table";
  4698. multi-vf-table;
  4699.  
  4700. dvfs_table_0 {
  4701. max_freq = <0x6b49d200>;
  4702. min_freq = <0x1c9c3800>;
  4703. lv_count = <0x8>;
  4704. lv1_freq = <0x6b49d200>;
  4705. lv1_volt = <0x488>;
  4706. lv2_freq = <0x58b11400>;
  4707. lv2_volt = <0x424>;
  4708. lv3_freq = <0x4ead9a00>;
  4709. lv3_volt = <0x3e8>;
  4710. lv4_freq = "@_~";
  4711. lv4_volt = <0x3ac>;
  4712. lv5_freq = <0x34edce00>;
  4713. lv5_volt = <0x370>;
  4714. lv6_freq = <0x0>;
  4715. lv6_volt = <0x370>;
  4716. lv7_freq = <0x0>;
  4717. lv7_volt = <0x370>;
  4718. lv8_freq = <0x0>;
  4719. lv8_volt = <0x370>;
  4720. device_type = "dvfs_table_0";
  4721. };
  4722.  
  4723. dvfs_table_1 {
  4724. max_freq = <0x6b49d200>;
  4725. min_freq = <0x1c9c3800>;
  4726. lv_count = <0x8>;
  4727. lv1_freq = <0x6b49d200>;
  4728. lv1_volt = <0x44c>;
  4729. lv2_freq = <0x58b11400>;
  4730. lv2_volt = <0x3e8>;
  4731. lv3_freq = <0x4ead9a00>;
  4732. lv3_volt = <0x3ac>;
  4733. lv4_freq = "@_~";
  4734. lv4_volt = <0x370>;
  4735. lv5_freq = <0x34edce00>;
  4736. lv5_volt = <0x334>;
  4737. lv6_freq = <0x0>;
  4738. lv6_volt = <0x334>;
  4739. lv7_freq = <0x0>;
  4740. lv7_volt = <0x334>;
  4741. lv8_freq = <0x0>;
  4742. lv8_volt = <0x334>;
  4743. device_type = "dvfs_table_1";
  4744. };
  4745.  
  4746. dvfs_table_2 {
  4747. max_freq = <0x6b49d200>;
  4748. min_freq = <0x1c9c3800>;
  4749. lv_count = <0x8>;
  4750. lv1_freq = <0x6b49d200>;
  4751. lv1_volt = <0x424>;
  4752. lv2_freq = <0x58b11400>;
  4753. lv2_volt = <0x3c0>;
  4754. lv3_freq = <0x4ead9a00>;
  4755. lv3_volt = <0x384>;
  4756. lv4_freq = "@_~";
  4757. lv4_volt = <0x348>;
  4758. lv5_freq = <0x34edce00>;
  4759. lv5_volt = <0x320>;
  4760. lv6_freq = <0x0>;
  4761. lv6_volt = <0x320>;
  4762. lv7_freq = <0x0>;
  4763. lv7_volt = <0x320>;
  4764. lv8_freq = <0x0>;
  4765. lv8_volt = <0x320>;
  4766. device_type = "dvfs_table_2";
  4767. };
  4768. };
  4769.  
  4770. dramfreq {
  4771. compatible = "allwinner,sunxi-dramfreq";
  4772. reg = <0x0 0x4002000 0x0 0x1000 0x0 0x4003000 0x0 0x3000 0x0 0x3001000 0x0 0x1000>;
  4773. interrupts = <0x0 0x21 0x4>;
  4774. clocks = <0xd6>;
  4775. status = "okay";
  4776. };
  4777.  
  4778. uboot {
  4779. };
  4780.  
  4781. iommu@030f0000 {
  4782. compatible = "allwinner,sunxi-iommu";
  4783. reg = <0x0 0x30f0000 0x0 0x1000>;
  4784. interrupts = <0x0 0x39 0x4>;
  4785. interrupt-names = "iommu-irq";
  4786. clocks = <0xd7>;
  4787. clock-names = "iommu";
  4788. #iommu-cells = <0x2>;
  4789. status = "okay";
  4790. linux,phandle = <0x19>;
  4791. phandle = <0x19>;
  4792. };
  4793.  
  4794. gpu@0x01800000 {
  4795. device_type = "gpu";
  4796. compatible = "arm,mali-t720", "arm,mali-midgard";
  4797. reg = <0x0 0x1800000 0x0 0x4000>;
  4798. interrupts = <0x0 0x53 0x4 0x0 0x54 0x4 0x0 0x55 0x4>;
  4799. interrupt-names = "GPU", "JOB", "MMU";
  4800. clocks = <0xd8 0xd9>;
  4801. clock-names = "clk_parent", "clk_mali";
  4802. operating-points = <0xb8920 0xfde80 0x98580 0xe7ef0 0x8ca00 0xe30d0 0x83d60 0xde2b0 0x7b0c0 0xd9490 0x6f540 0xd4670 0x69780 0xd1f60 0x668a0 0xcf850 0x639c0 0xcd140 0x5dc00 0xcaa30 0x57e40 0xc8320 0x52080 0xc5c10 0x4c2c0 0xc5c10 0x40740 0xc5c10 0x34bc0 0xc5c10>;
  4803. gpu_idle = <0x0>;
  4804. dvfs_status = <0x1>;
  4805. temp_ctrl_status = <0x1>;
  4806. scene_ctrl_status = <0x1>;
  4807. max_normal_level = <0xd>;
  4808. };
  4809.  
  4810. wlan {
  4811. compatible = "allwinner,sunxi-wlan";
  4812. wlan_busnum = <0x1>;
  4813. wlan_usbnum = <0x3>;
  4814. wlan_power;
  4815. wlan_io_regulator = "axp806_bldo3";
  4816. status = "okay";
  4817. device_type = "wlan";
  4818. wlan_en = <0xdb 0xb 0x8 0x1 0xffffffff 0xffffffff 0x0>;
  4819. wlan_regon = <0xdb 0xc 0x3 0x1 0xffffffff 0xffffffff 0x0>;
  4820. wlan_hostwake = <0xdb 0xc 0x0 0x0 0xffffffff 0xffffffff 0x0>;
  4821. };
  4822.  
  4823. bt {
  4824. compatible = "allwinner,sunxi-bt";
  4825. clocks = <0xda>;
  4826. bt_power = "vcc-wifi";
  4827. bt_io_regulator = "vcc-wifi-io";
  4828. status = "okay";
  4829. device_type = "bt";
  4830. bt_rst_n = <0xdb 0xc 0x4 0x1 0xffffffff 0xffffffff 0x0>;
  4831. };
  4832.  
  4833. btlpm {
  4834. compatible = "allwinner,sunxi-btlpm";
  4835. uart_index = <0x1>;
  4836. status = "okay";
  4837. device_type = "btlpm";
  4838. bt_hostwake_enable = <0x0>;
  4839. bt_wake = <0xdb 0xc 0x2 0x1 0xffffffff 0xffffffff 0x1>;
  4840. bt_hostwake = <0xdb 0xc 0x1 0x6 0xffffffff 0xffffffff 0x0>;
  4841. };
  4842. };
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