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The Complete Pentium Instruction Set Table

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  1. The Complete Pentium Instruction Set Table
  2. (32 Bit Addressing Mode Only)
  3. by Sang Cho
  4.  
  5. **********************************************
  6. Explanation of the Notation used in this Table
  7. **********************************************
  8.  
  9.  
  10. /digit -- A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses
  11. only the r/m (register or memory) operand. The reg field contains the digit
  12. that provides an extension to the instruction's opcode.
  13. /r -- Indicates that the ModR/M byte of the instruction contains both a register operand
  14. and an r/m operand.
  15. cb -- A relative byte offset from the next instruction for JMP, CALL etc.
  16. cw -- A relative word offset from the next instruciton for JMP, CALL etc.
  17. cd -- A relative doubleword offset from the next instruction for JMP, CALL etc.
  18. cp -- An absolute far pointer for JMP, CALL etc.
  19. ib, iw, id
  20. -- 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand
  21. +rb, +rw, +rd
  22. -- register code, from 0 through 7, added to an opcode byte.
  23.  
  24. rb rw rd
  25. ----------------------
  26. AL = 0 AX = 0 EAX = 0
  27. CL = 1 CX = 1 ECX = 1
  28. DL = 2 DX = 2 EDX = 2
  29. BL = 3 BX = 3 EBX = 3
  30. AH = 4 SP = 4 ESP = 4
  31. CH = 5 BP = 5 EBP = 5
  32. DH = 6 SI = 6 ESI = 6
  33. BH = 7 DI = 7 EDI = 7
  34.  
  35. +i -- A number used in floating-point instructions when one of the operands is ST(i) from
  36. the FPU register stack.
  37. rel8 -- A relative address in the range from -128 to 127 bytes from the end of the instruction.
  38. rel16 and rel32
  39. -- A relative address within the same code segment as the instruction assembled.
  40. ptr16:16 and ptr16:32
  41. -- A far pointer, typically in a code segment different from that of the instruction.
  42. r8 -- One of the byte general-purpose registers.
  43. r16 -- One of the word general-purpose registers.
  44. r32 -- One of the doubleword general-purpose registers.
  45. imm8 -- An immediate byte value.
  46. imm16 -- An immediate word value.
  47. imm32 -- An immediate doubleword value.
  48. r/m8 -- A byte general-purpose register, or a byte from memory.
  49. r/m16 -- A word general-purpose register, or a word memory operand.
  50. r/m32 -- A doubleword general-purpose register, or a doubleword memory operand.
  51. m -- A 16- or 32-bit operand in memory.
  52. m8 -- A byte operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers.
  53. Used with the string instructions and the XLAT instruction.
  54. m16 -- A word operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers.
  55. Used only with the string instructions.
  56. m32 -- A doubleword operand in memory, pointed to by the DS:(E)SI or ES:(E)DI registers.
  57. Used only with the string instructions.
  58. m64 -- A memory quadword operand in memory. Used only with the CMPXCHG8B instruction.
  59. m16:16, m16:32
  60. -- A memory operand containing a far pointer composed of two numbers.
  61. The number to the left of the colon corresponds to the pointer's segment selector.
  62. The number to the right corresponds to its offset.
  63. m16&32, m16&16, m32&32
  64. -- A memory operand consisting of data item pairs whose
  65. sizes are indicated on the left and the right side of the ampersand.
  66. All memory addressing modes are allowed. The m16&16 and m32&32 operands are used
  67. by the BOUND instruction to provide an operand containing an upper and lower bounds
  68. for array indices. The m16&32 operand is used by LIDT and LGDT to provide
  69. a word with which to load the limit field, and a doubleword with which to load
  70. the base field of the corresponding GDTR and IDTR registers.
  71. moffs8, moffs16, moffs32
  72. -- A simple memory variable (memory offset) of type byte,
  73. word, or doubleword used by some variants of the MOV instruction.
  74. The actual address is given by a simple offset relative to the segment base.
  75. No ModR/M byte is used in the instruction. The number shown with moffs indicates
  76. its size, which is determined by the address-size attribute of the instruction.
  77. Sreg -- A segment register. The segment register bit assignments are ES=0, CS=1, SS=2,
  78. DS=3, FS=4, and GS=5.
  79. m32real, m64real, m80real
  80. -- A single-, double-, and extended-real floating-point operand in memory.
  81. m16int, m32int, m64int
  82. -- A word-, short-, and long-integer floating-point operand in memory.
  83. ST or ST(0)
  84. -- The top element of the FPU register stack.
  85. ST(i) -- The i th element from the top of the FPU register stack. (i = 0 through 7)
  86. mm -- An MMX register. The 64-bit MMX registers are: MM0 through MM7.
  87. mm/m32 -- The low order 32 bits of an MMX register or a 32-bit memory operand.
  88. mm/m64 -- An MMX register or a 64-bit memory operand.
  89.  
  90.  
  91.  
  92.  
  93. Alphabetical Listing
  94. ===============================================================================
  95. Opcode,Data Instruction Explanation
  96. -------------------------------------------------------------------------------
  97. 37 AAA ASCII adjust AL after addition
  98. D5 0A AAD ASCII adjust AX before division
  99. D4 0A AAM ASCII adjust AX after multiplication
  100. 3F AAS ASCII adjust AL after subtraction
  101. 14 ib ADC AL,imm8 Add with carry
  102. 15 id ADC EAX,imm32 Add with carry
  103. 80 /2 ib ADC r/m8,imm8 Add with carry
  104. 81 /2 id ADC r/m32,imm32 Add with carry
  105. 83 /2 ib ADC r/m32,imm8 Add with carry
  106. 10 /r ADC r/m8,r8 Add with carry
  107. 11 /r ADC r/m32,r32 Add with carry
  108. 12 /r ADC r8,r/m8 Add with carry
  109. 13 /r ADC r32,r/m32 Add with carry
  110. 04 ib ADD AL,imm8 Add
  111. 05 id ADD EAX,imm32 Add
  112. 80 /0 ib ADD r/m8,imm8 Add
  113. 81 /0 id ADD r/m32,imm32 Add
  114. 83 /0 ib ADD r/m32,imm8 Add
  115. 00 /r ADD r/m8,r8 ADD
  116. 01 /r ADD r/m32,r32 ADD
  117. 02 /r ADD r8,r/m8 ADD
  118. 03 /r ADD r32,r/m32 ADD
  119. 24 ib AND AL,imm8 AND
  120. 25 id AND EAX,imm32 AND
  121. 80 /4 ib AND r/m8,imm8 AND
  122. 81 /4 id AND r/m32,imm32 AND
  123. 83 /4 ib AND r/m32,imm8 AND
  124. 20 /r AND r/m8,r8 AND
  125. 21 /r AND r/m32,r32 AND
  126. 22 /r AND r8,r/m8 AND
  127. 23 /r AND r32,r/m32 AND
  128. 63 /r ARPL r/m16,r16 Adjust Request Privilege Level of Sel.
  129. 62 /r BOUND r32,m32&32 Check Array Index Against Bounds
  130. 0F BC /r BSF r32,r/m32 Bit scan forward on r/m32
  131. 0F BD /r BSR r32,r/m32 Bit scan reverse on r/m32
  132. 0F C8+rd BSWAP r32 Reverses the byte order of a r32
  133. 0F A3 /r BT r/m32,r32 Bit Test
  134. 0F BA /4 ib BT r/m32,imm8 Bit Test
  135. 0F BB /r BTC r/m32,r32 Bit Test and Complement
  136. 0F BA /7 ib BTC r/m32,imm8 Bit Test and Complement
  137. 0F B3 /r BTR r/m32,r32 Bit Test and Clear
  138. 0F BA /6 ib BTR r/m32,imm8 Bit Test and Clear
  139. 0F AB /r BTS r/m32,r32 Bit Test and Set
  140. 0F BA /5 ib BTS r/m32,imm8 Bit Test and Set
  141. E8 cd CALL rel32 Call near, rel to n.inst
  142. FF /2 CALL r/m32 Call near, abs.ind.add. given in r/m32
  143. 9A cp CALL ptr16:32 Call far, abs.add. given in operand
  144. FF /3 CALL m16:32 Call far, abs.ind.add. given in m16:32
  145. 98 CBW Convert Byte to Word
  146. 99 CWD Convert Word to Doubleword
  147. 99 CDQ Convert Doubleword to Quadword
  148. F8 CLC Clear CF flag
  149. FC CLD Clear DF flag
  150. FA CLI Clear interrupt flag
  151. 0F 06 CLTS Clear Task-Switched Flag in Control Reg. Zero
  152. F5 CMC Complement CF flag
  153. 0F 47 /r CMOVA r32,r/m32 Move if above
  154. 0F 43 /r CMOVAE r32,r/m32 Move if above or equal
  155. 0F 42 /r CMOVB r32,r/m32 Move if below
  156. 0F 46 /r CMOVBE r32,r/m32 Move if below or equal
  157. 0F 42 /r CMOVC r32,r/m32 Move if carry
  158. 0F 44 /r CMOVE r32,r/m32 Move if equal
  159. 0F 4F /r CMOVG r32,r/m32 Move if greater
  160. 0F 4D /r CMOVGE r32,r/m32 Move if greater or equal
  161. 0F 4C /r CMOVL r32,r/m32 Move if less
  162. 0F 4E /r CMOVLE r32,r/m32 Move if less or equal
  163. 0F 46 /r CMOVNA r32,r/m32 Move if not above
  164. 0F 42 /r CMOVNAE r32,r/m32 Move if not above or equal
  165. 0F 43 /r CMOVNB r32,r/m32 Move if not below
  166. 0F 47 /r CMOVNBE r32,r/m32 Move if not below or equal
  167. 0F 43 /r CMOVNC r32,r/m32 Move if not carry
  168. 0F 45 /r CMOVNE r32,r/m32 Move if not equal
  169. 0F 4E /r CMOVNG r32,r/m32 Move if not greater
  170. 0F 4C /r CMOVNGE r32,r/m32 Move if not greater or equal
  171. 0F 4D /r CMOVNL r32,r/m32 Move if not less
  172. 0F 4F /r CMOVNLE r32,r/m32 Move if not less or equal
  173. 0F 41 /r CMOVNO r32,r/m32 Move if not overflow
  174. 0F 4B /r CMOVNP r32,r/m32 Move if not parity
  175. 0F 49 /r CMOVNS r32,r/m32 Move if not sign
  176. 0F 45 /r CMOVNZ r32,r/m32 Move if not zero
  177. 0F 40 /r CMOVO r32,r/m32 Move if overflow
  178. 0F 4A /r CMOVP r32,r/m32 Move if parity
  179. 0F 4A /r CMOVPE r32,r/m32 Move if parity even
  180. 0F 4B /r CMOVPO r32,r/m32 Move if parity odd
  181. 0F 48 /r CMOVS r32,r/m32 Move if sign
  182. 0F 44 /r CMOVZ r32,r/m32 Move if zero
  183. 3C ib CMP AL,imm8 Compare
  184. 3D id CMP EAX,imm32 Compare
  185. 80 /7 ib CMP r/m8,imm8 Compare
  186. 81 /7 id CMP r/m32,imm32 Compare
  187. 83 /7 ib CMP r/m32,imm8 Compare
  188. 38 /r CMP r/m8,r8 Compare
  189. 39 /r CMP r/m32,r32 Compare
  190. 3A /r CMP r8,r/m8 Compare
  191. 3B /r CMP r32,r/m32 Compare
  192. A6 CMPSB Compare byte at DS:(E)SI with ES:(E)DI
  193. A7 CMPSD Compare dw at DS:(E)SI with ES:(E)DI
  194. 0F B0 /r CMPXCHG r/m8,r8 Compare and Exchange
  195. 0F B1 /r CMPXCHG r/m32,r32 Compare and Exchange
  196. 0F C7 /1 m64 CMPXCHG8B m64 Compare and Exchange
  197. 0F A2 CPUID EAX := Processor id.info.
  198. 27 DAA Decimal adjust AL after addition
  199. 2F DAS Decimal adjust AL after subtraction
  200. FE /1 DEC r/m8 Decrement r/m8 by 1
  201. FF /1 DEC r/m32 Decrement r/m32 by 1
  202. 48+rd DEC r32 Decrement r32 by 1
  203. F6 /6 DIV r/m8 Unsigned divide AX by r/m8
  204. F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16
  205. F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32
  206. 0F 77 EMMS Set the FP tag word to empty
  207. C8 iw 00 ENTER imm16,0 Create a stack frame for a procedure
  208. C8 iw 01 ENTER imm16,1 Create a nested stack frame for a proc.
  209. C8 iw ib ENTER imm16,imm8 Create a nested stack frame for a proc.
  210. D9 F0 F2XM1 Replace ST(0) with 2**ST(0) - 1
  211. D9 E1 FABS Replace ST(0) with its absolute value
  212. D8 /0 FADD m32real Add m32real to ST(0) and s.r. in ST(0)
  213. DC /0 FADD m64real Add m64real to ST(0) and s.r.in ST(0)
  214. D8 C0+i FADD ST(0),ST(i) Add ST(0) to ST(i) and s.r.in ST(0)
  215. DC C0+i FADD ST(i),ST(0) Add ST(i) to ST(0) and s.r. in ST(i)
  216. DE C0+i FADDP ST(i),ST(0) Add ST(0) to ST(i), s.r.in ST(i),pop r.stack
  217. DE C1 FADDP Add ST(0) to ST(1), s.r.in ST(1),pop r.stack
  218. DA /0 FIADD m32int Add m32int to ST(0) and s.r.in ST(0)
  219. DE /0 FIADD m16int Add m16int to ST(0) and s.r.in ST(0)
  220. DF /4 FBLD m80bcd Convert m80BCD to real and push
  221. DF /6 FBSTP m80bcd Store ST(0) in m80bcd and pop ST(0)
  222. D9 E0 FCHS Complements sign of ST(0)
  223. 9B DB E2 FCLEX Clear f.e.f. after checking for ..
  224. DB E2 FNCLEX Clear f.e.f. without checking for ..
  225. DA C0+i FCMOVB ST(0),ST(i) Move if below
  226. DA C8+i FCMOVE ST(0),ST(i) Move if equal
  227. DA D0+i FCMOVBE ST(0),ST(i) Move if below or equal
  228. DA D8+i FCMOVU ST(0),ST(i) Move if unordered
  229. DB C0+i FCMOVNB ST(0),ST(i) Move if not below
  230. DB C8+i FCMOVNE ST(0),ST(i) Move if not equal
  231. DB D0+i FCMOVNBE ST(0),ST(i) Move if not below or equal
  232. DB D8+i FCMOVNU ST(0),ST(i) Move if not unordered
  233. D8 /2 FCOM m32real Compare ST(0) with m32real.
  234. DC /2 FCOM m64real Compare ST(0) with m64real.
  235. D8 D0+i FCOM ST(i) Compare ST(0) with ST(i).
  236. D8 D1 FCOM Compare ST(0) with ST(1).
  237. D8 /3 FCOMP m32real Compare ST(0) with m32real,pop r.stack.
  238. DC /3 FCOMP m64real Compare ST(0) with m64real,pop r.stack.
  239. D8 D8+i FCOMP ST(i) Compare ST(0) with ST(i), pop
  240. D8 D9 FCOMP Compare ST(0) with ST(1), pop
  241. DE D9 FCOMPP Compare ST(0) with ST(1), pop pop
  242. DB F0+i FCOMI ST,ST(i) Compare ST(0) with ST(i), set status flags
  243. DF F0+i FCOMIP ST,ST(i) Compare ST(0) with ST(i), set s.f. ,pop
  244. DB E8+i FUCOMI ST,ST(i) Compare ST(0) with ST(i), check o.v.set s.f.
  245. DF E8+i FUCOMIP ST,ST(i) Compare ST(0) with ST(i), check ovssf pop
  246. D9 FF FCOS Replace ST(0) with its cosine
  247. D9 F6 FDECSTP Decrement TOP field in FPU status word.
  248. D8 /6 FDIV m32real Divide ST(0) by m32real and s.r.in ST(0)
  249. DC /6 FDIV m64real Divide ST(0) by m64real and s.r.in ST(0)
  250. D8 F0+i FDIV ST(0),ST(i) Divide ST(0) by ST(i) and s.r.in ST(0)
  251. DC F8+i FDIV ST(i),ST(0) Divide ST(i) by ST(0) and s.r.in ST(i)
  252. DE F8+i FDIVP ST(i),ST(0) Divide ST(i) by ST(0), s.r.in ST(i) pop
  253. DE F9 FDIVP Divide ST(1) by ST(0), s.r.in ST(1) pop
  254. DA /6 FIDIV m32int Divide ST(0) by m32int and s.r.in ST(0)
  255. DE /6 FIDIV m16int Divide ST(0) by m64int and s.r.in ST(0)
  256. D8 /7 FDIVR m32real Divide m32real by ST(0) and s.r.in ST(0)
  257. DC /7 FDIVR m64real Divide m64real by ST(0) and s.r.in ST(0)
  258. D8 F8+i FDIVR ST(0),ST(i) Divide ST(i) by ST(0) and s.r.in ST(0)
  259. DC F0+i FDIVR ST(i),ST(0) Divide ST(0) by ST(i) and s.r.in ST(i)
  260. DE F0+i FDIVRP ST(i),ST(0) Divide ST(0) by ST(i), s.r.in ST(i) pop
  261. DE F1 FDIVRP Divide ST(0) by ST(1), s.r.in ST(1) pop
  262. DA /7 FIDIVR m32int Divide m32int by ST(0) and s.r.in ST(0)
  263. DE /7 FIDIVR m16int Divide m64int by ST(0) and s.r.in ST(0)
  264. DD C0+i FFREE ST(i) Sets tag for ST(i) to empty
  265. DE /2 FICOM m16int Compare ST(0) with m16int
  266. DA /2 FICOM m32int Compare ST(0) with m32int
  267. DE /3 FICOMP m16int Compare ST(0) with m16int and pop
  268. DA /3 FICOMP m32int Compare ST(0) with m32int and pop
  269. DF /0 FILD m16int Push m16int
  270. DB /0 FILD m32int Push m32int
  271. DF /5 FILD m64int Push m64int
  272. D9 F7 FINCSTP Increment the TOP field FPU status r.
  273. 9B DB E3 FINIT Initialize FPU after ...
  274. DB E3 FNINIT Initialize FPU without ...
  275. DF /2 FIST m16int Store ST(0) in m16int
  276. DB /2 FIST m32int Store ST(0) in m32int
  277. DF /3 FISTP m16int Store ST(0) in m16int and pop
  278. DB /3 FISTP m32int Store ST(0) in m32int and pop
  279. DF /7 FISTP m64int Store ST(0) in m64int and pop
  280. D9 /0 FLD m32real Push m32real
  281. DD /0 FLD m64real Push m64real
  282. DB /5 FLD m80real Push m80real
  283. D9 C0+i FLD ST(i) Push ST(i)
  284. D9 E8 FLD1 Push +1.0
  285. D9 E9 FLDL2T Push log2 10
  286. D9 EA FLDL2E Push log2 e
  287. D9 EB FLDPI Push pi
  288. D9 EC FLDLG2 Push log10 2
  289. D9 ED FLDLN2 Push loge 2
  290. D9 EE FLDZ Push +0.0
  291. D9 /5 FLDCW m2byte Load FPU control word from m2byte
  292. D9 /4 FLDENV m14/28byte Load FPU environment from m14/m28
  293. D8 /1 FMUL m32real Multiply ST(0) by m32real and s.r.in ST(0)
  294. DC /1 FMUL m64real Multiply ST(0) by m64real and s.r.in ST(0)
  295. D8 C8+i FMUL ST(0),ST(i) Multiply ST(0) by ST(i) and s.r.in ST(0)
  296. DC C8+i FMUL ST(i),ST(0) Multiply ST(i) by ST(0) and s.r.in ST(i)
  297. DE C8+i FMULP ST(i),ST(0) Multiply ST(i) by ST(0), s.r.in ST(i) pop
  298. DE C9 FMULP Multiply ST(1) by ST(0), s.r.in ST(1) pop
  299. DA /1 FIMUL m32int Multiply ST(0) by m32int and s.r.in ST(0)
  300. DE /1 FIMUL m16int Multiply ST(0) by m16int and s.r.in ST(0)
  301. D9 D0 FNOP No operation is performed
  302. D9 F3 FPATAN Repalces ST(1) with arctan(ST(1)/ST(0)) pop
  303. D9 F8 FPREM Replaces ST(0) with rem (ST(0)/ST(1))
  304. D9 F5 FPREM1 Replaces ST(0) with IEEE rem(ST(0)/ST(1))
  305. D9 F2 FPTAN Replaces ST(0) with its tangent push 1.0
  306. D9 FC FRNDINT Round ST(0) to an integer
  307. DD /4 FRSTOR m94/108byte Load FPU status from m94 or m108 byte
  308. 9B DD /6 FSAVE m94/108byte Store FPU status to m94 or m108
  309. DD /6 FNSAVE m94/108byte Store FPU environment to m94 or m108
  310. D9 FD FSCALE Scale ST(0) by ST(1)
  311. D9 FE FSIN Replace ST(0) with its sine
  312. D9 FB FSINCOS Compute sine and consine of ST(0) s push c
  313. D9 FA FSQRT square root of ST(0)
  314. D9 /2 FST m32real Copy ST(0) to m32real
  315. DD /2 FST m64real Copy ST(0) to m64real
  316. DD D0+i FST ST(i) Copy ST(0) to ST(i)
  317. D9 /3 FSTP m32real Copy ST(0) to m32real and pop
  318. DD /3 FSTP m64real Copy ST(0) to m64real and pop
  319. DB /7 FSTP m80real Copy ST(0) to m80real and pop
  320. DD D8+i FSTP ST(i) Copy ST(0) to ST(i) and pop
  321. 9B D9 /7 FSTCW m2byte Store FPU control word
  322. D9 /7 FNSTCW m2byte Store FPU control word without
  323. 9B D9 /6 FSTENV m14/28byte Store FPU environment
  324. D9 /6 FNSTENV m14/28byte Store FPU env without
  325. 9B DD /7 FSTSW m2byte Store FPU status word at m2byte after
  326. 9B DF E0 FSTSW AX Store FPU status word in AX after
  327. DD /7 FNSTSW m2byte Store FPU status word at m2byte without
  328. DF E0 FNSTSW AX Store FPU status word in AX without
  329. D8 /4 FSUB m32real Sub m32real from ST(0) and s.r.in ST(0)
  330. DC /4 FSUB m64real Sub m64real from ST(0) and s.r.in ST(0)
  331. D8 E0+i FSUB ST(0),ST(i) Sub ST(i) from ST(0) and s.r.in ST(0)
  332. DC E8+i FSUB ST(i),ST(0) Sub ST(0) from ST(i) and s.r.in ST(i)
  333. DE E8+i FSUBP ST(i),ST(0) Sub ST(0) from ST(i), s.r.in ST(i) pop
  334. DE E9 FSUBP Sub ST(0) from ST(1), s.r.in ST(1) pop
  335. DA /4 FISUB m32int Sub m32int from ST(0) and s.r.in ST(0)
  336. DE /4 FISUB m16int Sub m16int from ST(0) and s.r.in ST(0)
  337. D8 /5 FSUBR m32real Sub ST(0) from m32real and s.r.in ST(0)
  338. DC /5 FSUBR m64real Sub ST(0) from m64real and s.r.in ST(0)
  339. D8 E8+i FSUBR ST(0),ST(i) Sub ST(0) from ST(i) and s.r.in ST(0)
  340. DC E0+i FSUBR ST(i),ST(0) Sub ST(i) from ST(0) and s.r.in ST(i)
  341. DE E0+i FSUBRP ST(i),ST(0) Sub ST(i) from ST(0), s.r. in ST(i) pop
  342. DE E1 FSUBRP Sub ST(1) from ST(0), s.r.in ST(1) pop
  343. DA /5 FISUBR m32int Sub ST(0) from m32int and s.r.in ST(0)
  344. DE /5 FISUBR m16int Sub ST(0) from m16int and s.r.in ST(0)
  345. D9 E4 FTST Compare ST(0) with 0.0
  346. DD E0+i FUCOM ST(i) Compare ST(0) with ST(i)
  347. DD E1 FUCOM Compare ST(0) with ST(1)
  348. DD E8+i FUCOMP ST(i) Compare ST(0) with ST(i) and pop
  349. DD E9 FUCOMP Compare ST(0) with ST(1) and pop
  350. DA E9 FUCOMPP Compare ST(0) with ST(1) and pop pop
  351. D9 E5 FXAM Classify value or number in ST(0)
  352. D9 C8+i FXCH ST(i) Exchange ST(0) and ST(i)
  353. D9 C9 FXCH Exchange ST(0) and ST(1)
  354. D9 F4 FXTRACT Seperate value in ST(0) exp. and sig.
  355. D9 F1 FYL2X Replace ST(1) with ST(1)*log2ST(0) and pop
  356. D9 F9 FYL2XP1 Replace ST(1) with ST(1)*log2(ST(0)+1) pop
  357. F4 HLT Halt
  358. F6 /7 IDIV r/m8 Divide
  359. F7 /7 IDIV r/m32 Divide
  360. F6 /5 IMUL r/m8 Multiply
  361. F7 /5 IMUL r/m32 Multiply
  362. 0F AF /r IMUL r32,r/m32 Multiply
  363. 6B /r ib IMUL r32,r/m32,imm8 Multiply
  364. 6B /r ib IMUL r32,imm8 Multiply
  365. 69 /r id IMUL r32,r/m32,imm32 Multiply
  366. 69 /r id IMUL r32,imm32 Multiply
  367. E4 ib IN AL,imm8 Input byte from imm8 I/O port address into AL
  368. E5 ib IN EAX,imm8 Input byte from imm8 I/O port address into EAX
  369. EC IN AL,DX Input byte from I/O port in DX into AL
  370. ED IN EAX,DX Input doubleword from I/O port in DX into EAX
  371. FE /0 INC r/m8 Increment 1
  372. FF /0 INC r/m32 Increment 1
  373. 40+rd INC r32 Increment register by 1
  374. 6C INS m8 Input byte from I/O(DX) into ES:(E)DI
  375. 6D INS m32 Input dw from I/O(DX) into ES:(E)DI
  376. CC INT 3 Interrupt 3--trap to debugger
  377. CD ib INT imm8 Interrupt vector number (imm8)
  378. CE INTO Interrupt 4--if overflow flag is 1
  379. 0F 08 INVD Flush internal caches
  380. 0F 01 /7 INVLPG m Invalidate TLB Entry for page (m)
  381. CF IRETD Interrupt return(32)
  382. 77 cb JA rel8 Jump short if above
  383. 73 cb JAE rel8 Jump short if above or equal
  384. 76 cb JBE rel8 Jump short if below or equal
  385. 72 cb JC rel8 Jump short if carry
  386. E3 cb JECXZ rel8 Jump short if ECX register is 0
  387. 74 cb JE rel8 Jump short if equal
  388. 7F cb JG rel8 Jump short if greater
  389. 7D cb JGE rel8 Jump short if greater or equal
  390. 7C cb JL rel8 Jump short if less
  391. 7E cb JLE rel8 Jump short if less or equal
  392. 75 cb JNE rel8 Jump short if not equal
  393. 71 cb JNO rel8 Jump short if not overflow
  394. 79 cb JNS rel8 Jump short if not sign
  395. 70 cb JO rel8 Jump short if overflow
  396. 7A cb JPE rel8 Jump short if parity even
  397. 7B cb JPO rel8 Jump short if parity odd
  398. 78 cb JS rel8 Jump short if sign
  399. 0F 87 cd JA rel32 Jump near if above
  400. 0F 83 cd JAE rel32 Jump near if above or equal
  401. 0F 82 cd JB rel32 Jump near if below
  402. 0F 86 cd JBE rel32 Jump near if below or equal
  403. 0F 84 cd JE rel32 Jump near if equal
  404. 0F 8F cd JG rel32 Jump near if greater
  405. 0F 8D cd JGE rel32 Jump near if greater or equal
  406. 0F 8C cd JL rel32 Jump near if less
  407. 0F 8E cd JLE rel32 Jump near if less or equal
  408. 0F 85 cd JNE rel32 Jump near if not equal
  409. 0F 81 cd JNO rel32 Jump near if not overflow
  410. 0F 89 cd JNS rel32 Jump near if not sign
  411. 0F 80 cd JO rel32 Jump near if overflow
  412. 0F 8A cd JPE rel32 Jump near if parity even
  413. 0F 8B cd JPO rel32 Jump near if parity odd
  414. 0F 88 cd JS rel32 Jump near if sign
  415. EB cb JMP rel8 Jump short, relative,
  416. E9 cd JMP rel32 Jump near, relative,
  417. FF /4 JMP r/m32 Jump near, abs.ind.in r/m32
  418. EA cp JMP ptr16:32 Jump far, abs.add given in operand
  419. FF /r JMP m16:32 Jump far, abs.ind.in m16:32
  420. 9F LAHF Load Status Flags into AH
  421. 0F 02 /r LAR r32,r/m32 Load Access Rights Byte
  422. C5 /r LDS r32,m16:32 Load DS:r32 with far ptr
  423. 8D /r LEA r32,m Load effective address
  424. C9 LEAVE Set ESP to EBP, then pop EBP
  425. C4 /r LES r32,m16:32 Load ES:r32 with far ptr
  426. 0F B4 /r LFS r32,m16:32 Load FS:r32 with far ptr
  427. 0F B5 /r LGS r32,m16:32 Load GS:r32 with far ptr
  428. 0F 01 /2 LGDT m16&32 Load m into GDTR
  429. 0F 01 /3 LIDT m16&32 Load m into IDTR
  430. 0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR
  431. 0F 01 /6 LMSW r/m16 Load r/m16 in machine status word of CR0
  432. F0 LOCK Asserts LOCK signal for duration ..
  433. AC LODS m8 Load byte at address DS:(E)SI into AL
  434. AD LODS m32 Load dword at address DS:(E)SI into EAX
  435. E2 cb LOOP rel8 Dec count;jump if count # 0
  436. E1 cb LOOPE rel8 Dec count;jump if count # 0 and ZF=1
  437. E1 cb LOOPZ rel8 Dec count;jump if count # 0 and ZF=1
  438. E0 cb LOOPNE rel8 Dec count;jump if count # 0 and ZF=0
  439. E0 cb LOOPNZ rel8 Dec count;jump if count # 0 and ZF=0
  440. 0F 03 /r LSL r16,r/m16 Load Segment Limit
  441. 0F 03 /r LSL r32,r/m32 Load Segment Limit
  442. 0F B2 /r LSS r32,m16:32 Load SS:r32 with far ptr
  443. 0F 00 /3 LTR r/m16 Load Task Register
  444. 88 /r MOV r/m8,r8 Move
  445. 89 /r MOV r/m32,r32 Move
  446. 8A /r MOV r8,r/m8 Move
  447. 8B /r MOV r32,r/m32 Move
  448. 8C /r MOV r/m16,Sreg** Move segment register to r/m16
  449. 8E /r MOV Sreg,r/m16** Move r/m16 to segment register
  450. A0 MOV AL, moffs8* Move byte at ( seg:offset) to AL
  451. A1 MOV AX, moffs16* Move word at ( seg:offset) to AX
  452. A1 MOV EAX, moffs32* Move dword at ( seg:offset) to EAX
  453. A2 MOV moffs8*,AL Move AL to ( seg:offset)
  454. A3 MOV moffs16*,AX Move AX to ( seg:offset)
  455. A3 MOV moffs32*,EAX Move EAX to ( seg:offset)
  456. B0+rb MOV r8,imm8 Move imm8 to r8
  457. B8+rd MOV r32,imm32 Move imm32 to r32
  458. C6 /0 ib MOV r/m8,imm8 Move imm8 to r/m8
  459. C7 /0 id MOV r/m32,imm32 Move imm32 to r/m32
  460. 0F 22 /r MOV CR0, r32 Move r32 to CR0
  461. 0F 22 /r MOV CR2, r32 Move r32 to CR2
  462. 0F 22 /r MOV CR3, r32 Move r32 to CR3
  463. 0F 22 /r MOV CR4, r32 Move r32 to CR4
  464. 0F 20 /r MOV r32,CR0 Move CR0 to r32
  465. 0F 20 /r MOV r32,CR2 Move CR2 to r32
  466. 0F 20 /r MOV r32,CR3 Move CR3 to r32
  467. 0F 20 /r MOV r32,CR4 Move CR4 to r32
  468. 0F 21 /r MOV r32,DR0-DR7 Move debug register to r32
  469. 0F 23 /r MOV DR0-DR7,r32 Move r32 to debug register
  470. 0F 6E /r MOVD mm,r/m32 Move doubleword from r/m32 to mm
  471. 0F 7E /r MOVD r/m32,mm Move doubleword from mm to r/m32
  472. 0F 6F /r MOVQ mm,mm/m64 Move quadword from mm/m64 to mm
  473. 0F 7F /r MOVQ mm/m64,mm Move quadword from mm to mm/m64
  474. A4 MOVS m8,m8 Move byte at DS:(E)SI to ES:(E)DI
  475. A5 MOVS m32,m32 Move dword at DS:(E)SI to ES:(E)DI
  476. 0F BE /r MOVSX r32,r/m8 Move byte to doubleword, sign-extension
  477. 0F BF /r MOVSX r32,r/m16 Move word to doubleword, sign-extension
  478. 0F B6 /r MOVZX r32,r/m8 Move byte to doubleword, zero-extension
  479. 0F B7 /r MOVZX r32,r/m16 Move word to doubleword, zero-extension
  480. F6 /4 MUL r/m8 Unsigned multiply
  481. F7 /4 MUL r/m32 Unsigned multiply
  482. F6 /3 NEG r/m8 Two's complement negate r/m8
  483. F7 /3 NEG r/m32 Two's complement negate r/m32
  484. 90 NOP No operation
  485. F6 /2 NOT r/m8 Reverse each bit of r/m8
  486. F7 /2 NOT r/m32 Reverse each bit of r/m32
  487. 0C ib OR AL,imm8 OR
  488. 0D id OR EAX,imm32 OR
  489. 80 /1 ib OR r/m8,imm8 OR
  490. 81 /1 id OR r/m32,imm32 OR
  491. 83 /1 ib OR r/m32,imm8 OR
  492. 08 /r OR r/m8,r8 OR
  493. 09 /r OR r/m32,r32 OR
  494. 0A /r OR r8,r/m8 OR
  495. 0B /r OR r32,r/m32 OR
  496. E6 ib OUT imm8,AL Output byte in AL to I/O(imm8)
  497. E7 ib OUT imm8,EAX Output dword in EAX to I/O(imm8)
  498. EE OUT DX,AL Output byte in AL to I/O(DX)
  499. EF OUT DX,EAX Output dword in EAX to I/O(DX)
  500. 6E OUTS DX,m8 Output byte from DS:(E)SI to I/O(DX)
  501. 6F OUTS DX,m32 Output dword from DS:(E)SI to I/O (DX)
  502. 0F 63 /r PACKSSWB mm,mm/m64 Pack with Signed Saturation
  503. 0F 6B /r PACKSSDW mm,mm/m64 Pack with Signed Saturation
  504. 0F 67 /r PACKUSWB mm,mm/m64 Pack with Unsigned Saturation
  505. 0F FC /r PADDB mm,mm/m64 Add packed bytes
  506. 0F FD /r PADDW mm,mm/m64 Add packed words
  507. 0F FE /r PADDD mm,mm/m64 Add packed dwords
  508. 0F EC /r PADDSB mm,mm/m64 Add signed packed bytes
  509. 0F ED /r PADDSW mm,mm/m64 Add signed packed words
  510. 0F DC /r PADDUSB mm,mm/m64 Add unsigned pkd bytes
  511. 0F DD /r PADDUSW mm,mm/m64 Add unsigned pkd words
  512. 0F DB /r PAND mm,mm/m64 AND quadword from .. to ..
  513. 0F DF /r PANDN mm,mm/m64 And qword from .. to NOT qw in mm
  514. 0F 74 /r PCMPEQB mm,mm/m64 Packed Compare for Equal
  515. 0F 75 /r PCMPEQW mm,mm/m64 Packed Compare for Equal
  516. 0F 76 /r PCMPEQD mm,mm/m64 Packed Compare for Equal
  517. 0F 64 /r PCMPGTB mm,mm/m64 Packed Compare for GT
  518. 0F 65 /r PCMPGTW mm,mm/m64 Packed Compare for GT
  519. 0F 66 /r PCMPGTD mm,mm/m64 Packed Compare for GT
  520. 0F F5 /r PMADDWD mm,mm/m64 Packed Multiply and Add
  521. 0F E5 /r PMULHW mm,mm/m64 Packed Multiply High
  522. 0F D5 /r PMULLW mm,mm/m64 Packed Multiply Low
  523. 8F /0 POP m32 Pop m32
  524. 58+rd POP r32 Pop r32
  525. 1F POP DS Pop DS
  526. 07 POP ES Pop ES
  527. 17 POP SS Pop SS
  528. 0F A1 POP FS Pop FS
  529. 0F A9 POP GS Pop GS
  530. 61 POPAD Pop EDI,... and EAX
  531. 9D POPFD Pop Stack into EFLAGS Register
  532. 0F EB /r POR mm,mm/m64 OR qword from .. to mm
  533. 0F F1 /r PSLLW mm,mm/m64 Packed Shift Left Logical
  534. 0F 71 /6 ib PSLLW mm,imm8 Packed Shift Left Logical
  535. 0F F2 /r PSLLD mm,mm/m64 Packed Shift Left Logical
  536. 0F 72 /6 ib PSLLD mm,imm8 Packed Shift Left Logical
  537. 0F F3 /r PSLLQ mm,mm/m64 Packed Shift Left Logical
  538. 0F 73 /6 ib PSLLQ mm,imm8 Packed Shift Left Logical
  539. 0F E1 /r PSRAW mm,mm/m64 Packed Shift Right Arithmetic
  540. 0F 71 /4 ib PSRAW mm,imm8 Packed Shift Right Arithmetic
  541. 0F E2 /r PSRAD mm,mm/m64 Packed Shift Right Arithmetic
  542. 0F 72 /4 ib PSRAD mm,imm8 Packed Shift Right Arithmetic
  543. 0F D1 /r PSRLW mm,mm/m64 Packed Shift Right Logical
  544. 0F 71 /2 ib PSRLW mm,imm8 Packed Shift Right Logical
  545. 0F D2 /r PSRLD mm,mm/m64 Packed Shift Right Logical
  546. 0F 72 /2 ib PSRLD mm,imm8 Packed Shift Right Logical
  547. 0F D3 /r PSRLQ mm,mm/m64 Packed Shift Right Logical
  548. 0F 73 /2 ib PSRLQ mm,imm8 Packed Shift Right Logical
  549. 0F F8 /r PSUBB mm,mm/m64 Packed Subtract
  550. 0F F9 /r PSUBW mm,mm/m64 Packed Subtract
  551. 0F FA /r PSUBD mm,mm/m64 Packed Subtract
  552. 0F E8 /r PSUBSB mm,mm/m64 Packed Subtract with Saturation
  553. 0F E9 /r PSUBSW mm,mm/m64 Packed Subtract with Saturation
  554. 0F D8 /r PSUBUSB mm,mm/m64 Packed Subtract Unsigned with S.
  555. 0F D9 /r PSUBUSW mm,mm/m64 Packed Subtract Unsigned with S.
  556. 0F 68 /r PUNPCKHBW mm,mm/m64 Unpack High Packed Data
  557. 0F 69 /r PUNPCKHWD mm,mm/m64 Unpack High Packed Data
  558. 0F 6A /r PUNPCKHDQ mm,mm/m64 Unpack High Packed Data
  559. 0F 60 /r PUNPCKLBW mm,mm/m64 Unpack Low Packed Data
  560. 0F 61 /r PUNPCKLWD mm,mm/m64 Unpack Low Packed Data
  561. 0F 62 /r PUNPCKLDQ mm,mm/m64 Unpack Low Packed Data
  562. FF /6 PUSH r/m32 Push r/m32
  563. 50+rd PUSH r32 Push r32
  564. 6A ib PUSH imm8 Push imm8
  565. 68 id PUSH imm32 Push imm32
  566. 0E PUSH CS Push CS
  567. 16 PUSH SS Push SS
  568. 1E PUSH DS Push DS
  569. 06 PUSH ES Push ES
  570. 0F A0 PUSH FS Push FS
  571. 0F A8 PUSH GS Push GS
  572. 60 PUSHAD Push All g-regs
  573. 9C PUSHFD Push EFLAGS
  574. 0F EF /r PXOR mm,mm/m64 XOR qword
  575. D0 /2 RCL r/m8,1 Rotate 9 bits left once
  576. D2 /2 RCL r/m8,CL Rotate 9 bits left CL times
  577. C0 /2 ib RCL r/m8,imm8 Rotate 9 bits left imm8 times
  578. D1 /2 RCL r/m32,1 Rotate 33 bits left once
  579. D3 /2 RCL r/m32,CL Rotate 33 bits left CL times
  580. C1 /2 ib RCL r/m32,imm8 Rotate 33 bits left imm8 times
  581. D0 /3 RCR r/m8,1 Rotate 9 bits right once
  582. D2 /3 RCR r/m8,CL Rotate 9 bits right CL times
  583. C0 /3 ib RCR r/m8,imm8 Rotate 9 bits right imm8 times
  584. D1 /3 RCR r/m32,1 Rotate 33 bits right once
  585. D3 /3 RCR r/m32,CL Rotate 33 bits right CL times
  586. C1 /3 ib RCR r/m32,imm8 Rotate 33 bits right imm8 times
  587. D0 /0 ROL r/m8,1 Rotate 8 bits r/m8 left once
  588. D2 /0 ROL r/m8,CL Rotate 8 bits r/m8 left CL times
  589. C0 /0 ib ROL r/m8,imm8 Rotate 8 bits r/m8 left imm8 times
  590. D1 /0 ROL r/m32,1 Rotate 32 bits r/m32 left once
  591. D3 /0 ROL r/m32,CL Rotate 32 bits r/m32 left CL times
  592. C1 /0 ib ROL r/m32,imm8 Rotate 32 bits r/m32 left imm8 times
  593. D0 /1 ROR r/m8,1 Rotate 8 bits r/m8 right once
  594. D2 /1 ROR r/m8,CL Rotate 8 bits r/m8 right CL times
  595. C0 /1 ib ROR r/m8,imm8 Rotate 8 bits r/m16 right imm8 times
  596. D1 /1 ROR r/m32,1 Rotate 32 bits r/m32 right once
  597. D3 /1 ROR r/m32,CL Rotate 32 bits r/m32 right CL times
  598. C1 /1 ib ROR r/m32,imm8 Rotate 32 bits r/m32 right imm8 times
  599. 0F 32 RDMSR Read from Model Specific Register
  600. 0F 33 RDPMC Read Performance-Monitoring counters
  601. 0F 31 RDTSC Read Time-Stamp Counter
  602. F3 6C REP INS m8,DX Input ECX bytes from port DX into ES:[(E)DI]
  603. F3 6D REP INS m32,DX Input ECX dwords from port DX into ES:[(E)DI]
  604. F3 A4 REP MOVS m8,m8 Move ECX bytes from DS:[(E)SI] to ES:[(E)DI]
  605. F3 A5 REP MOVS m32,m32 Move ECX dwords from DS:[(E)SI] to ES:[(E)DI]
  606. F3 6E REP OUTS DX,m8 Output ECX bytes from DS:[(E)SI] to port DX
  607. F3 6F REP OUTS DX,m32 Output ECX dwords from DS:[(E)SI] to port DX
  608. F3 AC REP LODS AL Load ECX bytes from DS:[(E)SI] to AL
  609. F3 AD REP LODS EAX Load ECX dwords from DS:[(E)SI] to EAX
  610. F3 AA REP STOS m8 Fill ECX bytes at ES:[(E)DI] with AL
  611. F3 AB REP STOS m32 Fill ECX dwords at ES:[(E)DI] with EAX
  612. F3 A6 REPE CMPS m8,m8 Find nonmatching bytes in m and m
  613. F3 A7 REPE CMPS m32,m32 Find nonmatching dwords in m and m
  614. F3 AE REPE SCAS m8 Find non-AL byte starting at
  615. F3 AF REPE SCAS m32 Find non-EAX dword starting at
  616. F2 A6 REPNE CMPS m8,m8 Find matching bytes in m and m
  617. F2 A7 REPNE CMPS m32,m32 Find matching dwords in m and m
  618. F2 AE REPNE SCAS m8 Find AL, starting at ES:[(E)DI]
  619. F2 AF REPNE SCAS m32 Find EAX, starting at ES:[(E)DI]
  620. C3 RET Near return
  621. CB RET Far return
  622. C2 iw RET imm16 Near return, pop imm16 bytes from stack
  623. CA iw RET imm16 Far return, pop imm16 bytes from stack
  624. 0F AA RSM Resume from System Management
  625. 9E SAHF Store AH into Flags
  626. D0 /4 SAL r/m8,1 Shift Arithmetic Left
  627. D2 /4 SAL r/m8,CL Shift Arithmetic Left
  628. C0 /4 ib SAL r/m8,imm8 Shift Arithmetic Left
  629. D1 /4 SAL r/m32,1 Shift Arithmetic Left
  630. D3 /4 SAL r/m32,CL Shift Arithmetic Left
  631. C1 /4 ib SAL r/m32,imm8 Shift Arithmetic Left
  632. D0 /7 SAR r/m8,1 Shift Arithmetic Right
  633. D2 /7 SAR r/m8,CL Shift Arithmetic Right
  634. C0 /7 ib SAR r/m8,imm8 Shift Arithmetic Right
  635. D1 /7 SAR r/m32,1 Shift Arithmetic Right
  636. D3 /7 SAR r/m32,CL Shift Arithmetic Right
  637. C1 /7 ib SAR r/m32,imm8 Shift Arithmetic Right
  638. D0 /4 SHL r/m8,1 Shift Logical Left
  639. D2 /4 SHL r/m8,CL Shift Logical Left
  640. C0 /4 ib SHL r/m8,imm8 Shift Logical Left
  641. D1 /4 SHL r/m32,1 Shift Logical Left
  642. D3 /4 SHL r/m32,CL Shift Logical Left
  643. C1 /4 ib SHL r/m32,imm8 Shift Logical Left
  644. D0 /5 SHR r/m8,1 Shift Logical Right
  645. D2 /5 SHR r/m8,CL Shift Logical Right
  646. C0 /5 ib SHR r/m8,imm8 Shift Logical Right
  647. D1 /5 SHR r/m32,1 Shift Logical Right
  648. D3 /5 SHR r/m32,CL Shift Logical Right
  649. C1 /5 ib SHR r/m32,imm8 Shift Logical Right
  650. 1C ib SBB AL,imm8 Subtract with borrow
  651. 1D id SBB EAX,imm32 Subtract with borrow
  652. 80 /3 ib SBB r/m8,imm8 Subtract with borrow
  653. 81 /3 id SBB r/m32,imm32 Subtract with borrow
  654. 83 /3 ib SBB r/m32,imm8 Subtract with borrow
  655. 18 /r SBB r/m8,r8 Subtract with borrow
  656. 19 /r SBB r/m32,r32 Subtract with borrow
  657. 1A /r SBB r8,r/m8 Subtract with borrow
  658. 1B /r SBB r32,r/m32 Subtract with borrow
  659. AE SCAS m8 Scan String
  660. AF SCAS m32 Scan String
  661. 0F 97 /r SETA r/m8 Set byte if above
  662. 0F 93 /r SETAE r/m8 Set byte if above or equal
  663. 0F 92 /r SETB r/m8 Set byte if below
  664. 0F 96 /r SETBE r/m8 Set byte if below or equal
  665. 0F 94 /r SETE r/m8 Set byte if equal
  666. 0F 9F /r SETG r/m8 Set byte if greater
  667. 0F 9D /r SETGE r/m8 Set byte if greater or equal
  668. 0F 9C /r SETL r/m8 Set byte if less
  669. 0F 9E /r SETLE r/m8 Set byte if less or equal
  670. 0F 95 /r SETNE r/m8 Set byte if not equal
  671. 0F 91 /r SETNO r/m8 Set byte if not overflow
  672. 0F 99 /r SETNS r/m8 Set byte if not sign
  673. 0F 90 /r SETO r/m8 Set byte if overflow
  674. 0F 9A /r SETPE r/m8 Set byte if parity even
  675. 0F 9B /r SETPO r/m8 Set byte if parity odd
  676. 0F 98 /r SETS r/m8 Set byte if sign
  677. 0F 01 /0 SGDT m Store GDTR to m
  678. 0F 01 /1 SIDT m Store IDTR to m
  679. 0F A4 /r ib SHLD r/m32,r32,imm8 Double Precision Shift Left
  680. 0F A5 /r SHLD r/m32,r32,CL Double Precision Shift Left
  681. 0F AC /r ib SHRD r/m32,r32,imm8 Double Precision Shift Right
  682. 0F AD /r SHRD r/m32,r32,CL Double Precision Shift Right
  683. 0F 00 /0 SLDT r/m32 Store Local Descriptor Table Register
  684. 0F 01 /4 SMSW r/m32 Store Machine Status Word
  685. F9 STC Set Carry Flag
  686. FD STD Set Direction Flag
  687. FB STI Set Interrup Flag
  688. AA STOS m8 Store String
  689. AB STOS m32 Store String
  690. 0F 00 /1 STR r/m16 Store Task Register
  691. 2C ib SUB AL,imm8 Subtract
  692. 2D id SUB EAX,imm32 Subtract
  693. 80 /5 ib SUB r/m8,imm8 Subtract
  694. 81 /5 id SUB r/m32,imm32 Subtract
  695. 83 /5 ib SUB r/m32,imm8 Subtract
  696. 28 /r SUB r/m8,r8 Subtract
  697. 29 /r SUB r/m32,r32 Subtract
  698. 2A /r SUB r8,r/m8 Subtract
  699. 2B /r SUB r32,r/m32 Subtract
  700. A8 ib TEST AL,imm8 Logical Compare
  701. A9 id TEST EAX,imm32 Logical Compare
  702. F6 /0 ib TEST r/m8,imm8 Logical Compare
  703. F7 /0 id TEST r/m32,imm32 Logical Compare
  704. 84 /r TEST r/m8,r8 Logical Compare
  705. 85 /r TEST r/m16,r16 Logical Compare
  706. 85 /r TEST r/m32,r32 Logical Compare
  707. 0F 0B UD2 Undifined Instruction
  708. 0F 00 /4 VERR r/m16 Verify a Segment for Reading
  709. 0F 00 /5 VERW r/m16 Verify a Segment for Writing
  710. 9B WAIT Wait
  711. 9B FWAIT Wait
  712. 0F 09 WBINVD Write Back and Invalidate Cache
  713. 0F 30 WRMSR Write to Model Specific Register
  714. 0F C0 /r XADD r/m8,r8 Exchange and Add
  715. 0F C1 /r XADD r/m16,r16 Exchange and Add
  716. 0F C1 /r XADD r/m32,r32 Exchange and Add
  717. 90+rd XCHG EAX,r32 Exchange r32 with EAX
  718. 90+rd XCHG r32,EAX Exchange EAX with r32
  719. 86 /r XCHG r/m8,r8 Exchange byte
  720. 86 /r XCHG r8,r/m8 Exchange byte
  721. 87 /r XCHG r/m32,r32 Exchange doubleword
  722. 87 /r XCHG r32,r/m32 Exchange doubleword
  723. D7 XLAT m8 Table Look-up Translation
  724. 34 ib XOR AL,imm8 Logical Exclusive OR
  725. 35 id XOR EAX,imm32 Logical Exclusive OR
  726. 80 /6 ib XOR r/m8,imm8 Logical Exclusive OR
  727. 81 /6 id XOR r/m32,imm32 Logical Exclusive OR
  728. 83 /6 ib XOR r/m32,imm8 Logical Exclusive OR
  729. 30 /r XOR r/m8,r8 Logical Exclusive OR
  730. 31 /r XOR r/m32,r32 Logical Exclusive OR
  731. 32 /r XOR r8,r/m8 Logical Exclusive OR
  732. 33 /r XOR r32,r/m32 Logical Exclusive OR
  733.  
  734.  
  735. Opcode ordered Listing
  736. ===============================================================================
  737. Opcode,Data Instruction Explanation
  738. -------------------------------------------------------------------------------
  739. 00 /r ADD r/m8,r8 ADD
  740. 01 /r ADD r/m32,r32 ADD
  741. 02 /r ADD r8,r/m8 ADD
  742. 03 /r ADD r32,r/m32 ADD
  743. 04 ib ADD AL,imm8 Add
  744. 05 id ADD EAX,imm32 Add
  745. 06 PUSH ES Push ES
  746. 07 POP ES Pop ES
  747. 08 /r OR r/m8,r8 OR
  748. 09 /r OR r/m32,r32 OR
  749. 0A /r OR r8,r/m8 OR
  750. 0B /r OR r32,r/m32 OR
  751. 0C ib OR AL,imm8 OR
  752. 0D id OR EAX,imm32 OR
  753. 0E PUSH CS Push CS
  754. 0F 00 /0 SLDT r/m32 Store Local Descriptor Table Register
  755. 0F 00 /1 STR r/m16 Store Task Register
  756. 0F 00 /2 LLDT r/m16 Load segment selector r/m16 into LDTR
  757. 0F 00 /3 LTR r/m16 Load Task Register
  758. 0F 00 /4 VERR r/m16 Verify a Segment for Reading
  759. 0F 00 /5 VERW r/m16 Verify a Segment for Writing
  760. 0F 01 /0 SGDT m Store GDTR to m
  761. 0F 01 /1 SIDT m Store IDTR to m
  762. 0F 01 /2 LGDT m16&32 Load m into GDTR
  763. 0F 01 /3 LIDT m16&32 Load m into IDTR
  764. 0F 01 /4 SMSW r/m32 Store Machine Status Word
  765. 0F 01 /6 LMSW r/m16 Load r/m16 in machine status word of CR0
  766. 0F 01 /7 INVLPG m Invalidate TLB Entry for page (m)
  767. 0F 02 /r LAR r32,r/m32 Load Access Rights Byte
  768. 0F 03 /r LSL r16,r/m16 Load Segment Limit
  769. 0F 03 /r LSL r32,r/m32 Load Segment Limit
  770. 0F 06 CLTS Clear Task-Switched Flag in Control Reg. Zero
  771. 0F 08 INVD Flush internal caches
  772. 0F 09 WBINVD Write Back and Invalidate Cache
  773. 0F 0B UD2 Undifined Instruction
  774. 0F 20 /r MOV r32,CR0 Move CR0 to r32
  775. 0F 20 /r MOV r32,CR2 Move CR2 to r32
  776. 0F 20 /r MOV r32,CR3 Move CR3 to r32
  777. 0F 20 /r MOV r32,CR4 Move CR4 to r32
  778. 0F 21 /r MOV r32,DR0-DR7 Move debug register to r32
  779. 0F 22 /r MOV CR0, r32 Move r32 to CR0
  780. 0F 22 /r MOV CR2, r32 Move r32 to CR2
  781. 0F 22 /r MOV CR3, r32 Move r32 to CR3
  782. 0F 22 /r MOV CR4, r32 Move r32 to CR4
  783. 0F 23 /r MOV DR0-DR7,r32 Move r32 to debug register
  784. 0F 30 WRMSR Write to Model Specific Register
  785. 0F 31 RDTSC Read Time-Stamp Counter
  786. 0F 32 RDMSR Read from Model Specific Register
  787. 0F 33 RDPMC Read Performance-Monitoring counters
  788. 0F 40 /r CMOVO r32,r/m32 Move if overflow
  789. 0F 41 /r CMOVNO r32,r/m32 Move if not overflow
  790. 0F 42 /r CMOVB r32,r/m32 Move if below
  791. 0F 42 /r CMOVC r32,r/m32 Move if carry
  792. 0F 42 /r CMOVNAE r32,r/m32 Move if not above or equal
  793. 0F 43 /r CMOVAE r32,r/m32 Move if above or equal
  794. 0F 43 /r CMOVNB r32,r/m32 Move if not below
  795. 0F 43 /r CMOVNC r32,r/m32 Move if not carry
  796. 0F 44 /r CMOVE r32,r/m32 Move if equal
  797. 0F 44 /r CMOVZ r32,r/m32 Move if zero
  798. 0F 45 /r CMOVNE r32,r/m32 Move if not equal
  799. 0F 45 /r CMOVNZ r32,r/m32 Move if not zero
  800. 0F 46 /r CMOVBE r32,r/m32 Move if below or equal
  801. 0F 46 /r CMOVNA r32,r/m32 Move if not above
  802. 0F 47 /r CMOVA r32,r/m32 Move if above
  803. 0F 47 /r CMOVNBE r32,r/m32 Move if not below or equal
  804. 0F 48 /r CMOVS r32,r/m32 Move if sign
  805. 0F 49 /r CMOVNS r32,r/m32 Move if not sign
  806. 0F 4A /r CMOVP r32,r/m32 Move if parity
  807. 0F 4A /r CMOVPE r32,r/m32 Move if parity even
  808. 0F 4B /r CMOVNP r32,r/m32 Move if not parity
  809. 0F 4B /r CMOVPO r32,r/m32 Move if parity odd
  810. 0F 4C /r CMOVL r32,r/m32 Move if less
  811. 0F 4C /r CMOVNGE r32,r/m32 Move if not greater or equal
  812. 0F 4D /r CMOVGE r32,r/m32 Move if greater or equal
  813. 0F 4D /r CMOVNL r32,r/m32 Move if not less
  814. 0F 4E /r CMOVLE r32,r/m32 Move if less or equal
  815. 0F 4E /r CMOVNG r32,r/m32 Move if not greater
  816. 0F 4F /r CMOVG r32,r/m32 Move if greater
  817. 0F 4F /r CMOVNLE r32,r/m32 Move if not less or equal
  818. 0F 60 /r PUNPCKLBW mm,mm/m64 Unpack Low Packed Data
  819. 0F 61 /r PUNPCKLWD mm,mm/m64 Unpack Low Packed Data
  820. 0F 62 /r PUNPCKLDQ mm,mm/m64 Unpack Low Packed Data
  821. 0F 63 /r PACKSSWB mm,mm/m64 Pack with Signed Saturation
  822. 0F 64 /r PCMPGTB mm,mm/m64 Packed Compare for GT
  823. 0F 65 /r PCMPGTW mm,mm/m64 Packed Compare for GT
  824. 0F 66 /r PCMPGTD mm,mm/m64 Packed Compare for GT
  825. 0F 67 /r PACKUSWB mm,mm/m64 Pack with Unsigned Saturation
  826. 0F 68 /r PUNPCKHBW mm,mm/m64 Unpack High Packed Data
  827. 0F 69 /r PUNPCKHWD mm,mm/m64 Unpack High Packed Data
  828. 0F 6A /r PUNPCKHDQ mm,mm/m64 Unpack High Packed Data
  829. 0F 6B /r PACKSSDW mm,mm/m64 Pack with Signed Saturation
  830. 0F 6E /r MOVD mm,r/m32 Move doubleword from r/m32 to mm
  831. 0F 6F /r MOVQ mm,mm/m64 Move quadword from mm/m64 to mm
  832. 0F 71 /2 ib PSRLW mm,imm8 Packed Shift Right Logical
  833. 0F 71 /4 ib PSRAW mm,imm8 Packed Shift Right Arithmetic
  834. 0F 71 /6 ib PSLLW mm,imm8 Packed Shift Left Logical
  835. 0F 72 /2 ib PSRLD mm,imm8 Packed Shift Right Logical
  836. 0F 72 /4 ib PSRAD mm,imm8 Packed Shift Right Arithmetic
  837. 0F 72 /6 ib PSLLD mm,imm8 Packed Shift Left Logical
  838. 0F 73 /2 ib PSRLQ mm,imm8 Packed Shift Right Logical
  839. 0F 73 /6 ib PSLLQ mm,imm8 Packed Shift Left Logical
  840. 0F 74 /r PCMPEQB mm,mm/m64 Packed Compare for Equal
  841. 0F 75 /r PCMPEQW mm,mm/m64 Packed Compare for Equal
  842. 0F 76 /r PCMPEQD mm,mm/m64 Packed Compare for Equal
  843. 0F 77 EMMS Set the FP tag word to empty
  844. 0F 7E /r MOVD r/m32,mm Move doubleword from mm to r/m32
  845. 0F 7F /r MOVQ mm/m64,mm Move quadword from mm to mm/m64
  846. 0F 80 cd JO rel32 Jump near if overflow
  847. 0F 81 cd JNO rel32 Jump near if not overflow
  848. 0F 82 cd JB rel32 Jump near if below
  849. 0F 83 cd JAE rel32 Jump near if above or equal
  850. 0F 84 cd JE rel32 Jump near if equal
  851. 0F 85 cd JNE rel32 Jump near if not equal
  852. 0F 86 cd JBE rel32 Jump near if below or equal
  853. 0F 87 cd JA rel32 Jump near if above
  854. 0F 88 cd JS rel32 Jump near if sign
  855. 0F 89 cd JNS rel32 Jump near if not sign
  856. 0F 8A cd JPE rel32 Jump near if parity even
  857. 0F 8B cd JPO rel32 Jump near if parity odd
  858. 0F 8C cd JL rel32 Jump near if less
  859. 0F 8D cd JGE rel32 Jump near if greater or equal
  860. 0F 8E cd JLE rel32 Jump near if less or equal
  861. 0F 8F cd JG rel32 Jump near if greater
  862. 0F 90 /r SETO r/m8 Set byte if overflow
  863. 0F 91 /r SETNO r/m8 Set byte if not overflow
  864. 0F 92 /r SETB r/m8 Set byte if below
  865. 0F 93 /r SETAE r/m8 Set byte if above or equal
  866. 0F 94 /r SETE r/m8 Set byte if equal
  867. 0F 95 /r SETNE r/m8 Set byte if not equal
  868. 0F 96 /r SETBE r/m8 Set byte if below or equal
  869. 0F 97 /r SETA r/m8 Set byte if above
  870. 0F 98 /r SETS r/m8 Set byte if sign
  871. 0F 99 /r SETNS r/m8 Set byte if not sign
  872. 0F 9A /r SETPE r/m8 Set byte if parity even
  873. 0F 9B /r SETPO r/m8 Set byte if parity odd
  874. 0F 9C /r SETL r/m8 Set byte if less
  875. 0F 9D /r SETGE r/m8 Set byte if greater or equal
  876. 0F 9E /r SETLE r/m8 Set byte if less or equal
  877. 0F 9F /r SETG r/m8 Set byte if greater
  878. 0F A0 PUSH FS Push FS
  879. 0F A1 POP FS Pop FS
  880. 0F A2 CPUID EAX := Processor id.info.
  881. 0F A3 /r BT r/m32,r32 Bit Test
  882. 0F A4 /r ib SHLD r/m32,r32,imm8 Double Precision Shift Left
  883. 0F A5 /r SHLD r/m32,r32,CL Double Precision Shift Left
  884. 0F A8 PUSH GS Push GS
  885. 0F A9 POP GS Pop GS
  886. 0F AA RSM Resume from System Management
  887. 0F AB /r BTS r/m32,r32 Bit Test and Set
  888. 0F AC /r ib SHRD r/m32,r32,imm8 Double Precision Shift Right
  889. 0F AD /r SHRD r/m32,r32,CL Double Precision Shift Right
  890. 0F AF /r IMUL r32,r/m32 Multiply
  891. 0F B0 /r CMPXCHG r/m8,r8 Compare and Exchange
  892. 0F B1 /r CMPXCHG r/m32,r32 Compare and Exchange
  893. 0F B2 /r LSS r32,m16:32 Load SS:r32 with far ptr
  894. 0F B3 /r BTR r/m32,r32 Bit Test and Clear
  895. 0F B4 /r LFS r32,m16:32 Load FS:r32 with far ptr
  896. 0F B5 /r LGS r32,m16:32 Load GS:r32 with far ptr
  897. 0F B6 /r MOVZX r32,r/m8 Move byte to doubleword, zero-extension
  898. 0F B7 /r MOVZX r32,r/m16 Move word to doubleword, zero-extension
  899. 0F BA /4 ib BT r/m32,imm8 Bit Test
  900. 0F BA /5 ib BTS r/m32,imm8 Bit Test and Set
  901. 0F BA /6 ib BTR r/m32,imm8 Bit Test and Clear
  902. 0F BA /7 ib BTC r/m32,imm8 Bit Test and Complement
  903. 0F BB /r BTC r/m32,r32 Bit Test and Complement
  904. 0F BC /r BSF r32,r/m32 Bit scan forward on r/m32
  905. 0F BD /r BSR r32,r/m32 Bit scan reverse on r/m32
  906. 0F BE /r MOVSX r32,r/m8 Move byte to doubleword, sign-extension
  907. 0F BF /r MOVSX r32,r/m16 Move word to doubleword, sign-extension
  908. 0F C0 /r XADD r/m8,r8 Exchange and Add
  909. 0F C1 /r XADD r/m16,r16 Exchange and Add
  910. 0F C1 /r XADD r/m32,r32 Exchange and Add
  911. 0F C7 /1 m64 CMPXCHG8B m64 Compare and Exchange
  912. 0F C8+rd BSWAP r32 Reverses the byte order of a r32
  913. 0F D1 /r PSRLW mm,mm/m64 Packed Shift Right Logical
  914. 0F D2 /r PSRLD mm,mm/m64 Packed Shift Right Logical
  915. 0F D3 /r PSRLQ mm,mm/m64 Packed Shift Right Logical
  916. 0F D5 /r PMULLW mm,mm/m64 Packed Multiply Low
  917. 0F D8 /r PSUBUSB mm,mm/m64 Packed Subtract Unsigned with S.
  918. 0F D9 /r PSUBUSW mm,mm/m64 Packed Subtract Unsigned with S.
  919. 0F DB /r PAND mm,mm/m64 AND quadword from .. to ..
  920. 0F DC /r PADDUSB mm,mm/m64 Add unsigned pkd bytes
  921. 0F DD /r PADDUSW mm,mm/m64 Add unsigned pkd words
  922. 0F DF /r PANDN mm,mm/m64 And qword from .. to NOT qw in mm
  923. 0F E1 /r PSRAW mm,mm/m64 Packed Shift Right Arithmetic
  924. 0F E2 /r PSRAD mm,mm/m64 Packed Shift Right Arithmetic
  925. 0F E5 /r PMULHW mm,mm/m64 Packed Multiply High
  926. 0F E8 /r PSUBSB mm,mm/m64 Packed Subtract with Saturation
  927. 0F E9 /r PSUBSW mm,mm/m64 Packed Subtract with Saturation
  928. 0F EB /r POR mm,mm/m64 OR qword from .. to mm
  929. 0F EC /r PADDSB mm,mm/m64 Add signed packed bytes
  930. 0F ED /r PADDSW mm,mm/m64 Add signed packed words
  931. 0F EF /r PXOR mm,mm/m64 XOR qword
  932. 0F F1 /r PSLLW mm,mm/m64 Packed Shift Left Logical
  933. 0F F2 /r PSLLD mm,mm/m64 Packed Shift Left Logical
  934. 0F F3 /r PSLLQ mm,mm/m64 Packed Shift Left Logical
  935. 0F F5 /r PMADDWD mm,mm/m64 Packed Multiply and Add
  936. 0F F8 /r PSUBB mm,mm/m64 Packed Subtract
  937. 0F F9 /r PSUBW mm,mm/m64 Packed Subtract
  938. 0F FA /r PSUBD mm,mm/m64 Packed Subtract
  939. 0F FC /r PADDB mm,mm/m64 Add packed bytes
  940. 0F FD /r PADDW mm,mm/m64 Add packed words
  941. 0F FE /r PADDD mm,mm/m64 Add packed dwords
  942. 10 /r ADC r/m8,r8 Add with carry
  943. 11 /r ADC r/m32,r32 Add with carry
  944. 12 /r ADC r8,r/m8 Add with carry
  945. 13 /r ADC r32,r/m32 Add with carry
  946. 14 ib ADC AL,imm8 Add with carry
  947. 15 id ADC EAX,imm32 Add with carry
  948. 16 PUSH SS Push SS
  949. 17 POP SS Pop SS
  950. 18 /r SBB r/m8,r8 Subtract with borrow
  951. 19 /r SBB r/m32,r32 Subtract with borrow
  952. 1A /r SBB r8,r/m8 Subtract with borrow
  953. 1B /r SBB r32,r/m32 Subtract with borrow
  954. 1C ib SBB AL,imm8 Subtract with borrow
  955. 1D id SBB EAX,imm32 Subtract with borrow
  956. 1E PUSH DS Push DS
  957. 1F POP DS Pop DS
  958. 20 /r AND r/m8,r8 AND
  959. 21 /r AND r/m32,r32 AND
  960. 22 /r AND r8,r/m8 AND
  961. 23 /r AND r32,r/m32 AND
  962. 24 ib AND AL,imm8 AND
  963. 25 id AND EAX,imm32 AND
  964. 26 ES: Segment overide prefix
  965. 27 DAA Decimal adjust AL after addition
  966. 28 /r SUB r/m8,r8 Subtract
  967. 29 /r SUB r/m32,r32 Subtract
  968. 2A /r SUB r8,r/m8 Subtract
  969. 2B /r SUB r32,r/m32 Subtract
  970. 2C ib SUB AL,imm8 Subtract
  971. 2D id SUB EAX,imm32 Subtract
  972. 2E CS: Segment overide prefix
  973. 2F DAS Decimal adjust AL after subtraction
  974. 30 /r XOR r/m8,r8 Logical Exclusive OR
  975. 31 /r XOR r/m32,r32 Logical Exclusive OR
  976. 32 /r XOR r8,r/m8 Logical Exclusive OR
  977. 33 /r XOR r32,r/m32 Logical Exclusive OR
  978. 34 ib XOR AL,imm8 Logical Exclusive OR
  979. 35 id XOR EAX,imm32 Logical Exclusive OR
  980. 36 SS: Segment overide prefix
  981. 37 AAA ASCII adjust AL after addition
  982. 38 /r CMP r/m8,r8 Compare
  983. 39 /r CMP r/m32,r32 Compare
  984. 3A /r CMP r8,r/m8 Compare
  985. 3B /r CMP r32,r/m32 Compare
  986. 3C ib CMP AL,imm8 Compare
  987. 3D id CMP EAX,imm32 Compare
  988. 3E DS: Segment overide prefix
  989. 3F AAS ASCII adjust AL after subtraction
  990. 40+rd INC r32 Increment register by 1
  991. 48+rd DEC r32 Decrement r32 by 1
  992. 50+rd PUSH r32 Push r32
  993. 58+rd POP r32 Pop r32
  994. 60 PUSHAD Push All g-regs
  995. 61 POPAD Pop EDI,... and EAX
  996. 62 /r BOUND r32,m32&32 Check Array Index Against Bounds
  997. 63 /r ARPL r/m16,r16 Adjust Request Privilege Level of Sel.
  998. 64 FS: Segment overide prefix
  999. 65 GS: Segment overide prefix
  1000. 66 Opsize: Operand size overide prefix
  1001. 67 Address: Address size overide prefix
  1002. 68 id PUSH imm32 Push imm32
  1003. 69 /r id IMUL r32,imm32 Multiply
  1004. 69 /r id IMUL r32,r/m32,imm32 Multiply
  1005. 6A ib PUSH imm8 Push imm8
  1006. 6B /r ib IMUL r32,imm8 Multiply
  1007. 6B /r ib IMUL r32,r/m32,imm8 Multiply
  1008. 6C INS m8 Input byte from I/O(DX) into ES:(E)DI
  1009. 6D INS m32 Input dw from I/O(DX) into ES:(E)DI
  1010. 6E OUTS DX,m8 Output byte from DS:(E)SI to I/O(DX)
  1011. 6F OUTS DX,m32 Output dword from DS:(E)SI to I/O (DX)
  1012. 70 cb JO rel8 Jump short if overflow
  1013. 71 cb JNO rel8 Jump short if not overflow
  1014. 72 cb JC rel8 Jump short if carry
  1015. 73 cb JAE rel8 Jump short if above or equal
  1016. 74 cb JE rel8 Jump short if equal
  1017. 75 cb JNE rel8 Jump short if not equal
  1018. 76 cb JBE rel8 Jump short if below or equal
  1019. 77 cb JA rel8 Jump short if above
  1020. 78 cb JS rel8 Jump short if sign
  1021. 79 cb JNS rel8 Jump short if not sign
  1022. 7A cb JPE rel8 Jump short if parity even
  1023. 7B cb JPO rel8 Jump short if parity odd
  1024. 7C cb JL rel8 Jump short if less
  1025. 7D cb JGE rel8 Jump short if greater or equal
  1026. 7E cb JLE rel8 Jump short if less or equal
  1027. 7F cb JG rel8 Jump short if greater
  1028. 80 /0 ib ADD r/m8,imm8 Add
  1029. 80 /1 ib OR r/m8,imm8 OR
  1030. 80 /2 ib ADC r/m8,imm8 Add with carry
  1031. 80 /3 ib SBB r/m8,imm8 Subtract with borrow
  1032. 80 /4 ib AND r/m8,imm8 AND
  1033. 80 /5 ib SUB r/m8,imm8 Subtract
  1034. 80 /6 ib XOR r/m8,imm8 Logical Exclusive OR
  1035. 80 /7 ib CMP r/m8,imm8 Compare
  1036. 81 /0 id ADD r/m32,imm32 Add
  1037. 81 /1 id OR r/m32,imm32 OR
  1038. 81 /2 id ADC r/m32,imm32 Add with carry
  1039. 81 /3 id SBB r/m32,imm32 Subtract with borrow
  1040. 81 /4 id AND r/m32,imm32 AND
  1041. 81 /5 id SUB r/m32,imm32 Subtract
  1042. 81 /6 id XOR r/m32,imm32 Logical Exclusive OR
  1043. 81 /7 id CMP r/m32,imm32 Compare
  1044. 83 /0 ib ADD r/m32,imm8 Add
  1045. 83 /1 ib OR r/m32,imm8 OR
  1046. 83 /2 ib ADC r/m32,imm8 Add with carry
  1047. 83 /3 ib SBB r/m32,imm8 Subtract with borrow
  1048. 83 /4 ib AND r/m32,imm8 AND
  1049. 83 /5 ib SUB r/m32,imm8 Subtract
  1050. 83 /6 ib XOR r/m32,imm8 Logical Exclusive OR
  1051. 83 /7 ib CMP r/m32,imm8 Compare
  1052. 84 /r TEST r/m8,r8 Logical Compare
  1053. 85 /r TEST r/m16,r16 Logical Compare
  1054. 85 /r TEST r/m32,r32 Logical Compare
  1055. 86 /r XCHG r/m8,r8 Exchange byte
  1056. 86 /r XCHG r8,r/m8 Exchange byte
  1057. 87 /r XCHG r/m32,r32 Exchange doubleword
  1058. 87 /r XCHG r32,r/m32 Exchange doubleword
  1059. 88 /r MOV r/m8,r8 Move
  1060. 89 /r MOV r/m32,r32 Move
  1061. 8A /r MOV r8,r/m8 Move
  1062. 8B /r MOV r32,r/m32 Move
  1063. 8C /r MOV r/m16,Sreg** Move segment register to r/m16
  1064. 8D /r LEA r32,m Load effective address
  1065. 8E /r MOV Sreg,r/m16** Move r/m16 to segment register
  1066. 8F /0 POP m32 Pop m32
  1067. 90 NOP No operation
  1068. 90+rd XCHG EAX,r32 Exchange r32 with EAX
  1069. 90+rd XCHG r32,EAX Exchange EAX with r32
  1070. 98 CBW Convert Byte to Word
  1071. 99 CDQ Convert Doubleword to Quadword
  1072. 99 CWD Convert Word to Doubleword
  1073. 9A cp CALL ptr16:32 Call far, abs.add. given in operand
  1074. 9B FWAIT Wait
  1075. 9B WAIT Wait
  1076. 9B D9 /6 FSTENV m14/28byte Store FPU environment
  1077. 9B D9 /7 FSTCW m2byte Store FPU control word
  1078. 9B DB E2 FCLEX Clear f.e.f. after checking for ..
  1079. 9B DB E3 FINIT Initialize FPU after ...
  1080. 9B DD /6 FSAVE m94/108byte Store FPU status to m94 or m108
  1081. 9B DD /7 FSTSW m2byte Store FPU status word at m2byte after
  1082. 9B DF E0 FSTSW AX Store FPU status word in AX after
  1083. 9C PUSHFD Push EFLAGS
  1084. 9D POPFD Pop Stack into EFLAGS Register
  1085. 9E SAHF Store AH into Flags
  1086. 9F LAHF Load Status Flags into AH
  1087. A0 MOV AL, moffs8* Move byte at ( seg:offset) to AL
  1088. A1 MOV AX, moffs16* Move word at ( seg:offset) to AX
  1089. A1 MOV EAX, moffs32* Move dword at ( seg:offset) to EAX
  1090. A2 MOV moffs8*,AL Move AL to ( seg:offset)
  1091. A3 MOV moffs16*,AX Move AX to ( seg:offset)
  1092. A3 MOV moffs32*,EAX Move EAX to ( seg:offset)
  1093. A4 MOVS m8,m8 Move byte at DS:(E)SI to ES:(E)DI
  1094. A5 MOVS m32,m32 Move dword at DS:(E)SI to ES:(E)DI
  1095. A6 CMPSB Compare byte at DS:(E)SI with ES:(E)DI
  1096. A7 CMPSD Compare dw at DS:(E)SI with ES:(E)DI
  1097. A8 ib TEST AL,imm8 Logical Compare
  1098. A9 id TEST EAX,imm32 Logical Compare
  1099. AA STOS m8 Store String
  1100. AB STOS m32 Store String
  1101. AC LODS m8 Load byte at address DS:(E)SI into AL
  1102. AD LODS m32 Load dword at address DS:(E)SI into EAX
  1103. AE SCAS m8 Scan String
  1104. AF SCAS m32 Scan String
  1105. B0+rb MOV r8,imm8 Move imm8 to r8
  1106. B8+rd MOV r32,imm32 Move imm32 to r32
  1107. C0 /0 ib ROL r/m8,imm8 Rotate 8 bits r/m8 left imm8 times
  1108. C0 /1 ib ROR r/m8,imm8 Rotate 8 bits r/m16 right imm8 times
  1109. C0 /2 ib RCL r/m8,imm8 Rotate 9 bits left imm8 times
  1110. C0 /3 ib RCR r/m8,imm8 Rotate 9 bits right imm8 times
  1111. C0 /4 ib SAL r/m8,imm8 Shift Arithmetic Left
  1112. C0 /4 ib SHL r/m8,imm8 Shift Logical Left
  1113. C0 /5 ib SHR r/m8,imm8 Shift Logical Right
  1114. C0 /7 ib SAR r/m8,imm8 Shift Arithmetic Right
  1115. C1 /0 ib ROL r/m32,imm8 Rotate 32 bits r/m32 left imm8 times
  1116. C1 /1 ib ROR r/m32,imm8 Rotate 32 bits r/m32 right imm8 times
  1117. C1 /2 ib RCL r/m32,imm8 Rotate 33 bits left imm8 times
  1118. C1 /3 ib RCR r/m32,imm8 Rotate 33 bits right imm8 times
  1119. C1 /4 ib SAL r/m32,imm8 Shift Arithmetic Left
  1120. C1 /4 ib SHL r/m32,imm8 Shift Logical Left
  1121. C1 /5 ib SHR r/m32,imm8 Shift Logical Right
  1122. C1 /7 ib SAR r/m32,imm8 Shift Arithmetic Right
  1123. C2 iw RET imm16 Near return, pop imm16 bytes from stack
  1124. C3 RET Near return
  1125. C4 /r LES r32,m16:32 Load ES:r32 with far ptr
  1126. C5 /r LDS r32,m16:32 Load DS:r32 with far ptr
  1127. C6 /0 ib MOV r/m8,imm8 Move imm8 to r/m8
  1128. C7 /0 id MOV r/m32,imm32 Move imm32 to r/m32
  1129. C8 iw 00 ENTER imm16,0 Create a stack frame for a procedure
  1130. C8 iw 01 ENTER imm16,1 Create a nested stack frame for a proc.
  1131. C8 iw ib ENTER imm16,imm8 Create a nested stack frame for a proc.
  1132. C9 LEAVE Set ESP to EBP, then pop EBP
  1133. CA iw RET imm16 Far return, pop imm16 bytes from stack
  1134. CB RET Far return
  1135. CC INT 3 Interrupt 3--trap to debugger
  1136. CD ib INT imm8 Interrupt vector number (imm8)
  1137. CE INTO Interrupt 4--if overflow flag is 1
  1138. CF IRETD Interrupt return(32)
  1139. D0 /0 ROL r/m8,1 Rotate 8 bits r/m8 left once
  1140. D0 /1 ROR r/m8,1 Rotate 8 bits r/m8 right once
  1141. D0 /2 RCL r/m8,1 Rotate 9 bits left once
  1142. D0 /3 RCR r/m8,1 Rotate 9 bits right once
  1143. D0 /4 SAL r/m8,1 Shift Arithmetic Left
  1144. D0 /4 SHL r/m8,1 Shift Logical Left
  1145. D0 /5 SHR r/m8,1 Shift Logical Right
  1146. D0 /7 SAR r/m8,1 Shift Arithmetic Right
  1147. D1 /0 ROL r/m32,1 Rotate 32 bits r/m32 left once
  1148. D1 /1 ROR r/m32,1 Rotate 32 bits r/m32 right once
  1149. D1 /2 RCL r/m32,1 Rotate 33 bits left once
  1150. D1 /3 RCR r/m32,1 Rotate 33 bits right once
  1151. D1 /4 SAL r/m32,1 Shift Arithmetic Left
  1152. D1 /4 SHL r/m32,1 Shift Logical Left
  1153. D1 /5 SHR r/m32,1 Shift Logical Right
  1154. D1 /7 SAR r/m32,1 Shift Arithmetic Right
  1155. D2 /0 ROL r/m8,CL Rotate 8 bits r/m8 left CL times
  1156. D2 /1 ROR r/m8,CL Rotate 8 bits r/m8 right CL times
  1157. D2 /2 RCL r/m8,CL Rotate 9 bits left CL times
  1158. D2 /3 RCR r/m8,CL Rotate 9 bits right CL times
  1159. D2 /4 SAL r/m8,CL Shift Arithmetic Left
  1160. D2 /4 SHL r/m8,CL Shift Logical Left
  1161. D2 /5 SHR r/m8,CL Shift Logical Right
  1162. D2 /7 SAR r/m8,CL Shift Arithmetic Right
  1163. D3 /0 ROL r/m32,CL Rotate 32 bits r/m32 left CL times
  1164. D3 /1 ROR r/m32,CL Rotate 32 bits r/m32 right CL times
  1165. D3 /2 RCL r/m32,CL Rotate 33 bits left CL times
  1166. D3 /3 RCR r/m32,CL Rotate 33 bits right CL times
  1167. D3 /4 SAL r/m32,CL Shift Arithmetic Left
  1168. D3 /4 SHL r/m32,CL Shift Logical Left
  1169. D3 /5 SHR r/m32,CL Shift Logical Right
  1170. D3 /7 SAR r/m32,CL Shift Arithmetic Right
  1171. D4 0A AAM ASCII adjust AX after multiplication
  1172. D5 0A AAD ASCII adjust AX before division
  1173. D6 SETALC Set ALC: undocumented
  1174. D7 XLAT m8 Table Look-up Translation
  1175. D8 /0 FADD m32real Add m32real to ST(0) and s.r. in ST(0)
  1176. D8 /1 FMUL m32real Multiply ST(0) by m32real and s.r.in ST(0)
  1177. D8 /2 FCOM m32real Compare ST(0) with m32real.
  1178. D8 /3 FCOMP m32real Compare ST(0) with m32real,pop r.stack.
  1179. D8 /4 FSUB m32real Sub m32real from ST(0) and s.r.in ST(0)
  1180. D8 /5 FSUBR m32real Sub ST(0) from m32real and s.r.in ST(0)
  1181. D8 /6 FDIV m32real Divide ST(0) by m32real and s.r.in ST(0)
  1182. D8 /7 FDIVR m32real Divide m32real by ST(0) and s.r.in ST(0)
  1183. D8 C0+i FADD ST(0),ST(i) Add ST(0) to ST(i) and s.r.in ST(0)
  1184. D8 C8+i FMUL ST(0),ST(i) Multiply ST(0) by ST(i) and s.r.in ST(0)
  1185. D8 D0+i FCOM ST(i) Compare ST(0) with ST(i).
  1186. D8 D1 FCOM Compare ST(0) with ST(1).
  1187. D8 D8+i FCOMP ST(i) Compare ST(0) with ST(i), pop
  1188. D8 D9 FCOMP Compare ST(0) with ST(1), pop
  1189. D8 E0+i FSUB ST(0),ST(i) Sub ST(i) from ST(0) and s.r.in ST(0)
  1190. D8 E8+i FSUBR ST(0),ST(i) Sub ST(0) from ST(i) and s.r.in ST(0)
  1191. D8 F0+i FDIV ST(0),ST(i) Divide ST(0) by ST(i) and s.r.in ST(0)
  1192. D8 F8+i FDIVR ST(0),ST(i) Divide ST(i) by ST(0) and s.r.in ST(0)
  1193. D9 /0 FLD m32real Push m32real
  1194. D9 /2 FST m32real Copy ST(0) to m32real
  1195. D9 /3 FSTP m32real Copy ST(0) to m32real and pop
  1196. D9 /4 FLDENV m14/28byte Load FPU environment from m14/m28
  1197. D9 /5 FLDCW m2byte Load FPU control word from m2byte
  1198. D9 /6 FNSTENV m14/28byte Store FPU env without
  1199. D9 /7 FNSTCW m2byte Store FPU control word without
  1200. D9 C0+i FLD ST(i) Push ST(i)
  1201. D9 C8+i FXCH ST(i) Exchange ST(0) and ST(i)
  1202. D9 C9 FXCH Exchange ST(0) and ST(1)
  1203. D9 D0 FNOP No operation is performed
  1204. D9 E0 FCHS Complements sign of ST(0)
  1205. D9 E1 FABS Replace ST(0) with its absolute value
  1206. D9 E4 FTST Compare ST(0) with 0.0
  1207. D9 E5 FXAM Classify value or number in ST(0)
  1208. D9 E8 FLD1 Push +1.0
  1209. D9 E9 FLDL2T Push log2 10
  1210. D9 EA FLDL2E Push log2 e
  1211. D9 EB FLDPI Push pi
  1212. D9 EC FLDLG2 Push log10 2
  1213. D9 ED FLDLN2 Push loge 2
  1214. D9 EE FLDZ Push +0.0
  1215. D9 F0 F2XM1 Replace ST(0) with 2**ST(0) - 1
  1216. D9 F1 FYL2X Replace ST(1) with ST(1)*log2ST(0) and pop
  1217. D9 F2 FPTAN Replaces ST(0) with its tangent push 1.0
  1218. D9 F3 FPATAN Repalces ST(1) with arctan(ST(1)/ST(0)) pop
  1219. D9 F4 FXTRACT Seperate value in ST(0) exp. and sig.
  1220. D9 F5 FPREM1 Replaces ST(0) with IEEE rem(ST(0)/ST(1))
  1221. D9 F6 FDECSTP Decrement TOP field in FPU status word.
  1222. D9 F7 FINCSTP Increment the TOP field FPU status r.
  1223. D9 F8 FPREM Replaces ST(0) with rem (ST(0)/ST(1))
  1224. D9 F9 FYL2XP1 Replace ST(1) with ST(1)*log2(ST(0)+1) pop
  1225. D9 FA FSQRT square root of ST(0)
  1226. D9 FB FSINCOS Compute sine and consine of ST(0) s push c
  1227. D9 FC FRNDINT Round ST(0) to an integer
  1228. D9 FD FSCALE Scale ST(0) by ST(1)
  1229. D9 FE FSIN Replace ST(0) with its sine
  1230. D9 FF FCOS Replace ST(0) with its cosine
  1231. DA /0 FIADD m32int Add m32int to ST(0) and s.r.in ST(0)
  1232. DA /1 FIMUL m32int Multiply ST(0) by m32int and s.r.in ST(0)
  1233. DA /2 FICOM m32int Compare ST(0) with m32int
  1234. DA /3 FICOMP m32int Compare ST(0) with m32int and pop
  1235. DA /4 FISUB m32int Sub m32int from ST(0) and s.r.in ST(0)
  1236. DA /5 FISUBR m32int Sub ST(0) from m32int and s.r.in ST(0)
  1237. DA /6 FIDIV m32int Divide ST(0) by m32int and s.r.in ST(0)
  1238. DA /7 FIDIVR m32int Divide m32int by ST(0) and s.r.in ST(0)
  1239. DA C0+i FCMOVB ST(0),ST(i) Move if below
  1240. DA C8+i FCMOVE ST(0),ST(i) Move if equal
  1241. DA D0+i FCMOVBE ST(0),ST(i) Move if below or equal
  1242. DA D8+i FCMOVU ST(0),ST(i) Move if unordered
  1243. DA E9 FUCOMPP Compare ST(0) with ST(1) and pop pop
  1244. DB /0 FILD m32int Push m32int
  1245. DB /2 FIST m32int Store ST(0) in m32int
  1246. DB /3 FISTP m32int Store ST(0) in m32int and pop
  1247. DB /5 FLD m80real Push m80real
  1248. DB /7 FSTP m80real Copy ST(0) to m80real and pop
  1249. DB C0+i FCMOVNB ST(0),ST(i) Move if not below
  1250. DB C8+i FCMOVNE ST(0),ST(i) Move if not equal
  1251. DB D0+i FCMOVNBE ST(0),ST(i) Move if not below or equal
  1252. DB D8+i FCMOVNU ST(0),ST(i) Move if not unordered
  1253. DB E2 FNCLEX Clear f.e.f. without checking for ..
  1254. DB E3 FNINIT Initialize FPU without ...
  1255. DB E8+i FUCOMI ST,ST(i) Compare ST(0) with ST(i), check o.v.set s.f.
  1256. DB F0+i FCOMI ST,ST(i) Compare ST(0) with ST(i), set status flags
  1257. DC /0 FADD m64real Add m64real to ST(0) and s.r.in ST(0)
  1258. DC /1 FMUL m64real Multiply ST(0) by m64real and s.r.in ST(0)
  1259. DC /2 FCOM m64real Compare ST(0) with m64real.
  1260. DC /3 FCOMP m64real Compare ST(0) with m64real,pop r.stack.
  1261. DC /4 FSUB m64real Sub m64real from ST(0) and s.r.in ST(0)
  1262. DC /5 FSUBR m64real Sub ST(0) from m64real and s.r.in ST(0)
  1263. DC /6 FDIV m64real Divide ST(0) by m64real and s.r.in ST(0)
  1264. DC /7 FDIVR m64real Divide m64real by ST(0) and s.r.in ST(0)
  1265. DC C0+i FADD ST(i),ST(0) Add ST(i) to ST(0) and s.r. in ST(i)
  1266. DC C8+i FMUL ST(i),ST(0) Multiply ST(i) by ST(0) and s.r.in ST(i)
  1267. DC E0+i FSUBR ST(i),ST(0) Sub ST(i) from ST(0) and s.r.in ST(i)
  1268. DC E8+i FSUB ST(i),ST(0) Sub ST(0) from ST(i) and s.r.in ST(i)
  1269. DC F0+i FDIVR ST(i),ST(0) Divide ST(0) by ST(i) and s.r.in ST(i)
  1270. DC F8+i FDIV ST(i),ST(0) Divide ST(i) by ST(0) and s.r.in ST(i)
  1271. DD /0 FLD m64real Push m64real
  1272. DD /2 FST m64real Copy ST(0) to m64real
  1273. DD /3 FSTP m64real Copy ST(0) to m64real and pop
  1274. DD /4 FRSTOR m94/108byte Load FPU status from m94 or m108 byte
  1275. DD /6 FNSAVE m94/108byte Store FPU environment to m94 or m108
  1276. DD /7 FNSTSW m2byte Store FPU status word at m2byte without
  1277. DD C0+i FFREE ST(i) Sets tag for ST(i) to empty
  1278. DD D0+i FST ST(i) Copy ST(0) to ST(i)
  1279. DD D8+i FSTP ST(i) Copy ST(0) to ST(i) and pop
  1280. DD E0+i FUCOM ST(i) Compare ST(0) with ST(i)
  1281. DD E1 FUCOM Compare ST(0) with ST(1)
  1282. DD E8+i FUCOMP ST(i) Compare ST(0) with ST(i) and pop
  1283. DD E9 FUCOMP Compare ST(0) with ST(1) and pop
  1284. DE /0 FIADD m16int Add m16int to ST(0) and s.r.in ST(0)
  1285. DE /1 FIMUL m16int Multiply ST(0) by m16int and s.r.in ST(0)
  1286. DE /2 FICOM m16int Compare ST(0) with m16int
  1287. DE /3 FICOMP m16int Compare ST(0) with m16int and pop
  1288. DE /4 FISUB m16int Sub m16int from ST(0) and s.r.in ST(0)
  1289. DE /5 FISUBR m16int Sub ST(0) from m16int and s.r.in ST(0)
  1290. DE /6 FIDIV m16int Divide ST(0) by m64int and s.r.in ST(0)
  1291. DE /7 FIDIVR m16int Divide m64int by ST(0) and s.r.in ST(0)
  1292. DE C0+i FADDP ST(i),ST(0) Add ST(0) to ST(i), s.r.in ST(i),pop r.stack
  1293. DE C1 FADDP Add ST(0) to ST(1), s.r.in ST(1),pop r.stack
  1294. DE C8+i FMULP ST(i),ST(0) Multiply ST(i) by ST(0), s.r.in ST(i) pop
  1295. DE C9 FMULP Multiply ST(1) by ST(0), s.r.in ST(1) pop
  1296. DE D9 FCOMPP Compare ST(0) with ST(1), pop pop
  1297. DE E0+i FSUBRP ST(i),ST(0) Sub ST(i) from ST(0), s.r. in ST(i) pop
  1298. DE E1 FSUBRP Sub ST(1) from ST(0), s.r.in ST(1) pop
  1299. DE E8+i FSUBP ST(i),ST(0) Sub ST(0) from ST(i), s.r.in ST(i) pop
  1300. DE E9 FSUBP Sub ST(0) from ST(1), s.r.in ST(1) pop
  1301. DE F0+i FDIVRP ST(i),ST(0) Divide ST(0) by ST(i), s.r.in ST(i) pop
  1302. DE F1 FDIVRP Divide ST(0) by ST(1), s.r.in ST(1) pop
  1303. DE F8+i FDIVP ST(i),ST(0) Divide ST(i) by ST(0), s.r.in ST(i) pop
  1304. DE F9 FDIVP Divide ST(1) by ST(0), s.r.in ST(1) pop
  1305. DF /0 FILD m16int Push m16int
  1306. DF /2 FIST m16int Store ST(0) in m16int
  1307. DF /3 FISTP m16int Store ST(0) in m16int and pop
  1308. DF /4 FBLD m80bcd Convert m80BCD to real and push
  1309. DF /5 FILD m64int Push m64int
  1310. DF /6 FBSTP m80bcd Store ST(0) in m80bcd and pop ST(0)
  1311. DF /7 FISTP m64int Store ST(0) in m64int and pop
  1312. DF E0 FNSTSW AX Store FPU status word in AX without
  1313. DF E8+i FUCOMIP ST,ST(i) Compare ST(0) with ST(i), check ovssf pop
  1314. DF F0+i FCOMIP ST,ST(i) Compare ST(0) with ST(i), set s.f. ,pop
  1315. E0 cb LOOPNE rel8 Dec count;jump if count # 0 and ZF=0
  1316. E0 cb LOOPNZ rel8 Dec count;jump if count # 0 and ZF=0
  1317. E1 cb LOOPE rel8 Dec count;jump if count # 0 and ZF=1
  1318. E1 cb LOOPZ rel8 Dec count;jump if count # 0 and ZF=1
  1319. E2 cb LOOP rel8 Dec count;jump if count # 0
  1320. E3 cb JECXZ rel8 Jump short if ECX register is 0
  1321. E4 ib IN AL,imm8 Input byte from imm8 I/O port address into AL
  1322. E5 ib IN EAX,imm8 Input byte from imm8 I/O port address into EAX
  1323. E6 ib OUT imm8,AL Output byte in AL to I/O(imm8)
  1324. E7 ib OUT imm8,EAX Output dword in EAX to I/O(imm8)
  1325. E8 cd CALL rel32 Call near, rel to n.inst
  1326. E9 cd JMP rel32 Jump near, relative,
  1327. EA cp JMP ptr16:32 Jump far, abs.add given in operand
  1328. EB cb JMP rel8 Jump short, relative,
  1329. EC IN AL,DX Input byte from I/O port in DX into AL
  1330. ED IN EAX,DX Input doubleword from I/O port in DX into EAX
  1331. EE OUT DX,AL Output byte in AL to I/O(DX)
  1332. EF OUT DX,EAX Output dword in EAX to I/O(DX)
  1333. F0 LOCK Asserts LOCK signal for duration ..
  1334. F1 INT1 ICEBP
  1335. F2 A6 REPNE CMPS m8,m8 Find matching bytes in m and m
  1336. F2 A7 REPNE CMPS m32,m32 Find matching dwords in m and m
  1337. F2 AE REPNE SCAS m8 Find AL, starting at ES:[(E)DI]
  1338. F2 AF REPNE SCAS m32 Find EAX, starting at ES:[(E)DI]
  1339. F3 6C REP INS m8,DX Input ECX bytes from port DX into ES:[(E)DI]
  1340. F3 6D REP INS m32,DX Input ECX dwords from port DX into ES:[(E)DI]
  1341. F3 6E REP OUTS DX,m8 Output ECX bytes from DS:[(E)SI] to port DX
  1342. F3 6F REP OUTS DX,m32 Output ECX dwords from DS:[(E)SI] to port DX
  1343. F3 A4 REP MOVS m8,m8 Move ECX bytes from DS:[(E)SI] to ES:[(E)DI]
  1344. F3 A5 REP MOVS m32,m32 Move ECX dwords from DS:[(E)SI] to ES:[(E)DI]
  1345. F3 A6 REPE CMPS m8,m8 Find nonmatching bytes in m and m
  1346. F3 A7 REPE CMPS m32,m32 Find nonmatching dwords in m and m
  1347. F3 AA REP STOS m8 Fill ECX bytes at ES:[(E)DI] with AL
  1348. F3 AB REP STOS m32 Fill ECX dwords at ES:[(E)DI] with EAX
  1349. F3 AC REP LODS AL Load ECX bytes from DS:[(E)SI] to AL
  1350. F3 AD REP LODS EAX Load ECX dwords from DS:[(E)SI] to EAX
  1351. F3 AE REPE SCAS m8 Find non-AL byte starting at
  1352. F3 AF REPE SCAS m32 Find non-EAX dword starting at
  1353. F4 HLT Halt
  1354. F5 CMC Complement CF flag
  1355. F6 /2 NOT r/m8 Reverse each bit of r/m8
  1356. F6 /3 NEG r/m8 Two's complement negate r/m8
  1357. F6 /4 MUL r/m8 Unsigned multiply
  1358. F6 /5 IMUL r/m8 Multiply
  1359. F6 /6 DIV r/m8 Unsigned divide AX by r/m8
  1360. F6 /7 IDIV r/m8 Divide
  1361. F6 /0 ib TEST r/m8,imm8 Logical Compare
  1362. F7 /2 NOT r/m32 Reverse each bit of r/m32
  1363. F7 /3 NEG r/m32 Two's complement negate r/m32
  1364. F7 /4 MUL r/m32 Unsigned multiply
  1365. F7 /5 IMUL r/m32 Multiply
  1366. F7 /6 DIV r/m16 Unsigned divide DX:AX by r/m16
  1367. F7 /6 DIV r/m32 Unsigned divide EDX:EAX by r/m32
  1368. F7 /7 IDIV r/m32 Divide
  1369. F7 /0 id TEST r/m32,imm32 Logical Compare
  1370. F8 CLC Clear CF flag
  1371. F9 STC Set Carry Flag
  1372. FA CLI Clear interrupt flag
  1373. FB STI Set Interrup Flag
  1374. FC CLD Clear DF flag
  1375. FD STD Set Direction Flag
  1376. FE /0 INC r/m8 Increment 1
  1377. FE /1 DEC r/m8 Decrement r/m8 by 1
  1378. FF /0 INC r/m32 Increment 1
  1379. FF /1 DEC r/m32 Decrement r/m32 by 1
  1380. FF /2 CALL r/m32 Call near, abs.ind.add. given in r/m32
  1381. FF /3 CALL m16:32 Call far, abs.ind.add. given in m16:32
  1382. FF /4 JMP r/m32 Jump near, abs.ind.in r/m32
  1383. FF /6 PUSH r/m32 Push r/m32
  1384. FF /r JMP m16:32 Jump far, abs.ind.in m16:32
  1385. ===============================================================================
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