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  1. module cordic(
  2.   input [15:0]theta,
  3.   input beg, clk, rst,
  4.   output [15:0]cos,
  5.   output fin
  6.   );
  7.  
  8.   wire ld;
  9.   reg [15:0]atan;
  10.   reg itr;
  11.   wire sel;
  12.   cu cu1(
  13.   .beg(beg),
  14.   .itr(itr),
  15.   .ld(ld),
  16.   .fin(fin),
  17.   .init(sel)
  18.   );
  19.  
  20.   cntr cntr1(
  21.   .c_up(ld),
  22.   .clk(clk),
  23.   .clr(rst),
  24.   .q(itr)
  25.   );
  26.  
  27.   atan_const atan1(
  28.   .itr(itr),
  29.   .atan( atan)
  30.   );
  31.  
  32.   wire [15:0]z_out1;
  33.   wire [15:0]z_out2;
  34.   wire [15:0]z_out3;
  35.   wire [15:0]mux_out_1;
  36.   wire [15:0]mux_out_2;
  37.   wire [15:0]mux_out_3;
  38.   mux mux1(
  39.   .d1(z_out1),
  40.   .d2(16'h26dd),
  41.   .sel(sel),
  42.   .q(mux_out_1)
  43.   );
  44.   mux mux2(
  45.   .d1(z_out2),
  46.   .d2(16'h26dd),
  47.   .sel(sel),
  48.   .q(mux_out_2)
  49.   );
  50.   mux mux3(
  51.   .d1(z_out3),
  52.   .d2(theta),
  53.   .sel(sel),
  54.   .q(mux_out_3)
  55.   );
  56.  
  57.   reg [15:0]reg_out_2;
  58.   reg [15:0]reg_out_3;
  59.   rgst rgst1(
  60.   .d(mux_out_1),
  61.   .clk(clk),
  62.   .ld(ld),
  63.   .rst(rst),
  64.   .q(cos)
  65.   );
  66.   rgst rgst2(
  67.   .d(mux_out_2),
  68.   .clk(clk),
  69.   .ld(ld),
  70.   .rst(rst),
  71.   .q(reg_out_2)
  72.   );
  73.     rgst rgst3(
  74.   .d(mux_out_3),
  75.   .clk(clk),
  76.   .ld(ld),
  77.   .rst(rst),
  78.   .q(reg_out_3)
  79.   );
  80.  
  81.   wire [15:0]shift_out_1;
  82.   wire [15:0]shift_out_2;
  83.   shifter shift1(
  84.   .d(reg_out_1),
  85.   .i(itr),
  86.   .q(shift_out_1)
  87.   );
  88.   shifter shift2(
  89.   .d(reg_out_2),
  90.   .i(itr),
  91.   .q(shift_out_2)
  92.   );
  93.  
  94.   add_sub add1(
  95.   .x(shift_out_2),
  96.   .y(reg_out_1),
  97.   .sub(!reg_out_3[15]),
  98.   .z(z_out1)
  99.   );
  100.     add_sub add2(
  101.   .x(shift_out_1),
  102.   .y(reg_out_2),
  103.   .sub(reg_out_3[15]),
  104.   .z(z_out2)
  105.   );
  106.     add_sub add3(
  107.   .x(atan),
  108.   .y(reg_out_3),
  109.   .sub(!reg_out_3[15]),
  110.   .z(z_out3)
  111.   );
  112. endmodule
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