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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    12:41:42 04/01/2019
  6. -- Design Name:
  7. -- Module Name:    reader - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. --use IEEE.STD_LOGIC_ARITH.ALL;
  23. --use IEEE.STD_LOGIC_UNSIGNED.ALL;
  24. USE ieee.numeric_std.ALL;
  25.  
  26. ---- Uncomment the following library declaration if instantiating
  27. ---- any Xilinx primitives in this code.
  28. --library UNISIM;
  29. --use UNISIM.VComponents.all;
  30.  
  31. entity reader is
  32. port(
  33.     clk_i : in std_logic;
  34.     rst_i : in std_logic;
  35.     RXD_i : in std_logic;
  36.     digit_o : out std_logic_vector(31 downto 0) := (others => '1')
  37. );
  38. end reader;
  39.  
  40. architecture Behavioral of reader is
  41.  
  42. signal counter : integer := 0;
  43. signal can_read : std_logic := '0';
  44. signal reading : std_logic := '0';
  45. signal buffor : std_logic_vector(7 downto 0);
  46. signal index : integer := 0;
  47.  
  48. type Digits is array (0 to 15) of std_logic_vector(6 downto 0);
  49. signal dig : Digits:=  
  50.         (   "0000001",
  51.             "1001111",
  52.             "0010010",
  53.             "0000110",
  54.             "1001100",
  55.             "0100100",
  56.             "0100000",
  57.             "0001111",
  58.             "0000000",
  59.             "0000100",
  60.             "0001000",
  61.             "1100000",
  62.             "0110001",
  63.             "1000010",
  64.             "0110000",
  65.             "0111000"
  66.         );
  67.  
  68. signal N : integer := 5208;
  69.  
  70. begin
  71.  
  72. process(clk_i, rst_i)
  73. begin
  74.     if(rst_i = '1') then
  75.             digit_o <= (others => '1');
  76.     elsif(rising_edge(clk_i)) then
  77.    
  78.         if(counter < N) then
  79.             counter <= counter + 1;
  80.         else
  81.             counter <= 0;
  82.             can_read <= '1';
  83.         end if;
  84.        
  85.         if( can_read = '1') then
  86.             can_read <= '0';
  87.             if(RXD_i = '0' and reading = '0') then
  88.                 reading <= '1';
  89.             elsif(reading = '1' and index < 8) then
  90.                 buffor(index) <= RXD_i;
  91.                 index <= index + 1;
  92.             elsif(reading = '1' and index >= 8) then
  93.                 digit_o(23 downto 17) <= dig(to_integer(unsigned(buffor(7 downto 4))));
  94.                 digit_o(15 downto 9) <= dig(to_integer(unsigned(buffor(3 downto 0))));
  95.                 index <= 0;
  96.                 if(RXD_i = '1') then
  97.                     reading <= '0';    
  98.                 end if;
  99.             end if;
  100.         end if;
  101.     end if;
  102.    
  103. end process;
  104.  
  105. end Behavioral;
  106.  
  107.  
  108.  
  109. ----------------------------------------------------------------------------------
  110. -- Company:
  111. -- Engineer:
  112. --
  113. -- Create Date:    13:08:44 03/11/2019
  114. -- Design Name:
  115. -- Module Name:    led_mod - Behavioral
  116. -- Project Name:
  117. -- Target Devices:
  118. -- Tool versions:
  119. -- Description:
  120. --
  121. -- Dependencies:
  122. --
  123. -- Revision:
  124. -- Revision 0.01 - File Created
  125. -- Additional Comments:
  126. --
  127. ----------------------------------------------------------------------------------
  128. library IEEE;
  129. use IEEE.STD_LOGIC_1164.ALL;
  130. use IEEE.STD_LOGIC_ARITH.ALL;
  131. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  132.  
  133. ---- Uncomment the following library declaration if instantiating
  134. ---- any Xilinx primitives in this code.
  135. --library UNISIM;
  136. --use UNISIM.VComponents.all;
  137.  
  138. entity led_mod is
  139.     port(
  140.         clk_i: in std_logic;
  141.         rst_i: in std_logic;
  142.         digit_i: in std_logic_vector(31 downto 0);
  143.         led7_an_o: out std_logic_vector( 3 downto 0);
  144.         led7_seg_o: out std_logic_vector( 7 downto 0)
  145.         );
  146. end led_mod;
  147.  
  148. architecture Behavioral of led_mod is
  149.  
  150. constant clock: integer:= 50000;
  151. signal counter: integer:= 0;
  152. signal active: integer := 0;
  153.  
  154. begin
  155.  
  156.     with active select
  157.     led7_an_o <= "0111" when 0,
  158.                  "1011" when 1,
  159.                  "1101" when 2,
  160.                  "1110" when 3,
  161.                  "1111" when others;
  162.  
  163.     with active select
  164.     led7_seg_o <= digit_i(31 downto 24) when 0,
  165.                      digit_i(23 downto 16) when 1,
  166.                          digit_i(15 downto 8) when 2,
  167.                          digit_i(7 downto 0) when 3,
  168.                          "11111111" when others;
  169.                          
  170.     process(clk_i,rst_i)    
  171.      begin
  172.           if(rst_i = '1') then
  173.               active<=4;
  174.         elsif rising_edge(clk_i)  then
  175.                 if(counter < clock) then
  176.                     counter <= counter+1;
  177.                 else
  178.                     counter<=0;        
  179.                     if(active = 3 or active = 4) then
  180.                          active<= 0;
  181.                     else
  182.                         active <= active + 1;
  183.                     end if;
  184.                 end if;
  185.         end if;
  186.     end process;
  187.      
  188. end Behavioral;
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