Advertisement
Domy131097

DRS_LV3_moving_light

Nov 24th, 2020
50
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity moving_light is
  5. --TO DO 1 -> deklarirati ulaz "clk" (STD_LOGIC) i izlaz "output" (STD_LOGIC_VECTOR) veličine 8 bita
  6. Port (clk : IN STD_LOGIC;
  7. output: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  8. );
  9. end moving_light;
  10.  
  11. architecture Behavioral of moving_light is
  12.  
  13. --TO DO 2 -> definirati korisnički tip podataka naziva "state" koji može imati vrijednosti "state0", ... "state7"
  14. TYPE state IS(state0, state1, state2, state3, state4, state5, state6, state7);
  15. --TO DO 3 -> deklarirati signale "current_state" i "next_state" koji su tipa "state"
  16. SIGNAL current_state, next_state: state;
  17. --TO DO 4 -> deklarirati signal "clk_div" koji je tipa STD_LOGIC
  18. SIGNAL clk_div: STD_LOGIC;
  19.  
  20.  
  21. begin
  22.  
  23. --TO DO 5 -> instancirati generički djelitelj frekvencije na način da od ulaznog singala takta kreira signal takta frekvencije 1 Hz
  24. L1: entity work.generic_divider generic map(50_000_000) port map (clk, clk_div);
  25.  
  26. ----Lower section of FSM----
  27. process(clk_div)
  28. begin
  29. --TO DO 6 -> na rastući brid signala takta "clk_div" signalu "current_state" pridružiti vrijednost signala "next_state"
  30. if(clk_div'EVENT AND clk_div = '1') then
  31. current_state <= next_state;
  32. end if;
  33. end process;
  34.  
  35. ----Upper section of FSM----
  36. process(current_state)
  37. begin
  38. case current_state is
  39. --TO DO 7 -> u ovisnosti o vrijednosti signala "current_state" signalima "output" i "next_state" pridružiti odgovarajuće vrijednosti
  40. when state0 =>
  41. output <= "00000001";
  42. next_state <= state1;
  43. when state1 =>
  44. output <= "00000010";
  45. next_state <= state2;
  46. when state2 =>
  47. output <= "00000100";
  48. next_state <= state3;
  49. when state3 =>
  50. output <= "00001000";
  51. next_state <= state4;
  52. when state4 =>
  53. output <= "00010000";
  54. next_state <= state5;
  55. when state5 =>
  56. output <= "00100000";
  57. next_state <= state6;
  58. when state6 =>
  59. output <= "01000000";
  60. next_state <= state7;
  61. when state7 =>
  62. output <= "10000000";
  63. next_state <= state0;
  64. end case;
  65. end process;
  66.  
  67. end Behavioral;
  68.  
Advertisement
RAW Paste Data Copied
Advertisement