--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   11:20:09 03/21/2019
-- Design Name:
-- Module Name:   C:/Designs/OlcenLaszczuk/Projekt7/test.vhd
-- Project Name:  Projekt7
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: projekt7
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test IS
END test;

ARCHITECTURE behavior OF test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT projekt7
    PORT(
         start_stop_button_i : IN  std_logic;
         clk_i : IN  std_logic;
         rst_i : IN  std_logic;
         led7_an_o : OUT  std_logic_vector(3 downto 0);
         led7_seg_o : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal start_stop_button_i : std_logic := '0';
   signal clk_i : std_logic := '0';
   signal rst_i : std_logic := '0';

 	--Outputs
   signal led7_an_o : std_logic_vector(3 downto 0);
   signal led7_seg_o : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_i_period : time := 20ns;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
   uut: projekt7 PORT MAP (
          start_stop_button_i => start_stop_button_i,
          clk_i => clk_i,
          rst_i => rst_i,
          led7_an_o => led7_an_o,
          led7_seg_o => led7_seg_o
        );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
		wait for 10ns;
		start_stop_button_i <= '1';
		wait for 50ns;
		start_stop_button_i <= '0';
		wait for 450ns;
		start_stop_button_i <= '1';
		wait for 50ns;
		start_stop_button_i <= '0';
		wait;
   end process;

END;