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- module REGS(bufferIn,IR,MAR,MDR,MAR_in,MDR_in,MDR_out,IR_in,reg0_in,reg1_in,reg2_in,reg3_in,reg0_out,reg1_out,reg2_out,reg3_out,out);
- input wire [15:0] bufferIn;
- output reg [15:0] out;
- // Input buffer and output for buffer
- // Declare
- reg [15:0] reg0 = 0;
- reg [15:0] reg1 = 0;
- reg [15:0] reg2 = 0;
- reg [15:0] reg3 = 0;
- registers
- output reg [15:0] MAR = 0;
- output reg [15:0] MDR = 0;
- output reg [15:0] IR = 0;
- // Registers for MDR and MAR
- input wire MAR_in,MDR_in,MDR_out,IR_in,reg0_in,reg1_in,reg2_in,reg3_in,reg0_out,reg1_out,reg2_out,reg3_out;
- // input control wires
- /* IR */
- always @(posedge IR_in)
- IR = bufferIn;
- // buffer for setting input
- /* MAR */
- always @(posedge MAR_in)
- MAR = bufferIn;
- // buffer for setting input
- /* MDR */
- always @(posedge MDR_in)
- MDR = bufferIn;
- // buffer for setting input
- always @(MDR_out)
- assign out = MDR_out?MDR:16'bz;
- // Tri-State buffer for sending output when output is enabled or else 16'bz
- /* REGISTERS */
- //reg0
- always @(posedge reg0_in)
- reg0 = bufferIn;
- always @(reg0_out)
- assign out = reg0_out?reg0:16'bz;
- //reg1
- always @(posedge reg1_in)
- reg1 = bufferIn;
- always @(reg1_out)
- assign out = reg1_out?reg1:16'bz;
- //reg2
- always @(posedge reg2_in)
- reg2 = bufferIn;
- always @(reg2_out)
- assign out = reg2_out?reg2:16'bz;
- //reg3
- always @(posedge reg3_in)
- reg3 = bufferIn;
- always @(reg3_out)
- assign out = reg3_out?reg3:16'bz;
- endmodule
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