module Medidor_Function (clock, reset_n, enable, control, data_out);

input clock, reset_n, control, enable;
output reg [31:0] data_out;
reg flag;
reg [1:0] ctl;
always @(negedge clock)
begin
    if(!reset_n)
    begin
        data_out <= 0;
        flag <= 0;
    end
    else if (enable)
    begin
        flag <= 1;
        ctl <= control;
    end
    if (flag)
    begin
        if (ctl == 0)
            //data_out <= data_out + 1;
            data_out <= 50;
        if (ctl == 1)
        begin
            flag <= 0;
            data_out <= 51;
        end
        if (ctl == 2)
        begin
            data_out <= 52; //0;
            flag <= 0;
        end
    end

end
endmodule