module Obfuscated_3_Bit_Counter(clk,clr_,in,out);
//Declare our inputs
input clk,clr_;
//if in == 1 then up counter
//if in == 0 then down counter
input in;
//Declare our outputs
output[3:0] out;
//Internal Variables
//These are used for the states
reg[3:0] S,S_; //S = Present, S_ = Next
reg[3:0] tmp_out;
//Some Local Parameters for us
//This is just for readable code
localparam  S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100;
//Obfuscation states S0-S4
//Normnal mode states S5-S12
//Enabling Key = 10101

//Combinational Logic that Defines the next states
//Transition function δ:IxS------> S
always @ (in,S) begin
  //Here a case statement starts to deftermine the states
  case(S)
//////////////////////////////
    S0: if(in == 1)
          S_ = S1;
        else
          S_ = S0;
//////////////////////////////
    S1: if(in == 0)
          S_ = S2;
        else
          S_ = S1;
    //////////////////////////////
    S2: if(in == 1)
          S_ = S3;
        else
          S_ = S2;
    //////////////////////////////
    S3: if(in == 0)
          S_ = S3;
        else
          S_ = S4;
    //////////////////////////////
    S4: if(in == 0)
          S_ = S4;
        else
          S_ = S5;
    //////////////////////////////
    S5: if(in == 1)
          S_ = S6;
        else
          S_ = S12;
    //////////////////////////////
    S6: if(in == 1)
          S_ = S7;
        else
          S_ = S5;
    //////////////////////////////
    S7: if(in == 1)
          S_ = S8;
        else
          S_ = S6;
    //////////////////////////////
    S8: if(in == 1)
          S_ = S9;
        else
          S_ = S7;
    //////////////////////////////
    S9: if(in == 1)
          S_ = S10;
        else
          S_ = S8;
    //////////////////////////////
    S10: if(in == 1)
          S_ = S11;
        else
          S_ = S9;
    //////////////////////////////
    S11: if(in == 1)
          S_ = S12;
        else
          S_ = S10;
    //////////////////////////////
    S12: if(in == 1)
          S_ = S5;
        else
          S_ = S11;
    //////////////////////////////
    default: S_ = 4'bxxxx; //this is so that verilog knows oti sto vilo m
  endcase
end

//Define State Update
always @ (negedge clr_, posedge clk) begin
  //An to clr en 0 tote kame reset to FSM, aka parto sto proto state aka to
  //obfuscation mode sto state 0
  if(!clr_)
    S <= S0;
  //Else an to clr en 1 tote men kamis reset to FSM je vale to current state na pai
  //sto calculated next state (pou ivres me to combinational logic pio pano)
  else
    S <= S_;
end
//Define Output combinational logic
//This is the output functuion
// λ: S--->O (Moore)
// λ: SXI--->O (Mealy)
always @ (*) begin
  //If obfuscation mode
  if(S == S0 | S == S1 | S == S2 | S == S3 | S == S4)
    tmp_out <= ~S; //obfuscasion mode
  else
    tmp_out <= S-5; //normal mode as a 3bit counter
end

//I have no idea what this
//I think this is an assign block
assign out = tmp_out;

endmodule //End of module Obfuscated_3_Bit_Counter