module lab3_wa(input logic clk,
                    input logic reset,
                    input logic left, right,
                    output logic la, lb, lc, ra, rb, rc);
    // Define states
    typedef enum logic[2:0] {S0, S1, S2, S3, S4, S5, S6, S7} statetype;
    statetype[2:0] state, nextstate;

    // Update register
    always_ff@(posedge clk, posedge reset)
        if(reset) state <= S0;
        else         state <= nextstate;

    // Determine the next state
    always_comb
        case(state)
            S0:     if(left & right)            nextstate = S7;
                    else if(~left & right)  nextstate = S1;
                    else if(left & ~right)  nextstate = S4;
                    else                            nextstate = S0;
            S1: nextstate = S2;
            S2: nextstate = S3;
            S3: if(left & right)            nextstate = S7;
                    else if(~left & right)  nextstate = S1;
                    else if(left & ~right)  nextstate = S4;
                    else                            nextstate = S0;
            S4: nextstate = S5;
            S5: nextstate = S6;
            S6: if(left & right)            nextstate = S7;
                    else if(~left & right)  nextstate = S1;
                    else if(left & ~right)  nextstate = S4;
                    else                            nextstate = S0;
            S7: if(left & right)            nextstate = S7;
                    else if(~left & right)  nextstate = S1;
                    else if(left & ~right)  nextstate = S4;
                    else                            nextstate = S0;
            default: nextstate <= S0;
        endcase

    // Determine output
    case(state)
            S0:
                assign la = 0;
                assign lb = 0;
                assign lc = 0;
                assign ra = 0;
                assign rb = 0;
                assign rc = 0;
            S1:
                assign la = 1;
                assign lb = 0;
                assign lc = 0;
                assign ra = 0;
                assign rb = 0;
                assign rc = 0;
            S2:
                assign la = 1;
                assign lb = 1;
                assign lc = 0;
                assign ra = 0;
                assign rb = 0;
                assign rc = 0;
            S3:
                assign la = 1;
                assign lb = 1;
                assign lc = 1;
                assign ra = 0;
                assign rb = 0;
                assign rc = 0;
            S4:
                assign la = 0;
                assign lb = 0;
                assign lc = 0;
                assign ra = 1;
                assign rb = 0;
                assign rc = 0;
            S5:
                assign la = 0;
                assign lb = 0;
                assign lc = 0;
                assign ra = 1;
                assign rb = 1;
                assign rc = 0;
            S6:
                assign la = 0;
                assign lb = 0;
                assign lc = 0;
                assign ra = 1;
                assign rb = 1;
                assign rc = 1;
            S7:
                assign la = 0;
                assign lb = 0;
                assign lc = 0;
                assign ra = 0;
                assign rb = 0;
                assign rc = 0;