counter_test

`timescale 1ns/1ps

module counter_test;

logic clk,rst;
logic [2:0] periods;
logic [2:0] result;

initial begin
    clk=0;
    forever #10 clk = ~clk;
end

initial
begin
    rst=0;
        periods=3;

    @(negedge clk) rst=1;
    #1000;
        @(negedge clk) rst=0;
    @(negedge clk) rst=1;
    #300;
    $stop;
end

bin_cnt uut_inst(
    .clk(clk), .resetn(rst),
    .periods(periods),
    .cnt(result)
);

endmodule