LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;			--	needed for 'unsigned'

ENTITY hex7seg IS
	PORT (
				hex		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
				display	: OUT	STD_LOGIC_VECTOR(0 TO 6));
END hex7seg;

ARCHITECTURE Behavior OF hex7seg IS
BEGIN
	--
	--       0
	--      ---
	--     |   |
	--    5|   |1
	--     | 6 |
	--      ---
	--     |   |
	--    4|   |2
	--     |   |
	--      ---
	--       3
	--
	PROCESS ( hex)
	BEGIN
		CASE hex IS
			WHEN "0000" => display <= "0000001";
			WHEN "0001" => display <= "1001111";
			WHEN "0010" => display <= "0010010";
			WHEN "0011" => display <= "0000110";
			WHEN "0100" => display <= "1001100";
			WHEN "0101" => display <= "0100100";
			WHEN "0110" => display <= "0100000";
			WHEN "0111" => display <= "0001111";
			WHEN "1000" => display <= "0000000";
			WHEN "1001" => display <= "0000100";
			WHEN "1010" => display <= "0001000";
			WHEN "1011" => display <= "1100000";
			WHEN "1100" => display <= "0110001";
			WHEN "1101" => display <= "1000010";
			WHEN "1110" => display <= "0110000";
			WHEN "1111" => display <= "0111000";
			WHEN OTHERS => display <= "1111111";		--	empty
		END CASE;
	END PROCESS;
END Behavior;

----------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;			--	needed for 'unsigned'

entity DemoSSD is
port (	CLOCK_50: in std_logic;
			SW: in std_logic_vector (17 downto 0);
			LEDR: out std_logic_vector (17 downto 0);
			KEY: in std_logic_vector (3 downto 0);
			LEDG: out std_logic_vector (3 downto 0);
			HEX3, HEX2, HEX1, HEX0: out std_logic_vector (0 to 6)	-- 0 to 6  !!
		);
end entity DemoSSD;

architecture DemoSSD1 of DemoSSD is

component hex7seg IS
	PORT (
				hex		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
				display	: OUT	STD_LOGIC_VECTOR(0 TO 6)
			);
end component hex7seg;

signal num3, num2, num1 : std_logic_vector(3 downto 0);

begin
		LEDR <= SW;
		LEDG <= not KEY;

		num3 <= "0011";				-- waarde 3
		num2 <= "0010";				-- waarde 2
		num1 <= "0001";				-- waarde 1

		h3: hex7seg port map(num3, HEX3);
		h2: hex7seg port map(num2, HEX2);
		h1: hex7seg port map(num1, HEX1);
		h0: hex7seg port map(SW(3 downto 0), HEX0);

end DemoSSD1;