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passthrough_sdhc_s32g274aevb.dts

Feb 10th, 2020
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <2>;
  5. #size-cells = <1>;
  6.  
  7. gic: gic {
  8. #interrupt-cells = <3>;
  9. interrupt-controller;
  10. };
  11.  
  12. passthrough {
  13. compatible = "simple-bus";
  14. ranges;
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. /* S32GEN1_CLK_XBAR_DIV3 */
  18. misc_clk: misc_clk {
  19. #clock-cells = <0>;
  20. clock-frequency = <0x7F28155>;
  21. compatible = "fixed-clock";
  22. };
  23. /* S32GEN1_CLK_XBAR */
  24. misc_clk1: misc_clk1 {
  25. #clock-cells = <0>;
  26. clock-frequency = <0x17D78400>;
  27. compatible = "fixed-clock";
  28. };
  29. /* S32GEN1_CLK_SDHC */
  30. misc_clk2: misc_clk2 {
  31. #clock-cells = <0>;
  32. clock-frequency = <0xBEBC200>;
  33. compatible = "fixed-clock";
  34. };
  35.  
  36. usdhc@402F0000 {
  37. xen,force-assign-without-iommu;
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. compatible = "fsl,s32gen1-usdhc";
  41. status = "okay";
  42. reg = <0x0 0x402f0000 0x1000>;
  43. interrupt-parent = <&gic>;
  44. interrupts = <0 36 4>;
  45. clocks = <&misc_clk &misc_clk1 &misc_clk2>;
  46. clock-names = "ipg", "ahb", "per";
  47. bus-width = <8>;
  48. xen,reg = <0x0 0x4002f000 0x1000 0x0 0x4002f000>;
  49. };
  50. };
  51. };
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