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- /dts-v1/;
- / {
- #address-cells = <2>;
- #size-cells = <1>;
- gic: gic {
- #interrupt-cells = <3>;
- interrupt-controller;
- };
- passthrough {
- compatible = "simple-bus";
- ranges;
- #address-cells = <2>;
- #size-cells = <1>;
- /* S32GEN1_CLK_XBAR_DIV3 */
- misc_clk: misc_clk {
- #clock-cells = <0>;
- clock-frequency = <0x7F28155>;
- compatible = "fixed-clock";
- };
- /* S32GEN1_CLK_XBAR */
- misc_clk1: misc_clk1 {
- #clock-cells = <0>;
- clock-frequency = <0x17D78400>;
- compatible = "fixed-clock";
- };
- /* S32GEN1_CLK_SDHC */
- misc_clk2: misc_clk2 {
- #clock-cells = <0>;
- clock-frequency = <0xBEBC200>;
- compatible = "fixed-clock";
- };
- usdhc@402F0000 {
- xen,force-assign-without-iommu;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,s32gen1-usdhc";
- status = "okay";
- reg = <0x0 0x402f0000 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <0 36 4>;
- clocks = <&misc_clk &misc_clk1 &misc_clk2>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <8>;
- xen,reg = <0x0 0x4002f000 0x1000 0x0 0x4002f000>;
- };
- };
- };
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