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- module Round_Robin_FIFO_Arbiter(clk, rst_n, wen, a, b, c, d, dout, valid);
- input clk;
- input rst_n;
- input [3:0] wen;
- input [7:0] a, b, c, d;
- output [7:0] dout;
- output reg valid;
- reg [1:0] fifo_read;
- wire [3:0] error;
- wire [7:0] out [3:0];
- reg [3:0] ren;
- always @ (posedge clk) begin
- if(rst_n == 1'b0) fifo_read <= 2'b00;
- else fifo_read <= fifo_read + 1'b1;
- end
- always @ (error or fifo_read) begin
- if(wen[fifo_read - 1'b1] == 1'b1) valid = 1'b0;
- else if(error[fifo_read - 1'b1] == 1'b1) valid = 1'b0;
- else valid = 1'b1;
- end
- always @ (fifo_read or wen) begin
- if(wen[fifo_read] == 1'b1) ren = 4'b0000;
- else begin
- case(fifo_read)
- 2'b00: ren = 4'b0001;
- 2'b01: ren = 4'b0010;
- 2'b10: ren = 4'b0100;
- 2'b11: ren = 4'b1000;
- endcase
- end
- end
- assign dout = valid ? out[fifo_read - 1'b1] : 8'd0;
- FIFO_8 fa(clk, rst_n, wen[0], ren[0], a, out[0], error[0]);
- FIFO_8 fb(clk, rst_n, wen[1], ren[1], b, out[1], error[1]);
- FIFO_8 fc(clk, rst_n, wen[2], ren[2], c, out[2], error[2]);
- FIFO_8 fd(clk, rst_n, wen[3], ren[3], d, out[3], error[3]);
- endmodule
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