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- BL2 Built : 19:22:01, Jul 31 2019. g12b ge9a9000 - zhiguang.ouyang@droid07-sz
- Board ID = 8
- Set A53 clk to 24M
- Set A73 clk to 24M
- Set clk81 to 24M
- A53 clk: 1200 MHz
- A73 clk: 1200 MHz
- CLK81: 166.6M
- smccc: 0003125e
- eMMC boot @ 0
- sw8 s
- DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Jul 31 2019 19:21:56
- board id: 8
- Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
- Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
- PIEI prepare done
- fastboot data load
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- verify result: 265
- Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
- LPDDR4 probe
- ddr clk to 1608MHz
- Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
- dmc_version 0001
- Check phy result
- INFO : End of CA training
- INFO : End of initialization
- INFO : Training has run successfully!
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of Write leveling coarse delay
- INFO : Training has run successfully!
- Check phy result
- INFO : End of initialization
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- 1D training succeed
- Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
- Check phy result
- INFO : End of initialization
- INFO : End of 2D read delay Voltage center optimization
- INFO : End of 2D read delay Voltage center optimization
- INFO : End of 2D write delay Voltage center optimization
- INFO : End of 2D write delay Voltage center optimization
- INFO : Training has run successfully!
- channel==0
- RxClkDly_Margin_A0==97 ps 10
- TxDqDly_Margin_A0==106 ps 11
- RxClkDly_Margin_A1==97 ps 10
- TxDqDly_Margin_A1==106 ps 11
- TrainedVREFDQ_A0==26
- TrainedVREFDQ_A1==26
- VrefDac_Margin_A0==26
- DeviceVref_Margin_A0==26
- VrefDac_Margin_A1==27
- DeviceVref_Margin_A1==26
- channel==1
- RxClkDly_Margin_A0==97 ps 10
- TxDqDly_Margin_A0==106 ps 11
- RxClkDly_Margin_A1==106 ps 11
- TxDqDly_Margin_A1==106 ps 11
- TrainedVREFDQ_A0==25
- TrainedVREFDQ_A1==26
- VrefDac_Margin_A0==27
- DeviceVref_Margin_A0==25
- VrefDac_Margin_A1==26
- DeviceVref_Margin_A1==25
- dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
- soc_vref_reg_value 0x 00000027 00000025 00000027 00000025 00000025 00000025 00000026 00000024 00000025 00000025 00000024 00000024 00000025 00000026 00000024 00000025 00000025 00000028 00000026 00000027 00000026 00000026 00000026 00000025 00000027 00000026 00000026 00000026 00000028 00000026 00000027 00000026 dram_vref_reg_value 0x 00000013
- 2D training succeed
- aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Jul 31 2019 19:22:05
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 2048MB
- DMC_DDR_CTRL: 00e00024DDR size: 3928MB
- cs0 DataBus test pass
- cs1 DataBus test pass
- cs0 AddrBus test pass
- cs1 AddrBus test pass
- 100bdlr_step_size ps== 444
- result report
- boot times 0Enable ddr reg access
- 00000000
- emmc switch 3 ok
- Authentication key not yet programmed
- get rpmb counter error 0x00000007
- 00000000
- emmc switch 0 ok
- Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x000d6600, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- MVN_1=0x00000000
- MVN_2=0x00000000
- [Image: g12b_v1.1.3386-3b31431 2019-05-21 10:42:10 luan.yuan@droid15-sz]
- OPS=0x10
- ring efuse init
- chipver efuse init
- 29 0b 10 00 01 05 1c 00 00 04 37 30 4e 42 4e 50
- [0.018961 Inits done]
- secure task start!
- high task start!
- low task start!
- run into bl31
- NOTICE: BL31: v1.3(release):4fc40b1
- NOTICE: BL31: Built : 15:58:17, May 22 2019
- NOTICE: BL31: G12A normal boot!
- NOTICE: BL31: BL33 decompress pass
- ERROR: Error initializing runtime service opteed_fast
- U-Boot 2015.01-g5a7732a-dirty (Aug 09 2019 - 14:42:00)
- DRAM: 3.8 GiB
- Relocation Offset is: d6e2f000
- spi_post_bind(spifc): req_seq = 0
- register usb cfg[0][1] = 00000000d7f2f2d0
- aml_i2c_init_port init regs for 0
- NAND: get_sys_clk_rate_mtd() 270, clock setting 200!
- NAND device id: 0 9f ff ff ff ff
- No NAND device found!!!
- nand init failed: -6
- get_sys_clk_rate_mtd() 270, clock setting 200!
- NAND device id: 0 9f ff ff ff ff
- No NAND device found!!!
- nand init failed: -6
- MMC: aml_priv->desc_buf = 0x00000000d3e1fa70
- aml_priv->desc_buf = 0x00000000d3e21db0
- SDIO Port B: 0, SDIO Port C: 1
- co-phase 0x3, tx-dly 0, clock 400000
- co-phase 0x3, tx-dly 0, clock 400000
- co-phase 0x3, tx-dly 0, clock 400000
- emmc/sd response timeout, cmd8, status=0x3ff2800
- emmc/sd response timeout, cmd55, status=0x3ff2800
- co-phase 0x3, tx-dly 0, clock 400000
- co-phase 0x1, tx-dly 0, clock 40000000
- aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x2000
- [mmc_startup] mmc refix success
- init_part() 297: PART_TYPE_AML
- [mmc_init] mmc init success
- start dts,buffer=00000000d3e24620,dt_addr=00000000d3e24620
- get_partition_from_dts() 71: ret 0
- parts: 17
- 00: logo 0000000000800000 1
- 01: recovery 0000000001800000 1
- 02: misc 0000000000800000 1
- 03: dtbo 0000000000800000 1
- 04: cri_data 0000000000800000 2
- 05: param 0000000001000000 2
- 06: boot 0000000001000000 1
- set has_boot_slot = 0
- 07: rsv 0000000001000000 1
- 08: metadata 0000000001000000 1
- 09: vbmeta 0000000000200000 1
- 10: tee 0000000002000000 1
- 11: vendor 0000000010000000 1
- 12: odm 0000000008000000 1
- 13: system 0000000050000000 1
- 14: product 0000000008000000 1
- 15: cache 0000000046000000 2
- 16: data ffffffffffffffff 4
- init_part() 297: PART_TYPE_AML
- eMMC/TSD partition table have been checked OK!
- crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
- crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
- crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
- mmc env offset: 0x4d400000
- In: serial
- Out: serial
- Err: serial
- reboot_mode=cold_boot
- [store]To run cmd[emmc dtb_read 0x1000000 0x40000]
- _verify_dtb_checksum()-3406: calc ffb5c9ab, store ffb5c9ab
- _verify_dtb_checksum()-3406: calc ffb5c9ab, store ffb5c9ab
- dtb_read()-3623: total valid 2
- update_old_dtb()-3604: do nothing
- aml_i2c_init_port init regs for 0
- fusb302_init: Device ID: 0x91
- CC connected in 0 as UFP
- fusb302 detect chip.port_num = 0
- amlkey_init() enter!
- [EFUSE_MSG]keynum is 1
- vpu: clk_level in dts: 7
- vpu: vpu_power_on
- vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
- vpu: vpu_module_init_config
- vpp: vpp_init
- vpp: g12a/b osd1 matrix rgb2yuv ..............
- vpp: g12a/b osd2 matrix rgb2yuv..............
- vpp: g12a/b osd3 matrix rgb2yuv..............
- cvbs: cpuid:0x29
- lcd: detect mode: tablet, key_valid: 0
- lcd: load config from dts
- lcd: pinctrl_version: 2
- lcd: use panel_type=lcd_1
- lcd: bl: pinctrl_version: 2
- lcd: bl: name: backlight_pwm, method: 1
- lcd: bl: aml_bl_power_ctrl: 0
- Net: dwmac.ff3f0000amlkey_init() enter!
- amlkey_init() 71: already init!
- [EFUSE_MSG]keynum is 1
- MACADDR:02:00:00:1c:05:01(from chipid)
- CONFIG_AVB2:
- Start read misc partition datas!
- info->magic =
- info->version_major = 1
- info->version_minor = 0
- info->slots[0].priority = 15
- info->slots[0].tries_remaining = 7
- info->slots[0].successful_boot = 0
- info->slots[1].priority = 14
- info->slots[1].tries_remaining = 7
- info->slots[1].successful_boot = 0
- info->crc32 = -1075449479
- active slot = 0
- wipe_data=successful
- wipe_cache=successful
- upgrade_step=2
- reboot_mode:::: cold_boot
- lcd: error: outputmode[576cvbs] is not support
- hpd_state=1
- edid preferred_mode is 2160p60hz[97]
- hdr mode is 1
- dv mode is ver:0 len: 5
- hdr10+ mode is 1
- [OSD]load fb addr from dts:/meson-fb
- [OSD]set initrd_high: 0x7f800000
- [OSD]fb_addr for logo: 0x7f800000
- [OSD]load fb addr from dts:/meson-fb
- [OSD]fb_addr for logo: 0x7f800000
- [OSD]VPP_OFIFO_SIZE:0xfff01fff
- [CANVAS]canvas init
- [CANVAS]addr=0x7f800000 width=3840, height=2160
- [OSD]osd_hw.free_dst_data: 0,1919,0,1079
- [OSD]osd1_update_disp_freescale_enable
- cvbs: outputmode[1080p60hz] is invalid
- vpp: vpp_matrix_update: 2
- set hdmitx VIC = 16
- config HPLL = 5940000 frac_rate = 1
- HPLL: 0x3b3a04f7
- HPLL: 0x1b3a04f7
- HPLLv1: 0xdb3a04f7
- config HPLL done
- j = 6 vid_clk_div = 1
- hdmitx phy setting done
- hdmitx: set enc for VIC: 16
- enc_vpu_bridge_reset[1235]
- rx version is 2.0 div=10
- vpp: sdr_mode = 2
- vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 1
- normal power on
- boot wol: disable
- saradc: 0x289, hw_ver: 0x31
- gpio: pin GPIOAO_7 (gpio 7) value is 1
- port mode is usb3.0
- Command: bcb uboot-command
- Start read misc partition datas!
- BCB hasn't any datas,exit!
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