LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ITCE211Project_library.ALL;

ENTITY pe IS

    PORT (
           clk : IN STD_LOGIC;
		    eni,reset : in std_logic:='0' ;
          numberin : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
          numberout: OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
          eno : OUT STD_LOGIC :='0'
    );

END entity ;

ARCHITECTURE behavior OF pe IS

    SIGNAL stored : STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0) := (OTHERS => '0');


BEGIN

    PROCESS (clk)
    BEGIN
	          IF rising_edge (clk) THEN
            IF eni = '1' THEN
                IF numberin > stored THEN
                    eno <= '1';
                    numberout <= stored;
                    stored <= numberin;
                ELSE
                    eno <= '1';
                    numberout <= numberin;
                END IF;
            END IF;
        END IF;

		      END PROCESS;

END ARCHITECTURE ;