import acumulador
import inv
import mux
from somador_4bits import full_adder4, int2bus

A = 15
Sel0 = 0
Sel1 = 1
ck = 0
acc_S = 'X'

def addac(A, Sel0, Sel1, ck, anterior):
    inv_S = 15 - A

    mux0_S = mux.mux2(A, inv_S, Sel0)

    if anterior != 0 and anterior != 1:
        ant = 0
    else:
        ant = anterior

    add_S, COUT = full_adder4(int2bus(mux0_S), int2bus(ant), Sel0)

    S = mux.mux2(mux0_S, add_S, Sel1)

    acc_S = acumulador.acumula([S, ck], anterior)

    if acc_S == 15:
        acc_S = 1

    print('{0:04b}'.format(A) + "_" +
          str(Sel0) + "_" +
          str(Sel1) + "_" +
          str(ck) + "_" +
          '{0:04b}'.format(add_S) + "_" +
          str(acc_S))

    return acc_S

a = addac(15, 0, 0, 0, acc_S)
a = addac(15, 0, 0, 1, a)
a = addac(1, 0, 1, 0, a)
a = addac(0, 0, 0, 1, a)
a = addac(15, 0, 1, 0, a)
a = addac(15, 0, 1, 1, a)