`timescale 1ns/100ps


module tb;

    reg clk;
    reg f1,f2;
    reg reset;

    int cnt=0;



    wire [15:0] addr;
    trireg [ 7:0] data;

    wire sync,dbin,wr_n;




    initial
    begin
        clk = 1'b1;

        forever
        begin
            #(0.5);
            clk = ~clk;
        end
    end



    always @(posedge clk)
    begin
        cnt++;
        if(cnt>=100) cnt=0;

        if( cnt==0 )
            f1 <= 1'b1;
        else
            f1 <= 1'b0;

        if( cnt==50 )
            f2 <= 1'b1;
        else
            f2 <= 1'b0;
    end


    initial
    begin
        reset = 1'b1;

        repeat(10) @(posedge f2);

        reset <= 1'b0;
    end





    vm80a vm80a
    (
        .pin_clk  (clk),
        .pin_f1   (f1),
        .pin_f2   (f2),
        .pin_reset(reset),
        .pin_a    (addr),
        .pin_d    (data),
        .pin_hold (1'b0),
        .pin_hlda (),
        .pin_ready(1'b1),
        .pin_wait (),
        .pin_int  (1'b0),
        .pin_inte (),
        .pin_sync (sync),
        .pin_dbin (dbin),
        .pin_wr_n (wr_n)
    );









    // simple ROM
    reg [7:0] rom [0:15] =
    '{
        8'h31, //
        8'h10, //
        8'h80, // ld   sp,#8010

        8'h3e, //
        8'h00, // ld   a,#00

        8'h06, //
        8'h01, // ld   b,#01

        8'h90, // sub  b

        8'hf5, // push af

        8'h3e, //
        8'h01, // ld   a,#01

        8'h06, //
        8'h00, // ld   b,#00

        8'h90, // sub  b

        8'hf5, // push af

        8'h76  // halt
    };

    assign data = (dbin && addr<16) ? rom[addr] : 8'hZZ;


    // simple RAM
    reg [7:0] ram [0:15];

    assign data = (dbin && addr>=32768) ? ram[addr[3:0]] : 8'hZZ;

    always @(posedge wr_n)
    if( addr>=32768 )
        ram[addr[3:0]] = data;


endmodule