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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity MODULE is
- port( CLK, RESET: in std_logic;
- LED: out std_logic);
- end MODULE;
- architecture arch of MODULE is
- --##INSERT YOUR CODE HERE
- signal led_state : std_logic;
- signal counter : std_logic_vector(26 downto 0) := (others => '0');
- signal ticksek : std_logic;
- begin
- process(CLK, RESET)
- begin
- if RESET = '1' then
- counter<=(others=>'0');
- elsif (CLK='1' and CLK'event) then
- if counter="101111101011110000100000000" then
- --101111101011110000100000000
- ticksek <= '1';
- counter <= (others => '0');
- else
- ticksek <= '0';
- counter<=counter+1;
- end if;
- end if;
- end process;
- --ticksek <= '1' when counter = "00000000000000000000000011" else '0';
- process(CLK,RESET)
- begin
- led_state <= '1';
- if RESET = '1' then
- led_state <= '1';
- elsif ticksek='1' then
- case led_state is
- when '1' => led_state <= '0';
- when others => led_state <= '1';
- end case;
- end if;
- end process;
- LED <= led_state;
- end arch;
- --##INSERT YOUR CODE HERE END
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