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Dec 11th, 2019
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_unsigned.all;
  4.  
  5. entity MODULE is
  6. port( CLK, RESET: in std_logic;
  7. LED: out std_logic);
  8. end MODULE;
  9.  
  10. architecture arch of MODULE is
  11. --##INSERT YOUR CODE HERE
  12. signal led_state : std_logic;
  13. signal counter : std_logic_vector(26 downto 0) := (others => '0');
  14. signal ticksek : std_logic;
  15. begin
  16. process(CLK, RESET)
  17. begin
  18. if RESET = '1' then
  19. counter<=(others=>'0');
  20. elsif (CLK='1' and CLK'event) then
  21. if counter="101111101011110000100000000" then
  22. --101111101011110000100000000
  23. ticksek <= '1';
  24. counter <= (others => '0');
  25. else
  26. ticksek <= '0';
  27. counter<=counter+1;
  28. end if;
  29. end if;
  30. end process;
  31. --ticksek <= '1' when counter = "00000000000000000000000011" else '0';
  32.  
  33. process(CLK,RESET)
  34. begin
  35. led_state <= '1';
  36. if RESET = '1' then
  37. led_state <= '1';
  38. elsif ticksek='1' then
  39. case led_state is
  40. when '1' => led_state <= '0';
  41. when others => led_state <= '1';
  42. end case;
  43. end if;
  44. end process;
  45. LED <= led_state;
  46. end arch;
  47. --##INSERT YOUR CODE HERE END
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