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Host_Device_Tree

Cheros
Apr 1st, 2020
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  1. /*
  2. * Copyright 2017-2020 NXP
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9.  
  10. #include <dt-bindings/interrupt-controller/arm-gic.h>
  11. #include <dt-bindings/clock/s32gen1-clock.h>
  12.  
  13. /memreserve/ 0x8000fff8 0x00010000;
  14.  
  15. / {
  16. interrupt-parent = <&gic>;
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19.  
  20. aliases {
  21. can0 = &can0;
  22. can1 = &can1;
  23. can2 = &can2;
  24. can3 = &can3;
  25.  
  26. serial0 = &uart0;
  27. serial1 = &uart1;
  28. serial2 = &uart2;
  29. };
  30.  
  31. reserved-memory {
  32. #address-cells = <2>;
  33. #size-cells = <2>;
  34. ranges;
  35.  
  36. /* 4Mb shared memory for PCIe shared mem transfers, EP mode */
  37. pci_shared_memory: shm@0xc0000000 {
  38. compatible = "fsl,s32gen1-shm";
  39. reg = <0x0 0xc0000000 0x0 0x400000>; /* 4 MB */
  40. no-map;
  41. };
  42. };
  43.  
  44. cpus {
  45. #address-cells = <2>;
  46. #size-cells = <0>;
  47.  
  48. cpu0: cpu@0 {
  49. device_type = "cpu";
  50. compatible = "arm,cortex-a53";
  51. reg = <0x0 0x0>;
  52. /* enable-method (psci/spin-table) and the
  53. cpu-release-addr (if the latter) will be fixed up
  54. by u-boot, unless explicitly specified here.
  55. */
  56. };
  57. cpu1: cpu@1 {
  58. device_type = "cpu";
  59. compatible = "arm,cortex-a53";
  60. reg = <0x0 0x1>;
  61. };
  62. cpu2: cpu@100 {
  63. device_type = "cpu";
  64. compatible = "arm,cortex-a53";
  65. reg = <0x0 0x100>;
  66. };
  67. cpu3: cpu@101 {
  68. device_type = "cpu";
  69. compatible = "arm,cortex-a53";
  70. reg = <0x0 0x101>;
  71. };
  72.  
  73. cluster0_l2_cache: l2-cache0 {
  74. compatible = "cache";
  75. status = "disabled";
  76. };
  77.  
  78. cluster1_l2_cache: l2-cache1 {
  79. compatible = "cache";
  80. status = "disabled";
  81. };
  82.  
  83. };
  84.  
  85. clocks {
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88.  
  89. fxosc: fxosc {
  90. compatible = "fixed-clock";
  91. #clock-cells = <0>;
  92. };
  93. firc {
  94. compatible = "fixed-clock";
  95. clock-frequency = <48000000>;
  96. #clock-cells = <0>;
  97. };
  98. sirc {
  99. compatible = "fixed-clock";
  100. clock-frequency = <32000>;
  101. #clock-cells = <0>;
  102. };
  103. serdes_ext: serdes_ext {
  104. compatible = "fixed-clock";
  105. #clock-cells = <0>;
  106. };
  107. };
  108.  
  109. pmu {
  110. compatible = "arm,armv8-pmuv3";
  111. interrupts = <0 0x3c 0x4>,
  112. <0 0x3d 0x4>,
  113. <0 0x3e 0x4>,
  114. <0 0x3f 0x4>;
  115. };
  116.  
  117. generic_timer: timer {
  118. compatible = "arm,armv8-timer";
  119. interrupts = <1 13 0xf08>,
  120. <1 14 0xf08>,
  121. <1 11 0xf08>,
  122. <1 10 0xf08>;
  123. };
  124.  
  125. mc_cgm0: mc_cgm0@40030000 {
  126. compatible = "fsl,s32gen1-mc_cgm0";
  127. reg = <0x0 0x40030000 0x0 0x3000>;
  128. };
  129.  
  130. mc_cgm1: mc_cgm1@40034000 {
  131. compatible = "fsl,s32gen1-mc_cgm1";
  132. reg = <0x0 0x40034000 0x0 0x3000>;
  133. };
  134.  
  135. mc_cgm5: mc_cgm5@40068000 {
  136. compatible = "fsl,s32gen1-mc_cgm5";
  137. reg = <0x0 0x40068000 0x0 0x3000>;
  138. };
  139.  
  140. reset_0: reset@40078000 {
  141. compatible = "fsl,s32gen1-reset";
  142. /* MC RGM */
  143. reg = <0x0 0x40078000 0x0 0x3000>,
  144. /* MC ME */
  145. <0x0 0x40088000 0x0 0x1000>;
  146. };
  147.  
  148. a53_gpr: a53_gpr@4007C400 {
  149. compatible = "fsl,s32gen1-a53gpr";
  150. reg = <0x0 0x4007C400 0x0 0x100>;
  151. };
  152.  
  153. fccu: fccu@4030C000 {
  154. compatible = "fsl,s32gen1-fccu";
  155. reg = <0x0 0x4030C000 0x0 0x3000>;
  156. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  157. clock-names = "fccu";
  158. /* Address offset and configuration value for */
  159. /* NCF_E1 and NCFS_CFG2*/
  160. cfg_reg_off = <0x98 0x54>;
  161. cfg_reg_val = <0x78 0x1540>;
  162. status = "disabled";
  163. };
  164.  
  165. siul2_0 {
  166. compatible = "simple-mfd";
  167. #address-cells = <2>;
  168. #size-cells = <2>;
  169. /* MIDR registers
  170. * They physically exist in EIRQ
  171. * addr space but they don't belong
  172. * to GPIO
  173. */
  174. midr-reg = <0x0 0x4009C000 0x0 0x10>;
  175. status = "disabled";
  176. };
  177.  
  178. siul2_1 {
  179. compatible = "simple-mfd";
  180. #address-cells = <2>;
  181. #size-cells = <2>;
  182. /* MIDR registers
  183. * They physically exist in EIRQ
  184. * addr space but they don't belong
  185. * to GPIO
  186. */
  187. midr-reg = <0x0 0x44010000 0x0 0x10>;
  188. status = "disabled";
  189. };
  190.  
  191. swt3: swt@4010C000 {
  192. compatible = "fsl,s32gen1-wdt";
  193. reg = <0x0 0x4010C000 0x0 0x1000>;
  194. clocks = <&clks S32GEN1_CLK_FIRC>;
  195. clock-names = "swt";
  196. status = "disabled";
  197. };
  198.  
  199. stm0: stm@4011C000{
  200. compatible = "fsl,s32gen1-stm";
  201. reg = <0x0 0x4011C000 0x0 0x3000>;
  202. interrupts= <0 24 4>;
  203. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  204. clock-names = "stm";
  205. cpu = <2>;
  206. status = "disabled";
  207. };
  208.  
  209. stm1: stm@40120000{
  210. compatible = "fsl,s32gen1-stm";
  211. reg = <0x0 0x40120000 0x0 0x3000>;
  212. interrupts= <0 25 4>;
  213. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  214. clock-names = "stm";
  215. cpu = <3>;
  216. status = "disabled";
  217. };
  218.  
  219. edma0: dma-controller@40144000 {
  220. #dma-cells = <2>;
  221. compatible = "fsl,s32gen1-edma";
  222. reg = <0x0 0x40144000 0x0 0x24000>,
  223. <0x0 0x4012C000 0x0 0x3000>,
  224. <0x0 0x40130000 0x0 0x3000>;
  225. dma-channels = <32>;
  226. interrupts = <0 8 4>,
  227. <0 9 4>,
  228. <0 10 4>;
  229. interrupt-names = "edma-tx_0-15",
  230. "edma-tx_16-31",
  231. "edma-err";
  232. clock-names = "dmamux0", "dmamux1";
  233. clocks = <&clks S32GEN1_CLK_XBAR>,
  234. <&clks S32GEN1_CLK_XBAR>;
  235. status = "disabled";
  236. };
  237.  
  238. pit0: pit@40188000{
  239. compatible = "fsl,s32gen1-pit";
  240. reg = <0x0 0x40188000 0x0 0x3000>;
  241. interrupts= <0 53 4>;
  242. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  243. clock-names = "pit";
  244. cpu = <0>;
  245. status = "disabled";
  246. };
  247.  
  248. mscm0: mscm@40198000 {
  249. compatible = "fsl,s32gen1-mscm";
  250.  
  251. reg = <0x0 0x40198000 0x0 0x1000>;
  252.  
  253. /* CPU2CPU interrupts */
  254. interrupts = <0 1 4>, // CPU to M7/A53/R52 interrupt#0 (GIC 33)
  255. <0 2 4>, // CPU to M7/A53/R52 interrupt#1 (GIC 34)
  256. <0 3 4>; // CPU to M7/A53/R52 interrupt#2 (GIC 35)
  257. };
  258.  
  259. can0: flexcan@401B4000{
  260. compatible = "fsl,s32gen1-flexcan";
  261. reg = <0x0 0x401B4000 0x0 0xA000>;
  262. interrupts = <0 37 4>,
  263. <0 38 4>,
  264. <0 39 4>,
  265. <0 40 4>;
  266. interrupt-names = "state", "berr", "mb_0-7", "mb_8-127";
  267. clocks = <&clks S32GEN1_CLK_CAN>,
  268. <&clks S32GEN1_CLK_XBAR_DIV3>;
  269. clock-names = "per", "ipg";
  270. status = "disabled";
  271. };
  272.  
  273. can1: flexcan@401BE000{
  274. compatible = "fsl,s32gen1-flexcan";
  275. reg = <0x0 0x401BE000 0x0 0xA000>;
  276. interrupts = <0 41 4>,
  277. <0 42 4>,
  278. <0 43 4>,
  279. <0 44 4>;
  280. interrupt-names = "state", "berr", "mb_0-7", "mb_8-127";
  281. clocks = <&clks S32GEN1_CLK_CAN>,
  282. <&clks S32GEN1_CLK_XBAR_DIV3>;
  283. clock-names = "per", "ipg";
  284. status = "disabled";
  285. };
  286.  
  287. uart0:serial@401C8000 {
  288. compatible = "fsl,s32-linflexuart";
  289. reg = <0x0 0x401C8000 0x0 0x3000>;
  290. interrupts = <0 82 1>;
  291. clocks = <&clks S32GEN1_CLK_LIN_BAUD>,
  292. <&clks S32GEN1_CLK_LIN>;
  293. clock-names = "lin", "ipg";
  294. dmas = <&edma0 0 4>,
  295. <&edma0 0 3>;
  296. dma-names = "rx", "tx";
  297. };
  298.  
  299. uart1:serial@401CC000 {
  300. compatible = "fsl,s32-linflexuart";
  301. reg = <0x0 0x401CC000 0x0 0x3000>;
  302. interrupts = <0 83 1>;
  303. clocks = <&clks S32GEN1_CLK_LIN_BAUD>,
  304. <&clks S32GEN1_CLK_LIN>;
  305. clock-names = "lin", "ipg";
  306. dmas = <&edma0 0 6>,
  307. <&edma0 0 5>;
  308. dma-names = "rx", "tx";
  309. };
  310.  
  311. spi0: spi@401D4000 {
  312. compatible = "fsl,s32gen1-dspi";
  313. reg = <0x0 0x401D4000 0x0 0x3000>;
  314. interrupts = <0 85 4>;
  315. clocks = <&clks S32GEN1_CLK_DSPI>;
  316. clock-names = "dspi";
  317. spi-num-chipselects = <8>;
  318. bus-num = <0>;
  319. spi-fifo-size = <5>;
  320. spi-extended-mode;
  321. spi-cpol;
  322. spi-cpha;
  323. status = "disabled";
  324. };
  325.  
  326. spi1: spi@401D8000 {
  327. compatible = "fsl,s32gen1-dspi";
  328. reg = <0x0 0x401D8000 0x0 0x3000>;
  329. interrupts = <0 86 4>;
  330. clocks = <&clks S32GEN1_CLK_DSPI>;
  331. clock-names = "dspi";
  332. spi-num-chipselects = <5>;
  333. bus-num = <1>;
  334. spi-fifo-size = <5>;
  335. spi-extended-mode;
  336. spi-cpol;
  337. spi-cpha;
  338. status = "disabled";
  339. };
  340.  
  341. spi2: spi@401DC000 {
  342. compatible = "fsl,s32gen1-dspi";
  343. reg = <0x0 0x401DC000 0x0 0x3000>;
  344. interrupts = <0 87 4>;
  345. clocks = <&clks S32GEN1_CLK_DSPI>;
  346. clock-names = "dspi";
  347. spi-num-chipselects = <5>;
  348. bus-num = <2>;
  349. spi-fifo-size = <5>;
  350. spi-extended-mode;
  351. spi-cpol;
  352. spi-cpha;
  353. status = "disabled";
  354. };
  355.  
  356. i2c0: i2c@401E4000 {
  357. #address-cells = <1>;
  358. #size-cells = <0>;
  359. compatible = "fsl,s32gen1-i2c";
  360. reg = <0x0 0x401E4000 0x0 0x1000>;
  361. interrupts =<0 92 4>;
  362. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  363. clock-names = "ipg";
  364. dmas = <&edma0 0 16>,
  365. <&edma0 0 17>;
  366. dma-names = "rx","tx";
  367. status = "disabled";
  368. };
  369.  
  370. i2c1: i2c@401E8000 {
  371. #address-cells = <1>;
  372. #size-cells = <0>;
  373. compatible = "fsl,s32gen1-i2c";
  374. reg = <0x0 0x401E8000 0x0 0x1000>;
  375. interrupts =<0 93 4>;
  376. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  377. clock-names = "ipg";
  378. dmas = <&edma0 0 18>,
  379. <&edma0 0 19>;
  380. dma-names = "rx","tx";
  381. status = "disabled";
  382. };
  383.  
  384. i2c2: i2c@401EC000 {
  385. #address-cells = <1>;
  386. #size-cells = <0>;
  387. compatible = "fsl,s32gen1-i2c";
  388. reg = <0x0 0x401EC000 0x0 0x1000>;
  389. interrupts =<0 94 4>;
  390. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  391. clock-names = "ipg";
  392. dmas = <&edma1 1 16>,
  393. <&edma1 1 17>;
  394. dma-names = "rx","tx";
  395. status = "disabled";
  396. };
  397.  
  398. swt4: swt@40200000 {
  399. compatible = "fsl,s32gen1-wdt";
  400. reg = <0x0 0x40200000 0x0 0x1000>;
  401. clocks = <&clks S32GEN1_CLK_FIRC>;
  402. clock-names = "swt";
  403. status = "disabled";
  404. };
  405.  
  406. swt5: swt@40204000 {
  407. compatible = "fsl,s32gen1-wdt";
  408. reg = <0x0 0x40204000 0x0 0x1000>;
  409. clocks = <&clks S32GEN1_CLK_FIRC>;
  410. clock-names = "swt";
  411. status = "disabled";
  412. };
  413.  
  414. swt6: swt@40208000 {
  415. compatible = "fsl,s32gen1-wdt";
  416. reg = <0x0 0x40208000 0x0 0x1000>;
  417. clocks = <&clks S32GEN1_CLK_FIRC>;
  418. clock-names = "swt";
  419. status = "disabled";
  420. };
  421.  
  422. hse: crypto {
  423. compatible = "simple-bus";
  424. #address-cells = <2>;
  425. #size-cells = <2>;
  426. #interrupt-cells = <3>;
  427. ranges = <0x0 0x0 0x0 0x40210000 0x0 0x4000>;
  428.  
  429. mu0b@40210000 {
  430. compatible = "fsl,s32gen1-hse";
  431. reg = <0x0 0x0 0x0 0x1000>;
  432. interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, /* GIC 135 */
  433. <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>, /* GIC 136 */
  434. <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>; /* GIC 137 */
  435. interrupt-names = "hse-mu0b-ack",
  436. "hse-mu0b-rx",
  437. "hse-mu0b-err";
  438. };
  439. mu1b@40211000 {
  440. compatible = "fsl,s32gen1-hse";
  441. reg = <0x0 0x1000 0x0 0x1000>;
  442. interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>, /* GIC 138 */
  443. <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, /* GIC 139 */
  444. <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>; /* GIC 140 */
  445. interrupt-names = "hse-mu1b-ack",
  446. "hse-mu1b-rx",
  447. "hse-mu1b-err";
  448. };
  449. mu2b@40212000 {
  450. compatible = "fsl,s32gen1-hse";
  451. reg = <0x0 0x2000 0x0 0x1000>;
  452. interrupts = <GIC_SPI 109 IRQ_TYPE_EDGE_RISING>, /* GIC 141 */
  453. <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, /* GIC 142 */
  454. <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>; /* GIC 143 */
  455. interrupt-names = "hse-mu2b-ack",
  456. "hse-mu2b-rx",
  457. "hse-mu2b-err";
  458. };
  459. mu3b@40213000 {
  460. compatible = "fsl,s32gen1-hse";
  461. reg = <0x0 0x3000 0x0 0x1000>;
  462. interrupts = <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>, /* GIC 144 */
  463. <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, /* GIC 145 */
  464. <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; /* GIC 146 */
  465. interrupt-names = "hse-mu3b-ack",
  466. "hse-mu3b-rx",
  467. "hse-mu3b-err";
  468. };
  469. };
  470.  
  471. edma1: dma-controller@40244000 {
  472. #dma-cells = <2>;
  473. compatible = "fsl,s32gen1-edma";
  474. reg = <0x0 0x40244000 0x0 0x24000>,
  475. <0x0 0x4022C000 0x0 0x3000>,
  476. <0x0 0x40230000 0x0 0x3000>;
  477. dma-channels = <32>;
  478. interrupts = <0 11 4>,
  479. <0 12 4>,
  480. <0 13 4>;
  481. interrupt-names = "edma-tx_0-15",
  482. "edma-tx_16-31",
  483. "edma-err";
  484. clock-names = "dmamux0", "dmamux1";
  485. clocks = <&clks S32GEN1_CLK_XBAR>,
  486. <&clks S32GEN1_CLK_XBAR>;
  487. status = "disabled";
  488. };
  489.  
  490. pit1: pit@40288000{
  491. compatible = "fsl,s32gen1-pit";
  492. reg = <0x0 0x40288000 0x0 0x3000>;
  493. interrupts= <0 54 4>;
  494. cpu = <1>;
  495. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  496. clock-names = "pit";
  497. status = "disabled";
  498. };
  499.  
  500. can2: flexcan@402A8000{
  501. compatible = "fsl,s32gen1-flexcan";
  502. reg = <0x0 0x402A8000 0x0 0xA000>;
  503. interrupts = <0 45 4>,
  504. <0 46 4>,
  505. <0 47 4>,
  506. <0 48 4>;
  507. interrupt-names = "state", "berr", "mb_0-7", "mb_8-127";
  508. clocks = <&clks S32GEN1_CLK_CAN>,
  509. <&clks S32GEN1_CLK_XBAR_DIV3>;
  510. clock-names = "per", "ipg";
  511. status = "disabled";
  512. };
  513.  
  514. can3: flexcan@402B2000{
  515. compatible = "fsl,s32gen1-flexcan";
  516. reg = <0x0 0x402B2000 0x0 0xA000>;
  517. interrupts = <0 49 4>,
  518. <0 50 4>,
  519. <0 51 4>,
  520. <0 52 4>;
  521. interrupt-names = "state", "berr", "mb_0-7", "mb_8-127";
  522. clocks = <&clks S32GEN1_CLK_CAN>,
  523. <&clks S32GEN1_CLK_XBAR_DIV3>;
  524. clock-names = "per", "ipg";
  525. status = "disabled";
  526. };
  527.  
  528. uart2:serial@402BC000 {
  529. compatible = "fsl,s32-linflexuart";
  530. reg = <0x0 0x402BC000 0x0 0x3000>;
  531. interrupts = <0 84 1>;
  532. clocks = <&clks S32GEN1_CLK_LIN_BAUD>,
  533. <&clks S32GEN1_CLK_LIN>;
  534. clock-names = "lin", "ipg";
  535. dmas = <&edma1 1 4>,
  536. <&edma1 1 3>;
  537. dma-names = "rx", "tx";
  538. };
  539.  
  540. spi3: spi@402C8000 {
  541. compatible = "fsl,s32gen1-dspi";
  542. reg = <0x0 0x402C8000 0x0 0x3000>;
  543. interrupts = <0 88 4>;
  544. clocks = <&clks S32GEN1_CLK_DSPI>;
  545. clock-names = "dspi";
  546. spi-num-chipselects = <5>;
  547. bus-num = <3>;
  548. spi-fifo-size = <5>;
  549. spi-extended-mode;
  550. spi-cpol;
  551. spi-cpha;
  552. status = "disabled";
  553. };
  554.  
  555. spi4: spi@402CC000 {
  556. compatible = "fsl,s32gen1-dspi";
  557. reg = <0x0 0x402CC000 0x0 0x3000>;
  558. interrupts = <0 89 4>;
  559. clocks = <&clks S32GEN1_CLK_DSPI>;
  560. clock-names = "dspi";
  561. spi-num-chipselects = <5>;
  562. bus-num = <4>;
  563. spi-fifo-size = <5>;
  564. spi-extended-mode;
  565. spi-cpol;
  566. spi-cpha;
  567. status = "disabled";
  568. };
  569.  
  570. spi5: spi@402D0000 {
  571. compatible = "fsl,s32gen1-dspi";
  572. reg = <0x0 0x402D0000 0x0 0x3000>;
  573. interrupts = <0 90 4>;
  574. clocks = <&clks S32GEN1_CLK_DSPI>;
  575. clock-names = "dspi";
  576. spi-num-chipselects = <5>;
  577. bus-num = <5>;
  578. spi-fifo-size = <5>;
  579. spi-extended-mode;
  580. spi-cpol;
  581. spi-cpha;
  582. status = "disabled";
  583. };
  584.  
  585. i2c3: i2c@402D8000 {
  586. #address-cells = <1>;
  587. #size-cells = <0>;
  588. compatible = "fsl,s32gen1-i2c";
  589. reg = <0x0 0x402D8000 0x0 0x1000>;
  590. interrupts =<0 95 4>;
  591. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  592. clock-names = "ipg";
  593. dmas = <&edma1 1 18>,
  594. <&edma1 1 19>;
  595. dma-names = "rx","tx";
  596. status = "disabled";
  597. };
  598.  
  599. i2c4: i2c@402DC000 {
  600. #address-cells = <1>;
  601. #size-cells = <0>;
  602. compatible = "fsl,s32gen1-i2c";
  603. reg = <0x0 0x402DC000 0x0 0x1000>;
  604. interrupts =<0 96 4>;
  605. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>;
  606. clock-names = "ipg";
  607. dmas = <&edma1 1 20>,
  608. <&edma1 1 21>;
  609. dma-names = "rx","tx";
  610. status = "disabled";
  611. };
  612.  
  613. usdhc0: usdhc@402F0000{
  614. compatible = "fsl,s32gen1-usdhc";
  615. reg = <0x0 0x402F0000 0x0 0x1000>;
  616. interrupts = <0 36 4>;
  617. clocks = <&clks S32GEN1_CLK_XBAR_DIV3>,
  618. <&clks S32GEN1_CLK_XBAR>,
  619. <&clks S32GEN1_CLK_SDHC>;
  620. clock-names = "ipg", "ahb", "per";
  621. bus-width = <8>;
  622. status = "disabled";
  623. };
  624.  
  625. gic: interrupt-controller@50800000 {
  626. compatible = "arm,gic-v3";
  627. #interrupt-cells = <3>;
  628. #address-cells = <2>;
  629. #size-cells = <2>;
  630. interrupt-controller;
  631. reg = <0 0x50800000 0 0x10000>,
  632. <0 0x50880000 0 0x200000>,
  633. <0 0x50400000 0 0x2000>,
  634. <0 0x50410000 0 0x2000>,
  635. <0 0x50420000 0 0x2000>;
  636. interrupts = <1 9 0xf04>;
  637. };
  638.  
  639. rtc0: rtc@40060000 {
  640. compatible = "fsl,s32gen1-rtc";
  641. #interrupt-cells = <3>;
  642. reg = <0x0 0x40060000 0x0 0x1000>;
  643. interrupts = <0 121 4>; // RTC irq - GIC 153
  644. /* Input clock selection: use the 48MHz FIRC with DIV512,
  645. * for a roll-over time of just under 13 hours.
  646. */
  647. clksel = <2>; // 2: FIRC; 0: SIRC
  648. dividers = <1 0>; // div512 enabled; div32 disabled
  649. };
  650.  
  651. gmac0: ethernet@4033c000 {
  652. compatible = "fsl,s32cc-dwmac";
  653. reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
  654. <0x0 0x4007C004 0x0 0x4>; /* S32 CTRL_STS reg */
  655. interrupt-parent = <&gic>;
  656. interrupts = <0 57 4>;
  657. interrupt-names = "macirq";
  658. tx-fifo-depth = <20480>;
  659. rx-fifo-depth = <20480>;
  660. clocks = <&clks S32GEN1_CLK_XBAR>, <&clks S32GEN1_CLK_XBAR>,
  661. <&clks S32GEN1_CLK_GMAC_TX>;
  662. clock-names = "stmmaceth", "pclk", "tx";
  663. gmac0_mdio: mdio0 {
  664. compatible = "snps,dwmac-mdio";
  665. #address-cells = <1>;
  666. #size-cells = <0>;
  667. };
  668. };
  669.  
  670. pcie0: pcie@40400000 {
  671. compatible = "fsl,s32gen1-pcie";
  672. reg = <0x00 0x40400000 0x0 0x00001000 /* dbi registers */
  673. 0x00 0x40420000 0x0 0x00001000 /* dbi2 registers */
  674. 0x00 0x40460000 0x0 0x00001000 /* atu registers */
  675. 0x00 0x40470000 0x0 0x00001000 /* dma registers */
  676. 0x00 0x40480000 0x0 0x00004000 /* ctrl registers */
  677. 0x58 0x00000000 0x0 0x00002000 /* RC config space */
  678. 0x58 0x40000000 0x0 0x40000000>; /* EP addr space, 1GB */
  679. reg-names = "dbi", "dbi2", "atu", "dma", "ctrl",
  680. "config", "addr_space";
  681. #address-cells = <3>;
  682. #size-cells = <2>;
  683. device_type = "pci";
  684. device_id = <0>;
  685. ranges =
  686. /* downstream I/O */
  687. <0x81000000 0x0 0x00000000 0x58 0x00003000 0x0 0x00010000
  688. /* non-prefetchable memory */
  689. 0x82000000 0x0 0x00013000 0x58 0x00013000 0x0 0x40000000>;
  690.  
  691. num-lanes = <2>;
  692. max-link-speed = <3>;
  693. bus-range = <0x0 0xff>;
  694. interrupts = <0 124 4>, <0 123 4>, <0 125 4>,
  695. <0 126 4>, <0 127 4>, <0 132 4>,
  696. <0 133 4>, <0 134 4>;
  697. interrupt-names = "link_req_stat", "dma","msi",
  698. "phy_link_down", "phy_link_up", "misc",
  699. "pcs", "tlp_req_no_comp";
  700. #interrupt-cells = <1>;
  701. interrupt-map-mask = <0 0 0 0x7>;
  702. interrupt-map = <0 0 0 1 &gic 0 128 4>,
  703. <0 0 0 2 &gic 0 129 4>,
  704. <0 0 0 3 &gic 0 130 4>,
  705. <0 0 0 4 &gic 0 131 4>;
  706.  
  707. /* EP mode only */
  708. num-ib-windows = <6>;
  709. num-ob-windows = <6>;
  710.  
  711. status = "disabled";
  712. };
  713.  
  714. pcie1: pcie@44100000 {
  715. compatible = "fsl,s32gen1-pcie";
  716. reg = <0x00 0x44100000 0x0 0x00001000 /* dbi registers */
  717. 0x00 0x44120000 0x0 0x00001000 /* dbi2 registers */
  718. 0x00 0x44160000 0x0 0x00001000 /* atu registers */
  719. 0x00 0x44170000 0x0 0x00001000 /* dma registers */
  720. 0x00 0x44180000 0x0 0x00004000 /* ctrl registers */
  721. 0x48 0x00000000 0x0 0x00002000 /* RC config space */
  722. 0x48 0x40000000 0x0 0x40000000>; /* EP addr space, 1GB */
  723. reg-names = "dbi", "dbi2", "atu", "dma", "ctrl",
  724. "config", "addr_space";
  725. #address-cells = <3>;
  726. #size-cells = <2>;
  727. device_type = "pci";
  728. device_id = <1>;
  729. ranges =
  730. /* downstream I/O */
  731. <0x81000000 0x0 0x00000000 0x48 0x00003000 0x0 0x00010000
  732. /* non-prefetchable memory */
  733. 0x82000000 0x0 0x00013000 0x48 0x00013000 0x0 0x40000000>;
  734.  
  735. num-lanes = <1>;
  736. max-link-speed = <3>;
  737. bus-range = <0x0 0xff>;
  738. interrupts = <0 215 4>, <0 214 4>, <0 216 4>,
  739. <0 217 4>, <0 218 4>, <0 223 4>,
  740. <0 224 4>, <0 225 4>;
  741. interrupt-names = "link_req_stat", "dma","msi",
  742. "phy_link_down", "phy_link_up", "misc",
  743. "pcs", "tlp_req_no_comp";
  744. #interrupt-cells = <1>;
  745. interrupt-map-mask = <0 0 0 0x7>;
  746. interrupt-map = <0 0 0 1 &gic 0 219 4>,
  747. <0 0 0 2 &gic 0 220 4>,
  748. <0 0 0 3 &gic 0 221 4>,
  749. <0 0 0 4 &gic 0 222 4>;
  750.  
  751. /* EP mode only */
  752. num-ib-windows = <6>;
  753. num-ob-windows = <6>;
  754.  
  755. status = "disabled";
  756. };
  757. };
  758.  
  759. &cluster0_l2_cache {
  760. status = "okay";
  761. };
  762.  
  763. &cluster1_l2_cache {
  764. status = "okay";
  765. };
  766.  
  767. &cpu0 {
  768. next-level-cache = <&cluster0_l2_cache>;
  769. };
  770.  
  771. &cpu1 {
  772. next-level-cache = <&cluster0_l2_cache>;
  773. };
  774.  
  775. &cpu2 {
  776. next-level-cache = <&cluster1_l2_cache>;
  777. };
  778.  
  779. &cpu3 {
  780. next-level-cache = <&cluster1_l2_cache>;
  781. };
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