verilog example

input wire signal;

reg [31:0]a = 0;

assign count = ^a;

always @(posedge clk)
begin
    a <= {a[30:0], signal};
end

vs

always @(posedge clk)
begin
    a <= {a[30:0], signal};
    count <= (^a[30:0])^signal;
end