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- From b4994493715c0e12127b6b98bfb4e66843bfbf80 Mon Sep 17 00:00:00 2001
- From: Karol Gugala <kgugala@antmicro.com>
- Date: Mon, 16 Sep 2019 17:16:28 +0200
- Subject: [PATCH] utils: vlog_to_pbtype: autoinfer carry chains on pins
- Signed-off-by: Karol Gugala <kgugala@antmicro.com>
- ---
- utils/vlog/vlog_to_pbtype.py | 17 +++++++++++++----
- 1 file changed, 13 insertions(+), 4 deletions(-)
- diff --git a/utils/vlog/vlog_to_pbtype.py b/utils/vlog/vlog_to_pbtype.py
- index 236013a1..847b9324 100755
- --- a/utils/vlog/vlog_to_pbtype.py
- +++ b/utils/vlog/vlog_to_pbtype.py
- @@ -451,7 +451,7 @@ def get_list_name_and_length(l: List[str]) -> Tuple[str, int]:
- return list_name, len(l)
- -def make_ports(clocks, mod, pb_type_xml, only_type=None):
- +def make_ports(clocks, mod, pb_type_xml, yj, only_type=None):
- for name, width, bits, iodir in mod.ports:
- ioattrs = {"name": name, "num_pins": str(width)}
- pclass = mod.net_attr(name, "PORT_CLASS")
- @@ -475,6 +475,15 @@ def make_ports(clocks, mod, pb_type_xml, only_type=None):
- port_attrs = mod.port_attrs(name)
- carry_name = port_attrs.get('carry', None)
- + if carry_name is None and width == 1:
- + for con in mod.port_conns(name):
- + for cell, celltype in mod.cells:
- + cmod = yj.module(celltype)
- + cellconns = mod.cell_conns(cell, iodir)
- + for port, net in cellconns:
- + if net == con:
- + cport_attrs = cmod.port_attrs(port)
- + carry_name = cport_attrs.get('carry', None)
- if carry_name:
- ET.SubElement(
- port_xml, 'pack_pattern', {
- @@ -745,9 +754,9 @@ def make_pb_type(
- # Create the pins for this pb_type
- clocks = yosys.run.list_clocks(args.infiles, mod.name)
- - make_ports(clocks, mod, pb_type_xml, "clocks")
- - make_ports(clocks, mod, pb_type_xml, "inputs")
- - make_ports(clocks, mod, pb_type_xml, "outputs")
- + make_ports(clocks, mod, pb_type_xml, yj, "clocks")
- + make_ports(clocks, mod, pb_type_xml, yj, "inputs")
- + make_ports(clocks, mod, pb_type_xml, yj, "outputs")
- if modes and not mode_processing:
- for mode in modes:
- --
- 2.23.0
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