nick

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity reg is
  generic(
    wordSize: natural :=4
  );
  port(
    clock, reset, load: in bit;
    d: in bit_vector(wordSize-1 downto 0);
    q: out bit_vector(wordSize-1 downto 0)
  );
end reg;

architecture arch of reg is
begin
  process(clock, reset, load)
  begin
    if (reset = '1') then
      q <= (others => '0');
    elsif (clock'event and clock='1') then
      if (load='1') then
        q <= d;
      end if;
    end if;
  end process;
end arch;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_BIT.ALL;
use IEEE.MATH_REAL.CEIL;
use IEEE.MATH_REAL.LOG2;

entity regfile is
  generic(
    regn: natural := 32;
    wordSize: natural := 64
  );
  port(
    clock, reset, regWrite : in bit;
    rr1, rr2, wr: in bit_vector(natural(ceil(log2(real(regn))))-1 downto 0);
    d: in bit_vector(wordSize-1 downto 0);
    q1, q2: out bit_vector(wordSize-1 downto 0)
  );
end regfile;

architecture behavioral of regfile is
  component reg is
        generic (
            wordSize : natural := 4
        );
        port (
            clock, reset, load : in bit;
            d : in bit_vector(wordSize - 1 downto 0);
            q : out bit_vector(wordSize - 1 downto 0)
        );
  end component;
  type registerFile is array(regn-1 downto 0) of bit_vector(wordSize-1 downto 0);
    signal write : registerFile;
    signal read : registerFile;
    signal zero : bit_vector (wordSize-1 downto 0);
begin
  gen: for i in 0 to regn-2 generate
    Rf: reg generic map (wordSize => wordSize)
          port map (clock, reset, regWrite, write(i), read(i));
  end generate gen;
  Rz: reg generic map (wordSize => wordSize)
        port map(clock, reset, regWrite, zero, read(regn-1));
  q1 <= read(to_integer(unsigned(rr1)));
  q2 <= read(to_integer(unsigned(rr2)));
  write(to_integer(unsigned(wr))) <= d;

end behavioral;