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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 14:28:13 03/23/2017
- -- Design Name:
- -- Module Name: Id - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity Id is
- Port ( X : in STD_LOGIC_VECTOR (63 downto 0);
- Y : out STD_LOGIC_VECTOR (63 downto 0));
- end Id;
- architecture Behavioral of Id is
- component P is
- Port ( X : in STD_LOGIC_VECTOR (63 downto 0);
- Y : out STD_LOGIC_VECTOR (63 downto 0));
- end component P;
- component NL is
- Port ( X : in STD_LOGIC_VECTOR (63 downto 0);
- Ka : in STD_LOGIC_VECTOR (63 downto 0);
- Kb : in STD_LOGIC_VECTOR (63 downto 0);
- Y : out STD_LOGIC_VECTOR (63 downto 0));
- end component NL;
- component NLi is
- Port ( X : in STD_LOGIC_VECTOR (63 downto 0);
- Ka : in STD_LOGIC_VECTOR (63 downto 0);
- Kb : in STD_LOGIC_VECTOR (63 downto 0);
- Y : out STD_LOGIC_VECTOR (63 downto 0));
- end component NLi;
- component KeyGen is
- Port ( Y : out STD_LOGIC_VECTOR (511 downto 0));
- end component KeyGen;
- signal buff : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi : STD_LOGIC_VECTOR (63 downto 0);
- signal buff1 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi1 : STD_LOGIC_VECTOR (63 downto 0);
- signal buff2 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi2 : STD_LOGIC_VECTOR (63 downto 0);
- signal buff3 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi3 : STD_LOGIC_VECTOR (63 downto 0);
- signal buff4 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi4 : STD_LOGIC_VECTOR (63 downto 0);
- signal buff5 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi5 : STD_LOGIC_VECTOR (63 downto 0);
- signal buff6 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi6 : STD_LOGIC_VECTOR (63 downto 0);
- signal buff7 : STD_LOGIC_VECTOR (63 downto 0);
- signal buffi7 : STD_LOGIC_VECTOR (63 downto 0);
- signal key : STD_LOGIC_VECTOR (511 downto 0);
- signal checker1 : STD_LOGIC_VECTOR (63 downto 0);
- signal checker2 : STD_LOGIC_VECTOR (63 downto 0);
- signal checker3 : STD_LOGIC_VECTOR (63 downto 0);
- signal checker4 : STD_LOGIC_VECTOR (63 downto 0);
- begin
- b0: KeyGen port map (key);
- b1: NL port map (X, key(511 downto 448), key(447 downto 384), buff);
- b2: P port map (buff, buffi);
- b3: NL port map (buffi, key(383 downto 320), key(319 downto 256), buff1);
- b4: P port map (buff1, buffi1);
- b5: NL port map (buffi1, key(255 downto 192), key(191 downto 128), buff2);
- b6: P port map (buff2, buffi2);
- b7: NL port map (buffi2, key(127 downto 64), key(63 downto 0), buff3);
- b8: P port map (buff3, buffi3);
- b9: buff4 <= buffi3;
- b10: P port map (buff4, buffi4);
- b11: NLi port map (buffi4, key(127 downto 64), key(63 downto 0), buff5);
- b12: P port map (buff5, buffi5);
- b13: NLi port map (buffi5, key(255 downto 192), key(191 downto 128), buff6);
- b14: P port map (buff6, buffi6);
- b15: NLi port map (buffi6, key(383 downto 320), key(319 downto 256), buff7);
- b16: P port map (buff7, buffi7);
- b17: NLi port map (buffi7, key(511 downto 448), key(447 downto 384), Y);
- b18: checker1 <= buff XOR Y;
- b19: checker2 <= buff1 XOR buff7;
- b20: checker3 <= buff2 XOR buff6;
- b21: checker4 <= buff3 XOR buff5;
- end Behavioral;
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