library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pamiec is
	port(
		key : in std_logic;
		clk : in std_logic;
		sw	:in std_logic_vector (7 downto 0);
		wr: in std_logic;
		HEX0 : out std_logic_vector(0 to 6);
		HEX1: out std_logic_vector(0 to 6)
		);
end pamiec;


architecture rtl of pamiec is
component RAM
	port(
		address : in std_logic_vector (4 downto 0);
		clock : in std_logic := '1';
		data : in std_logic_vector (7 downto 0);
		wren : in std_logic;
		q : out std_logic_vector (7 downto 0)
		);
end component;

component hex7seg
	port(
		hex : in std_logic_vector(3 downo 0);
		display : out std_logic_vector(0 to 6)
		);
end component;

signal currentCount : std_logic_vector (4 downto 0);
signal output : std_logic_vector (7 downto 0);
alias bit3_0 : std_logic_vector (3 downto 0) is output(3 downto 0);
alias bit7_4 : std_logic_vector (3 downto 0) is output(7 downto 4);

signal HEXTMP0 : std_logic_vector(0 to 6);
signal HEXTMP1 : std_logic_vector(0 to 6);

begin

	MEM : RAM port map (address=>currentCount, clock=>clk, data=>sw, wren=>wr, q=>output);
	SEG0 : hex7seg port map (hex=>bit3_0, display=>HEXTMP0);
	SEG1 : hex7seg port map (hex=>bit7_4, display=>HEXTMP1);

	process(key)
	begin
		if(key = '0' and key'event) then
			if(currentCount = "11111") then
			currentCount <= "00000";
			else
			currentCount <= currentCount + '1';
			end if;
		end if;
	end process;

	process(output)
	begin
	HEX0 <= HEXTMP0;
	HEX1 <= HEXTMP1;
	end process;

end rtl;