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- ---------------------------------------------------------------------------
- -- instruction_memory.vhd - Implementation of A Single-Port, 64 x 32-bit
- -- Instruction Memory.
- --
- -- Modified instruction memory from Lih Wen Koh's Single Cycle Core Processor
- ---------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- entity instruction_memory is
- port ( reset : in std_logic;
- clk : in std_logic;
- addr_in : in std_logic_vector(5 downto 0);
- insn_out : out std_logic_vector(31 downto 0) );
- end instruction_memory;
- architecture behavioral of instruction_memory is
- type mem_array is array(0 to 63) of std_logic_vector(31 downto 0);
- signal sig_insn_mem : mem_array;
- begin
- mem_process: process ( clk,
- addr_in ) is
- variable var_insn_mem : mem_array;
- variable var_addr : integer;
- begin
- if (reset = '1') then
- --Assembly Code
- --insn_0 : loop0: addi $1, $0, 70 - $1 <- $0 + 70, i=0, string address starting position
- --insn_1 : addi $2, $0, 3 - $2 <- $0 + 3, j=0, pattern address starting position
- --insn_2 : load $4, $0, 1 - load data 1($0) into $4, which is the pattern length
- --insn_3 : addi $5, $0, 0 - $5 <- $0 + 0, count=0
- --insn_4 : addi $6, $0, 0 - $6 <- $0 + 0, k=0, the index of pattern
- --insn_5 : addi $9, $0, 0 - $9 <- $0 + 0, the number of matching characters
- --insn_6 : load $7, $1, 0 - load data 0($1) into $7, which is a character of string
- --rd,rs,rt
- --insn_7 : beq loop0, $4, $0
- --insn_8 : noop - avoid data hazard, which is RAW
- --insn_9 : noop - avoid data hazard, which is RAW
- --
- --insn_10 : loop1: bne loop2, $7, $10 - if($7 != 0) go to loop2, not the final character
- --insn_11 : beq end, $0, $0 - jump to end, the final character
- --
- --insn_12 : loop2: addi $2, $0, 3 - $2 <- $0 + 3, pattern position for reset
- --insn_13 : addi $6, $0, 0 - $6 <- $0 + 0, pattern index for reset
- --
- --insn_14 : noop - avoid data hazard, which is RAW
- --insn_15 : noop - avoid data hazard, which is RAW
- --
- --insn_16 : loop7: bne loop3, $6, $4 - pattern index != pattern length
- --insn_17 : beq loop6, $6, $4 - pattern index == pattern length
- --
- --insn_18 : loop3: "80000000" - before load character from string, check testbench signal to allow read character
- --insn_19 : load $7, $1, 0 - load data 0($1) into $7, which is the character of string
- --insn_20 : load $8, $2, 0 - load data 0($2) into $8, which is the character of pattern
- --
- --insn_21 : noop - avoid data hazard, which is RAW
- --insn_22 : noop - avoid data hazard, which is RAW
- --
- --insn_23 : beq loop4, $7, $8 - if($7 == $8) go to loop4, character of pattern == character of string
- --insn_24 : bne loop5, $7, $8 - if($7 != $8) go to loop5, character of pattern != character of string
- --
- --insn_25 : loop4: addi $1, $1, 1 - $1 <- $1 + 1, string position ++
- --insn_26 : addi $2, $2, 1 - $2 <- $2 + 1, pattern position ++
- --insn_27 : addi $6, $6, 1 - $6 <- $6 + 1, pattern index ++
- --insn_28 : addi $9, $9, 1 - $9 <- $9 + 1, the number of matching characters ++
- --insn_29 : beq loop7, $0, $0 - jump to loop7
- --
- --insn_30 : loop5: addi $1, $1, 1 - $1 <- $1 + 1, string position ++
- --
- --insn_31 : noop - avoid data hazard, which is RAW
- --insn_32 : noop - avoid data hazard, which is RAW
- --
- --insn_33 : sub $1, $9, $1 - $1 <- $1 - $9, back to previous position, prevent "AABB"
- --insn_34 : addi $9, $0, 0 - $9 <- $0 + 0, reset the value of $9
- --insn_35 : beq loop1, $0, $0 - jump to loop1
- --
- --insn_36 : loop6: load $5, $0, 2 - load 2($0), which is count number into $5 at first for real time
- --
- --insn_37 noop - avoid data hazard, which is WAW
- --insn_38 noop - avoid data hazard, which is WAW
- --
- --insn_39 addi $5, $5, 1 - $5 <- $5 + 1, count ++
- --
- --insn_40 : noop - avoid data hazard, which is RAW
- --insn_41 : noop - avoid data hazard, which is RAW
- --
- --insn_42 : store $5, $0, 2 - store data $5 into 2($0) for real time
- --insn_43 : addi $9, $0, 0 - $9 <- $0 + 0, reset the value of $9
- --insn_44 : beq loop1, $0, $0 - jump to loop1
- --
- --insn_45 : end: noop - end of program
- --insn_46 - insn_63 : noop
- -- 12 decimal to Hex: 12-C; 13-D; 14-E
- --rs|rt|rd
- var_insn_mem(0) := X"40000146";
- var_insn_mem(1) := X"40000203";
- var_insn_mem(2) := X"10000401";
- var_insn_mem(3) := X"40000500";
- var_insn_mem(4) := X"40000600";
- var_insn_mem(5) := X"40000900";
- var_insn_mem(6) := X"10010700";
- var_insn_mem(7) := X"50040000";
- var_insn_mem(8) := X"00000000";
- var_insn_mem(9) := X"00000000";
- var_insn_mem(10) := X"60070A0C";
- var_insn_mem(11) := X"5000002D";
- var_insn_mem(12) := X"40000203";
- var_insn_mem(13) := X"40000600";
- var_insn_mem(14) := X"00000000";
- var_insn_mem(15) := X"00000000";
- var_insn_mem(16) := X"60060412";
- var_insn_mem(17) := X"50060424";
- var_insn_mem(18) := X"80000000";
- var_insn_mem(19) := X"10010700";
- var_insn_mem(20) := X"10020800";
- var_insn_mem(21) := X"00000000";
- var_insn_mem(22) := X"00000000";
- var_insn_mem(23) := X"50070819";
- var_insn_mem(24) := X"6007081E";
- var_insn_mem(25) := X"40010101";
- var_insn_mem(26) := X"40020201";
- var_insn_mem(27) := X"40060601";
- var_insn_mem(28) := X"40090901";
- var_insn_mem(29) := X"50000010";
- var_insn_mem(30) := X"40010101";
- var_insn_mem(31) := X"00000000";
- var_insn_mem(32) := X"00000000";
- var_insn_mem(33) := X"70010901";
- var_insn_mem(34) := X"40000900";
- var_insn_mem(35) := X"5000000A";
- var_insn_mem(36) := X"10000502";
- var_insn_mem(37) := X"00000000";
- var_insn_mem(38) := X"00000000";
- var_insn_mem(39) := X"40050501";
- var_insn_mem(40) := X"00000000";
- var_insn_mem(41) := X"00000000";
- var_insn_mem(42) := X"20000502";
- var_insn_mem(43) := X"40000900";
- var_insn_mem(44) := X"5000000A";
- var_insn_mem(45) := X"00000000";
- var_insn_mem(46) := X"00000000";
- var_insn_mem(47) := X"00000000";
- var_insn_mem(48) := X"00000000";
- var_insn_mem(49) := X"00000000";
- var_insn_mem(50) := X"00000000";
- var_insn_mem(51) := X"00000000";
- var_insn_mem(52) := X"00000000";
- var_insn_mem(53) := X"00000000";
- var_insn_mem(54) := X"00000000";
- var_insn_mem(55) := X"00000000";
- var_insn_mem(56) := X"00000000";
- var_insn_mem(57) := X"00000000";
- var_insn_mem(58) := X"00000000";
- var_insn_mem(59) := X"00000000";
- var_insn_mem(60) := X"00000000";
- var_insn_mem(61) := X"00000000";
- var_insn_mem(62) := X"00000000";
- var_insn_mem(63) := X"00000000";
- elsif (rising_edge(clk)) then
- -- read instructions on the rising clock edge
- var_addr := conv_integer(addr_in);
- insn_out <= var_insn_mem(var_addr);
- end if;
- -- the following are probe signals (for simulation purpose)
- sig_insn_mem <= var_insn_mem;
- end process;
- end behavioral;
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