module register(
	clk,
	irq_port,
	data_o,
	read_i,
	check);

input 	clk;
input	read_i;
output reg irq_port;
output reg check;
output reg [31:0] data_o;


reg [1:0] state;
reg toread;

parameter IDLE = 0, DATA = 1, READING = 2;
always @ (state)
begin
	case(state)
		IDLE:
		begin
			data_o = 32'h0000;
			irq_port = 1'b0;
		end

		DATA:
		begin
			irq_port = 1'b1;
			data_o = 32'h1234;
		end

		READING:
		begin
			irq_port = 1'b0;
		end
	endcase
end

always @ (posedge clk)
begin
	case(state)
		IDLE:
		begin
			if (clk) begin
				state = DATA;
			end
		end

		DATA:
		begin
			if(clk) begin
				if(toread==1)
				begin
				state = READING;
				end
			end
		end

		READING:
		begin
			if (clk) begin
				state = IDLE;
			end
		end
		default:
		begin
			state=IDLE;
		end

	endcase
end

always @ (negedge read_i)
begin

	case(toread)
		0:
		begin
			toread=1;
		end
		1:
		begin
			toread=0;
		end
		default:
		begin
			toread=0;
		end
	endcase
check<=toread;
end


endmodule