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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity halfadder is
- port(a, b: in bit;
- s, c: out bit);
- end halfadder;
- architecture DATAFLOW of halfadder is
- begin
- s <= A xor B;
- c <= A and B;
- end DATAFLOW;
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