multiplekser

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplekser is
Port(U:in STD_LOGIC;
		clk10: in STD_LOGIC;
		clk1:in STD_LOGIC;
		Sl:in STD_LOGIC;
		U10:in STD_LOGIC;
		x:out STD_LOGIC);
	end multiplekser;
architecture multi of multiplekser is
begin
process(Sl,U10)
begin
	if (Sl ='1' and U10='0')
	then
	x<=U;
	else if
	(Sl='0' and U10='1')
	then
	x<=clk10;
	else
	X<=clk1;
	end if;
	end if;
	end process;
	end multi;