----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    12:41:42 04/01/2019
-- Design Name:
-- Module Name:    reader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reader is
port(
	clk_i : in std_logic;
	rst_i : in std_logic;
	RXD_i : in std_logic;
	digit_o : out std_logic_vector(31 downto 0) := (others => '1')
);
end reader;

architecture Behavioral of reader is

signal counter : integer := 0;
signal can_read : std_logic := '0';
signal reading : std_logic := '0';
signal buffor : std_logic_vector(7 downto 0);
signal index : integer := 0;

type Digits is array (0 to 15) of std_logic_vector(6 downto 0);
signal dig : Digits:=
		(	"0000001",
			"1001111",
			"0010010",
			"0000110",
			"1001100",
			"0100100",
			"0100000",
			"0001111",
			"0000000",
			"0000100",
			"0001000",
			"1100000",
			"0110001",
			"1000010",
			"0110000",
			"0111000"
		);

signal N : integer := 5208;

begin

process(clk_i, rst_i)
begin
	if(rst_i = '1') then
        	digit_o <= (others => '1');
	elsif(rising_edge(clk_i)) then

		if(counter < N) then
			counter <= counter + 1;
		else
			counter <= 0;
			can_read <= '1';
		end if;

		if( can_read = '1') then
			can_read <= '0';
			if(RXD_i = '0' and reading = '0') then
				reading <= '1';
			elsif(reading = '1' and index < 8) then
				buffor(index) <= RXD_i;
				index <= index + 1;
			elsif(reading = '1' and index >= 8) then
				digit_o(23 downto 17) <= dig(to_integer(unsigned(buffor(7 downto 4))));
				digit_o(15 downto 9) <= dig(to_integer(unsigned(buffor(3 downto 0))));
				index <= 0;
				if(RXD_i = '1') then
					reading <= '0';
				end if;
			end if;
		end if;
	end if;

end process;

end Behavioral;



----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    13:08:44 03/11/2019
-- Design Name:
-- Module Name:    led_mod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led_mod is
	port(
		clk_i: in std_logic;
		rst_i: in std_logic;
		digit_i: in std_logic_vector(31 downto 0);
		led7_an_o: out std_logic_vector( 3 downto 0);
		led7_seg_o: out std_logic_vector( 7 downto 0)
		);
end led_mod;

architecture Behavioral of led_mod is

constant clock: integer:= 50000;
signal counter: integer:= 0;
signal active: integer := 0;

begin

    with active select
    led7_an_o <= "0111" when 0,
                 "1011" when 1,
                 "1101" when 2,
                 "1110" when 3,
                 "1111" when others;

	with active select
	led7_seg_o <= digit_i(31 downto 24) when 0,
					 digit_i(23 downto 16) when 1,
						 digit_i(15 downto 8) when 2,
						 digit_i(7 downto 0) when 3,
						 "11111111" when others;

    process(clk_i,rst_i)
	 begin
		  if(rst_i = '1') then
			  active<=4;
        elsif rising_edge(clk_i)  then
				if(counter < clock) then
					counter <= counter+1;
				else
					counter<=0;
					if(active = 3 or active = 4) then
						 active<= 0;
					else
						active <= active + 1;
					end if;
				end if;
        end if;
    end process;

end Behavioral;