library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY FA IS PORT(
	a: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	b: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	cin: IN STD_LOGIC;
	r: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	cout: OUT STD_LOGIC
);
END FA;

ARCHITECTURE arch OF FA IS

BEGIN
cout <=( (a(0) and b(0)) or
	(b(1) and b(0) and cin) or
	(a(1) and a(0) and b(1)) or
	(a(1) and b(0) and cin) or
	(a(1) and a(0) and cin) or
	(a(1) and b(1) and b(0)) or
	(a(0) and b(1) and cin)
) after 10 ns;


r(1) <=((not a(1) and b(1) and not cin) or
	(not a(1) and not b(1) and cin) or
	(a(1) and not b(1) and not cin) or
	( a(1) and b(1) and cin)
) after 10 ns;



r(0) <=( (not a(0) and b(1) and not b(0) and cin) or
	(not a(1) and not a(0) and b(0) and not cin) or
	(a(1) and a(0) and b(1) and b(0) ) or
	(a(1) and not a(0) and not b(0) and cin) or
	(not a(0) and not b(1) and b(0) and not cin) or
	(a(1) and a(0) and b(0) and cin) or
	(a(1) and not a(0) and b(1) and not b(0)) or
	(not a(1) and not a(0) and not b(1) and b(0)) or
	(a(0) and not b(1) and not b(0) and not cin) or
	(not a(1) and a(0) and not b(1) and not b(0)) or
	(a(0) and b(1) and b(0) and cin) or
	(not a(1) and a(0) and not b(0) and not cin)
) after 10 ns;
END arch;