; atmega328p specifics begin (see m238Pdef.inc)
.equ RAMEND, 0x8ff ; highest ram address
.equ SREG, 0x3f   ; cpu status register
.equ SPL, 0x3d    ; stack pointer low byte
.equ SPH, 0x3e    ; stack pointer high byte

#define XH r27    ; x pointer reg
#define XL r26
#define YH r29    ; y pointer reg
#define YL r28
#define ZH r31    ; z pointer reg
#define ZL r30

; ***** CPU **************************
; SREG - Status Register
.equ    SREG_C, 0   ; Carry Flag
.equ    SREG_Z, 1   ; Zero Flag
.equ    SREG_N, 2   ; Negative Flag
.equ    SREG_V, 3   ; Two's Complement Overflow Flag
.equ    SREG_S, 4   ; Sign Bit
.equ    SREG_H, 5   ; Half Carry Flag
.equ    SREG_T, 6   ; Bit Copy Storage
.equ    SREG_I, 7   ; Global Interrupt Enable

;USART register addresses
.equ    UDR0, 0xc6
.equ    UBRR0L, 0xc4
.equ    UBRR0H, 0xc5
.equ    UCSR0C, 0xc2
.equ    UCSR0B, 0xc1
.equ    UCSR0A, 0xc0


; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
.equ    UDR0_0, 0   ; USART I/O Data Register bit 0
.equ    UDR0_1, 1   ; USART I/O Data Register bit 1
.equ    UDR0_2, 2   ; USART I/O Data Register bit 2
.equ    UDR0_3, 3   ; USART I/O Data Register bit 3
.equ    UDR0_4, 4   ; USART I/O Data Register bit 4
.equ    UDR0_5, 5   ; USART I/O Data Register bit 5
.equ    UDR0_6, 6   ; USART I/O Data Register bit 6
.equ    UDR0_7, 7   ; USART I/O Data Register bit 7

; UCSR0A - USART Control and Status Register A
.equ    MPCM0, 0    ; Multi-processor Communication Mode
.equ    U2X0, 1 ; Double the USART transmission speed
.equ    UPE0, 2 ; Parity Error
.equ    DOR0, 3 ; Data overRun
.equ    FE0, 4  ; Framing Error
.equ    UDRE0, 5    ; USART Data Register Empty
.equ    TXC0, 6 ; USART Transmitt Complete
.equ    RXC0, 7 ; USART Receive Complete

; UCSR0B - USART Control and Status Register B
.equ    TXB80, 0    ; Transmit Data Bit 8
.equ    RXB80, 1    ; Receive Data Bit 8
.equ    UCSZ02, 2   ; Character Size
.equ    TXEN0, 3    ; Transmitter Enable
.equ    RXEN0, 4    ; Receiver Enable
.equ    UDRIE0, 5   ; USART Data register Empty Interrupt Enable
.equ    TXCIE0, 6   ; TX Complete Interrupt Enable
.equ    RXCIE0, 7   ; RX Complete Interrupt Enable

; UCSR0C - USART Control and Status Register C
.equ    UCPOL0, 0   ; Clock Polarity
.equ    UCSZ00, 1   ; Character Size
.equ    UCPHA0, UCSZ00  ; For compatibility
.equ    UCSZ01, 2   ; Character Size
.equ    UDORD0, UCSZ01  ; For compatibility
.equ    USBS0, 3    ; Stop Bit Select
.equ    UPM00, 4    ; Parity Mode Bit 0
.equ    UPM01, 5    ; Parity Mode Bit 1
.equ    UMSEL00, 6  ; USART Mode Select
.equ    UMSEL0, UMSEL00 ; For compatibility
.equ    UMSEL01, 7  ; USART Mode Select
.equ    UMSEL1, UMSEL01 ; For compatibility

; UBRR0H - USART Baud Rate Register High Byte
.equ    UBRR8, 0    ; USART Baud Rate Register bit 8
.equ    UBRR9, 1    ; USART Baud Rate Register bit 9
.equ    UBRR10, 2   ; USART Baud Rate Register bit 10
.equ    UBRR11, 3   ; USART Baud Rate Register bit 11

; UBRR0L - USART Baud Rate Register Low Byte
.equ    _UBRR0, 0   ; USART Baud Rate Register bit 0
.equ    _UBRR1, 1   ; USART Baud Rate Register bit 1
.equ    UBRR2, 2    ; USART Baud Rate Register bit 2
.equ    UBRR3, 3    ; USART Baud Rate Register bit 3
.equ    UBRR4, 4    ; USART Baud Rate Register bit 4
.equ    UBRR5, 5    ; USART Baud Rate Register bit 5
.equ    UBRR6, 6    ; USART Baud Rate Register bit 6
.equ    UBRR7, 7    ; USART Baud Rate Register bit 7

; atmega328p specifics end
.org 0
   rjmp main

 main:
    ; reset system status
    ldi r16,0
    out SREG,r16

    ; init stack pointer
    ldi r16,lo8(RAMEND)
    out SPL,r16
    ldi r16,hi8(RAMEND)
    out SPH,r16

    rcall init_uart
    rjmp mainloop

init_uart:
  ; set baud rate 1 Mbps
  ldi r16, 1<<U2X0
  sts UCSR0A, r16
  ldi r16, 0
  sts UBRR0H, r16
  ldi r16, 1
  sts UBRR0L, r16

  ; enable receive and transmit, without interrupts
  ldi r16, (1<<RXEN0)|(1<<TXEN0)
  sts UCSR0B,r16

  ; frame format: 8 data bits, 1 stop bit, no parity.
  ldi r16, (1<<UCSZ01)|(1<<UCSZ00)
  sts UCSR0C,r16

  ret

; sends one byte over the serial line.
; data must reside in r17.
send_byte:
  ; wait for UDR to become empty
  lds r16, UCSR0A
  sbrs r16, UDRE0
  rjmp send_byte

  ; write data to transmit register
  sts UDR0, R17

  ret

; 3M cycle delay (~ 0.19s)
wait:
  ldi r21,0x10
  ldi r22,0x00
  ldi r23,0x00

_wait_loop:
  dec r23
  brne _wait_loop
  dec r22
  brne _wait_loop
  dec r21
  brne _wait_loop

  ret

mainloop:
  ldi r17, 'H'
  call send_byte
  ldi r17, 'e'
  call send_byte
  ldi r17, 'l'
  call send_byte
  ldi r17, 'l'
  call send_byte
  ldi r17, 'o'
  call send_byte
  ldi r17, '!'
  call send_byte

  call wait

  rjmp mainloop