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- module test(input clk,
- input reset,
- output reg[3:0] ledss
- );
- integer i=0;
- wire[31:0] dataread;
- reg[31:0] datawrite=0;
- reg wren=0;
- reg[31:0] address=0;
- ramm ram(.address(address),
- .clock(clk),
- .data(datawrite),
- .wren(wren),
- .q(dataread)
- ); //
- always @(posedge clk )
- begin
- if(i==2)
- begin
- case(dataread)
- 32'b11111111111111111111111111111111:ledss<=4'b0110;
- endcase
- end
- if(i!=3)
- i=i+1;
- end
- endmodule
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