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- /*
- * cstart.S
- *
- * Initial code to get Neutrino started
- *
- * This code runs as the first instructions after control has transferred
- * from any bootup monitor. This module defines a minimal bootup stack,
- * and sets SP to this stack, and then starts running C code in _main().
- */
- .data
- .globl stack
- .globl boot_args
- .globl vstart
- boot_args:
- .ascii "ddpvbskr" /* signature for mkifs */
- stack_end:
- .space 3*1024
- stack:
- .text
- .extern _main
- .globl _start
- _start:
- //
- // Turn off interrupts and make sure we are in SVC mode
- //
- mrs lr, cpsr
- bic lr, lr, #0x1f
- orr lr, lr, #0xd3
- msr cpsr, lr
- //
- // Turn off MMU and data cache if necessary.
- // WARNING: assumes we are running with a 1-1 mapping if MMU is enabled.
- //
- mrc p15, 0, lr, c1, c0, 0
- bic lr, lr, #0x0000000f // WCAM bits
- bic lr, lr, #0x00000300 // RS bits
- mcr p15, 0, lr, c1, c0, 0
- mov r0, #0
- mov r0, r0
- mov r0, r0
- //
- // Set the translation table base
- //
- ldr r0, =_arm_board_ttb // set start of Translation Table base
- orr r0, r0, #((3 << 3) | 3)
- mcr p15, 0, r0, c2, c0, 0
- # mcr p15, 0, r0, c2, c0, 1 // set TTBR1 so armv_setup_v7 works
- /* Enable the MMU, I-Cache and D-Cache */
- mrc p15, 0, r0, c1, c0, 0
- BIC r0, r0, #(1 << 12) // enable I Cache
- BIC r0, r0, #(1 << 2) // enable D Cache
- BIC r0, r0, #(1 << 0) // enable MMU
- mcr p15, 0, r0, c1, c0, 0
- ldr sp, =stack
- bl _main
- oops:
- b oops
- /*
- * void vstart(uintptr_t syspageptr, unsigned entry_point, unsigned cpunum)
- *
- * Enable the mmu and jump to the next program's entry point
- * The next program is responsible for tearing down the 1-1 section
- * mapping of the startup program set up by init_mmu().
- */
- vstart:
- /* SAVE CONTEXT OF REGISTERS */
- mov r4, r1
- mov r5, r2
- //
- // Invalidate L1 I/D
- //
- mcr p15, 0, ip, c8, c7, 0 // Invalidate entire unified TLB
- mcr p15, 0, ip, c8, c6, 0 // Invalidate entire data TLB
- mcr p15, 0, ip, c8, c5, 0 // Invalidate entire instruction TLB
- dsb
- isb
- mcr p15, 0, ip, c7, c5, 0 // invalidate icache
- mcr p15, 0, ip, c7, c5, 6 // invalidate BP array
- dsb
- isb
- //
- // Fluch D-cache
- //
- bl _armv7_flush_whole_dcache
- /*
- * Set the translation table base
- */
- ldr ip, =L1_paddr
- ldr ip, [ip]
- add ip, ip, r5, lsl #14 // L1_paddr * (cpu * ARM_L1_SIZE)
- mcr p15, 0, ip, c2, c0, 0 // TTBR0
- mcr p15, 0, ip, c2, c0, 1 // TTBR1
- mov ip, #1
- mcr p15, 0, ip, c2, c0, 2 // TTBCR = 1
- /*
- * Enable MMU domain 0
- */
- mov ip, #1
- mcr p15, 0, ip, c3, c0, 0
- /*
- * Enable the MMU, using read-modify-write to preserve reserved bits.
- */
- ldr r2, =mmu_cr_clr
- ldr r3, =mmu_cr_set
- ldr r2, [r2]
- ldr r3, [r3]
- mrc p15, 0, lr, c1, c0, 0
- bic ip, lr, r2
- orr ip, ip, r3
- dsb
- isb
- mcr p15, 0, ip, c1, c0, 0
- dsb
- isb
- mov ip, #0
- /*
- * Invalidate the caches and TLBs
- */
- .align 5
- mcr p15, 0, ip, c7, c5, 0 // invalidate instruction caches
- mcr p15, 0, ip, c8, c7, 0 // invalidate TLBs
- dsb
- isb
- /*
- * Call entry_point(_syspage_ptr, cpunum)
- */
- /* RESTORE CONTEXT OF REGISTERS */
- mov r1, r5
- mov pc, r4
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