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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer: krzys_h
- //
- // Create Date: 21:35:34 07/28/2019
- // Design Name:
- // Module Name: helloWorld
- // Project Name:
- // Target Devices:
- // Tool versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module uart_tx #(parameter baudrate = 9600, parameter clock_rate = 100000000) (
- output reg tx,
- input [7:0] data,
- input do_send,
- output reg done_send,
- input CLK
- );
- localparam clks_per_bit = clock_rate / baudrate;
- localparam counter_len = 32; // $clog2(clks_per_bit)
- localparam STATE_IDLE = 0;
- localparam STATE_STARTBIT = 1;
- localparam STATE_DATA = 2;
- localparam STATE_STOPBIT = 3;
- reg [7:0] send_buffer;
- reg [1:0] state = STATE_IDLE;
- reg [2:0] current_bit;
- reg [counter_len:0] clock_counter;
- always @(posedge CLK)
- begin
- case(state)
- STATE_IDLE:
- begin
- tx <= 1;
- done_send <= 0;
- if (do_send)
- begin
- send_buffer <= data;
- clock_counter <= 0;
- state <= STATE_STARTBIT;
- end
- end
- STATE_STARTBIT:
- begin
- tx <= 0;
- if (clock_counter < clks_per_bit)
- begin
- clock_counter <= clock_counter + 1;
- end
- else
- begin
- clock_counter <= 0;
- current_bit <= 0;
- state <= STATE_DATA;
- end
- end
- STATE_DATA:
- begin
- tx <= send_buffer[current_bit];
- if (clock_counter < clks_per_bit)
- begin
- clock_counter <= clock_counter + 1;
- end
- else
- begin
- clock_counter <= 0;
- if (current_bit == 7)
- state <= STATE_STOPBIT;
- else
- current_bit <= current_bit + 1;
- end
- end
- STATE_STOPBIT:
- begin
- tx <= 1;
- if (clock_counter < clks_per_bit)
- begin
- clock_counter <= clock_counter + 1;
- end
- else
- begin
- state <= STATE_IDLE;
- done_send <= 1;
- end
- end
- endcase
- end
- endmodule
- module helloWorld(
- output [3:3] IO_P1,
- input CLK
- );
- reg [31:0] counter = 0;
- reg [7:0] num = 0;
- parameter [7:0] str[0:13] = "Hello world!\r\n";
- reg do_send = 1;
- uart_tx tx(
- .tx(IO_P1[3]),
- .CLK(CLK),
- .data(str[num]),
- .do_send(do_send),
- .done_send(done_send)
- );
- always @(posedge CLK)
- begin
- if (counter == 100000000)
- begin
- counter <= 0;
- num <= 0;
- do_send <= 1;
- end
- else
- counter <= counter + 1;
- if (do_send)
- begin
- do_send <= 0;
- end
- if (done_send)
- begin
- if (num != 13)
- begin
- do_send <= 1;
- num <= num + 1;
- end
- else
- begin
- do_send <= 0;
- end
- end
- end
- endmodule
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