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OPi PC 2 running 'Debian server'

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Nov 14th, 2016
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  1. root@Orangepi:/boot/orangepi# df -h
  2. Filesystem Size Used Avail Use% Mounted on
  3. /dev/mmcblk0p2 1.1G 381M 628M 38% /
  4. devtmpfs 482M 0 482M 0% /dev
  5. tmpfs 490M 0 490M 0% /dev/shm
  6. tmpfs 490M 6.5M 484M 2% /run
  7. tmpfs 5.0M 4.0K 5.0M 1% /run/lock
  8. tmpfs 490M 0 490M 0% /sys/fs/cgroup
  9. /dev/mmcblk0p1 50M 13M 38M 26% /boot
  10. root@Orangepi:/boot/orangepi# cat /etc/mtab
  11. rootfs / rootfs rw 0 0
  12. /dev/mmcblk0p2 / ext4 rw,noatime,stripe=1024,data=ordered 0 0
  13. sysfs /sys sysfs rw,nosuid,nodev,noexec,relatime 0 0
  14. proc /proc proc rw,nosuid,nodev,noexec,relatime 0 0
  15. devtmpfs /dev devtmpfs rw,nosuid,size=492596k,nr_inodes=123149,mode=755 0 0
  16. securityfs /sys/kernel/security securityfs rw,nosuid,nodev,noexec,relatime 0 0
  17. selinuxfs /sys/fs/selinux selinuxfs rw,relatime 0 0
  18. tmpfs /dev/shm tmpfs rw,nosuid,nodev 0 0
  19. devpts /dev/pts devpts rw,nosuid,noexec,relatime,gid=5,mode=620,ptmxmode=000 0 0
  20. tmpfs /run tmpfs rw,nosuid,nodev,mode=755 0 0
  21. tmpfs /run/lock tmpfs rw,nosuid,nodev,noexec,relatime,size=5120k 0 0
  22. tmpfs /sys/fs/cgroup tmpfs ro,nosuid,nodev,noexec,mode=755 0 0
  23. cgroup /sys/fs/cgroup/systemd cgroup rw,nosuid,nodev,noexec,relatime,xattr,release_agent=/lib/systemd/systemd-cgroups-agent,name=systemd 0 0
  24. pstore /sys/fs/pstore pstore rw,nosuid,nodev,noexec,relatime 0 0
  25. cgroup /sys/fs/cgroup/cpuset cgroup rw,nosuid,nodev,noexec,relatime,cpuset 0 0
  26. cgroup /sys/fs/cgroup/debug cgroup rw,nosuid,nodev,noexec,relatime,debug 0 0
  27. cgroup /sys/fs/cgroup/cpu,cpuacct cgroup rw,nosuid,nodev,noexec,relatime,cpuacct,cpu 0 0
  28. cgroup /sys/fs/cgroup/freezer cgroup rw,nosuid,nodev,noexec,relatime,freezer 0 0
  29. debugfs /sys/kernel/debug debugfs rw,relatime 0 0
  30. configfs /sys/kernel/config configfs rw,relatime 0 0
  31. fusectl /sys/fs/fuse/connections fusectl rw,relatime 0 0
  32. /dev/mmcblk0p1 /boot vfat rw,relatime,fmask=0022,dmask=0022,codepage=437,iocharset=iso8859-1,shortname=mixed,errors=remount-ro 0 0
  33. root@Orangepi:/boot/orangepi# uname -a
  34. Linux Orangepi 3.10.65 #31 SMP PREEMPT Mon Nov 14 09:31:54 CST 2016 aarch64 GNU/Linux
  35. root@Orangepi:/boot/orangepi# cat OrangePiH5orangepi.dts
  36. /dts-v1/;
  37.  
  38. /memreserve/ 0x0000000040020000 0x0000000000000800;
  39. /memreserve/ 0x0000000048000000 0x0000000001000000;
  40. /memreserve/ 0x0000000048100000 0x0000000000004000;
  41. /memreserve/ 0x0000000048104000 0x0000000000001000;
  42. /memreserve/ 0x0000000048105000 0x0000000000001000;
  43. / {
  44. model = "sun50iw2";
  45. compatible = "arm,sun50iw2p1";
  46. interrupt-parent = <0x1>;
  47. #address-cells = <0x2>;
  48. #size-cells = <0x2>;
  49.  
  50. clocks {
  51. compatible = "allwinner,sunxi-clk-init";
  52. device_type = "clocks";
  53. #address-cells = <0x2>;
  54. #size-cells = <0x2>;
  55. ranges;
  56. reg = <0x0 0x1c20000 0x0 0x324 0x0 0x1f01400 0x0 0x1d4 0x0 0x1f00060 0x0 0x4>;
  57.  
  58. losc {
  59. #clock-cells = <0x0>;
  60. compatible = "allwinner,fixed-clock";
  61. clock-frequency = <0x8000>;
  62. clock-output-names = "losc";
  63. linux,phandle = <0xb>;
  64. phandle = <0xb>;
  65. };
  66.  
  67. iosc {
  68. #clock-cells = <0x0>;
  69. compatible = "allwinner,fixed-clock";
  70. clock-frequency = <0xf42400>;
  71. clock-output-names = "iosc";
  72. linux,phandle = <0xc>;
  73. phandle = <0xc>;
  74. };
  75.  
  76. hosc {
  77. #clock-cells = <0x0>;
  78. compatible = "allwinner,fixed-clock";
  79. clock-frequency = <0x16e3600>;
  80. clock-output-names = "hosc";
  81. linux,phandle = <0x6>;
  82. phandle = <0x6>;
  83. };
  84.  
  85. pll_cpu {
  86. #clock-cells = <0x0>;
  87. compatible = "allwinner,sunxi-pll-clock";
  88. lock-mode = "none";
  89. clock-output-names = "pll_cpu";
  90. };
  91.  
  92. pll_audio {
  93. #clock-cells = <0x0>;
  94. compatible = "allwinner,sunxi-pll-clock";
  95. lock-mode = "none";
  96. assigned-clock-rates = <0x1770000>;
  97. clock-output-names = "pll_audio";
  98. linux,phandle = <0x2>;
  99. phandle = <0x2>;
  100. };
  101.  
  102. pll_video {
  103. #clock-cells = <0x0>;
  104. compatible = "allwinner,sunxi-pll-clock";
  105. lock-mode = "none";
  106. assigned-clock-rates = <0x11b3dc40>;
  107. clock-output-names = "pll_video";
  108. linux,phandle = <0x3>;
  109. phandle = <0x3>;
  110. };
  111.  
  112. pll_ve {
  113. #clock-cells = <0x0>;
  114. compatible = "allwinner,sunxi-pll-clock";
  115. device_type = "clk_pll_ve";
  116. lock-mode = "none";
  117. assigned-clock-rates = <0x1908b100>;
  118. clock-output-names = "pll_ve";
  119. linux,phandle = <0x15>;
  120. phandle = <0x15>;
  121. };
  122.  
  123. pll_ddr {
  124. #clock-cells = <0x0>;
  125. compatible = "allwinner,sunxi-pll-clock";
  126. lock-mode = "none";
  127. clock-output-names = "pll_ddr";
  128. linux,phandle = <0x99>;
  129. phandle = <0x99>;
  130. };
  131.  
  132. pll_periph0 {
  133. #clock-cells = <0x0>;
  134. compatible = "allwinner,sunxi-pll-clock";
  135. lock-mode = "none";
  136. clock-output-names = "pll_periph0";
  137. linux,phandle = <0x4>;
  138. phandle = <0x4>;
  139. };
  140.  
  141. pll_periph1 {
  142. #clock-cells = <0x0>;
  143. compatible = "allwinner,sunxi-pll-clock";
  144. lock-mode = "none";
  145. clock-output-names = "pll_periph1";
  146. linux,phandle = <0x5>;
  147. phandle = <0x5>;
  148. };
  149.  
  150. pll_gpu {
  151. #clock-cells = <0x0>;
  152. compatible = "allwinner,sunxi-pll-clock";
  153. lock-mode = "none";
  154. clock-output-names = "pll_gpu";
  155. linux,phandle = <0x9b>;
  156. phandle = <0x9b>;
  157. };
  158.  
  159. pll_de {
  160. #clock-cells = <0x0>;
  161. compatible = "allwinner,sunxi-pll-clock";
  162. lock-mode = "none";
  163. assigned-clock-rates = <0x337f9800>;
  164. clock-output-names = "pll_de";
  165. linux,phandle = <0x7>;
  166. phandle = <0x7>;
  167. };
  168.  
  169. pll_audiox8 {
  170. #clock-cells = <0x0>;
  171. compatible = "allwinner,fixed-factor-clock";
  172. clocks = <0x2>;
  173. clock-mult = <0x8>;
  174. clock-div = <0x1>;
  175. clock-output-names = "pll_audiox8";
  176. };
  177.  
  178. pll_audiox4 {
  179. #clock-cells = <0x0>;
  180. compatible = "allwinner,fixed-factor-clock";
  181. clocks = <0x2>;
  182. clock-mult = <0x8>;
  183. clock-div = <0x2>;
  184. clock-output-names = "pll_audiox4";
  185. };
  186.  
  187. pll_audiox2 {
  188. #clock-cells = <0x0>;
  189. compatible = "allwinner,fixed-factor-clock";
  190. clocks = <0x2>;
  191. clock-mult = <0x8>;
  192. clock-div = <0x4>;
  193. clock-output-names = "pll_audiox2";
  194. };
  195.  
  196. pll_videox2 {
  197. #clock-cells = <0x0>;
  198. compatible = "allwinner,fixed-factor-clock";
  199. clocks = <0x3>;
  200. clock-mult = <0x2>;
  201. clock-div = <0x1>;
  202. clock-output-names = "pll_videox2";
  203. };
  204.  
  205. pll_periph0x2 {
  206. #clock-cells = <0x0>;
  207. compatible = "allwinner,fixed-factor-clock";
  208. clocks = <0x4>;
  209. clock-mult = <0x2>;
  210. clock-div = <0x1>;
  211. clock-output-names = "pll_periph0x2";
  212. };
  213.  
  214. pll_periph1x2 {
  215. #clock-cells = <0x0>;
  216. compatible = "allwinner,fixed-factor-clock";
  217. clocks = <0x5>;
  218. clock-mult = <0x2>;
  219. clock-div = <0x1>;
  220. clock-output-names = "pll_periph1x2";
  221. linux,phandle = <0x53>;
  222. phandle = <0x53>;
  223. };
  224.  
  225. pll_periph0d2 {
  226. #clock-cells = <0x0>;
  227. compatible = "allwinner,fixed-factor-clock";
  228. clocks = <0x4>;
  229. clock-mult = <0x1>;
  230. clock-div = <0x2>;
  231. clock-output-names = "pll_periph0d2";
  232. };
  233.  
  234. hoscd2 {
  235. #clock-cells = <0x0>;
  236. compatible = "allwinner,fixed-factor-clock";
  237. clocks = <0x6>;
  238. clock-mult = <0x1>;
  239. clock-div = <0x2>;
  240. clock-output-names = "hoscd2";
  241. };
  242.  
  243. hoscx2 {
  244. #clock-cells = <0x0>;
  245. compatible = "allwinner,fixed-factor-clock";
  246. clocks = <0x6>;
  247. clock-mult = <0x2>;
  248. clock-div = <0x1>;
  249. clock-output-names = "hoscx2";
  250. };
  251.  
  252. cpu {
  253. #clock-cells = <0x0>;
  254. compatible = "allwinner,sunxi-periph-clock";
  255. clock-output-names = "cpu";
  256. };
  257.  
  258. cpuapb {
  259. #clock-cells = <0x0>;
  260. compatible = "allwinner,sunxi-periph-clock";
  261. clock-output-names = "cpuapb";
  262. };
  263.  
  264. axi {
  265. #clock-cells = <0x0>;
  266. compatible = "allwinner,sunxi-periph-clock";
  267. clock-output-names = "axi";
  268. };
  269.  
  270. pll_periphahb0 {
  271. #clock-cells = <0x0>;
  272. compatible = "allwinner,sunxi-periph-clock";
  273. clock-output-names = "pll_periphahb0";
  274. };
  275.  
  276. ahb1 {
  277. #clock-cells = <0x0>;
  278. assigned-clock-rates = <0xbebc200>;
  279. compatible = "allwinner,sunxi-periph-clock";
  280. clock-output-names = "ahb1";
  281. linux,phandle = <0x9a>;
  282. phandle = <0x9a>;
  283. };
  284.  
  285. apb1 {
  286. #clock-cells = <0x0>;
  287. compatible = "allwinner,sunxi-periph-clock";
  288. clock-output-names = "apb1";
  289. };
  290.  
  291. apb2 {
  292. #clock-cells = <0x0>;
  293. compatible = "allwinner,sunxi-periph-clock";
  294. clock-output-names = "apb2";
  295. linux,phandle = <0x74>;
  296. phandle = <0x74>;
  297. };
  298.  
  299. ahb2 {
  300. #clock-cells = <0x0>;
  301. compatible = "allwinner,sunxi-periph-clock";
  302. clock-output-names = "ahb2";
  303. };
  304.  
  305. ths {
  306. #clock-cells = <0x0>;
  307. compatible = "allwinner,sunxi-periph-clock";
  308. clock-output-names = "ths";
  309. linux,phandle = <0x89>;
  310. phandle = <0x89>;
  311. };
  312.  
  313. nand {
  314. #clock-cells = <0x0>;
  315. compatible = "allwinner,sunxi-periph-clock";
  316. clock-output-names = "nand";
  317. linux,phandle = <0x7c>;
  318. phandle = <0x7c>;
  319. };
  320.  
  321. sdmmc0_mod {
  322. #clock-cells = <0x0>;
  323. compatible = "allwinner,sunxi-periph-clock";
  324. clock-output-names = "sdmmc0_mod";
  325. linux,phandle = <0x59>;
  326. phandle = <0x59>;
  327. };
  328.  
  329. sdmmc0_bus {
  330. #clock-cells = <0x0>;
  331. compatible = "allwinner,sunxi-periph-clock";
  332. clock-output-names = "sdmmc0_bus";
  333. linux,phandle = <0x5a>;
  334. phandle = <0x5a>;
  335. };
  336.  
  337. sdmmc0_rst {
  338. #clock-cells = <0x0>;
  339. compatible = "allwinner,sunxi-periph-clock";
  340. clock-output-names = "sdmmc0_rst";
  341. linux,phandle = <0x5b>;
  342. phandle = <0x5b>;
  343. };
  344.  
  345. sdmmc1_mod {
  346. #clock-cells = <0x0>;
  347. compatible = "allwinner,sunxi-periph-clock";
  348. clock-output-names = "sdmmc1_mod";
  349. linux,phandle = <0x5e>;
  350. phandle = <0x5e>;
  351. };
  352.  
  353. sdmmc1_bus {
  354. #clock-cells = <0x0>;
  355. compatible = "allwinner,sunxi-periph-clock";
  356. clock-output-names = "sdmmc1_bus";
  357. linux,phandle = <0x5f>;
  358. phandle = <0x5f>;
  359. };
  360.  
  361. sdmmc1_rst {
  362. #clock-cells = <0x0>;
  363. compatible = "allwinner,sunxi-periph-clock";
  364. clock-output-names = "sdmmc1_rst";
  365. linux,phandle = <0x60>;
  366. phandle = <0x60>;
  367. };
  368.  
  369. sdmmc2_mod {
  370. #clock-cells = <0x0>;
  371. compatible = "allwinner,sunxi-periph-clock";
  372. clock-output-names = "sdmmc2_mod";
  373. linux,phandle = <0x54>;
  374. phandle = <0x54>;
  375. };
  376.  
  377. sdmmc2_bus {
  378. #clock-cells = <0x0>;
  379. compatible = "allwinner,sunxi-periph-clock";
  380. clock-output-names = "sdmmc2_bus";
  381. linux,phandle = <0x55>;
  382. phandle = <0x55>;
  383. };
  384.  
  385. sdmmc2_rst {
  386. #clock-cells = <0x0>;
  387. compatible = "allwinner,sunxi-periph-clock";
  388. clock-output-names = "sdmmc2_rst";
  389. linux,phandle = <0x56>;
  390. phandle = <0x56>;
  391. };
  392.  
  393. ts {
  394. #clock-cells = <0x0>;
  395. compatible = "allwinner,sunxi-periph-clock";
  396. clock-output-names = "ts";
  397. linux,phandle = <0x80>;
  398. phandle = <0x80>;
  399. };
  400.  
  401. ce {
  402. #clock-cells = <0x0>;
  403. compatible = "allwinner,sunxi-periph-clock";
  404. clock-output-names = "ce";
  405. linux,phandle = <0x71>;
  406. phandle = <0x71>;
  407. };
  408.  
  409. spi0 {
  410. #clock-cells = <0x0>;
  411. compatible = "allwinner,sunxi-periph-clock";
  412. clock-output-names = "spi0";
  413. linux,phandle = <0x4b>;
  414. phandle = <0x4b>;
  415. };
  416.  
  417. spi1 {
  418. #clock-cells = <0x0>;
  419. compatible = "allwinner,sunxi-periph-clock";
  420. clock-output-names = "spi1";
  421. linux,phandle = <0x4f>;
  422. phandle = <0x4f>;
  423. };
  424.  
  425. i2s0 {
  426. #clock-cells = <0x0>;
  427. compatible = "allwinner,sunxi-periph-clock";
  428. clock-output-names = "i2s0";
  429. linux,phandle = <0x3b>;
  430. phandle = <0x3b>;
  431. };
  432.  
  433. i2s1 {
  434. #clock-cells = <0x0>;
  435. compatible = "allwinner,sunxi-periph-clock";
  436. clock-output-names = "i2s1";
  437. linux,phandle = <0x40>;
  438. phandle = <0x40>;
  439. };
  440.  
  441. i2s2 {
  442. #clock-cells = <0x0>;
  443. compatible = "allwinner,sunxi-periph-clock";
  444. clock-output-names = "i2s2";
  445. linux,phandle = <0x41>;
  446. phandle = <0x41>;
  447. };
  448.  
  449. spdif {
  450. #clock-cells = <0x0>;
  451. compatible = "allwinner,sunxi-periph-clock";
  452. clock-output-names = "spdif";
  453. linux,phandle = <0x42>;
  454. phandle = <0x42>;
  455. };
  456.  
  457. usbphy0 {
  458. #clock-cells = <0x0>;
  459. compatible = "allwinner,sunxi-periph-clock";
  460. clock-output-names = "usbphy0";
  461. linux,phandle = <0x2c>;
  462. phandle = <0x2c>;
  463. };
  464.  
  465. usbphy1 {
  466. #clock-cells = <0x0>;
  467. compatible = "allwinner,sunxi-periph-clock";
  468. clock-output-names = "usbphy1";
  469. linux,phandle = <0x30>;
  470. phandle = <0x30>;
  471. };
  472.  
  473. usbphy2 {
  474. #clock-cells = <0x0>;
  475. compatible = "allwinner,sunxi-periph-clock";
  476. clock-output-names = "usbphy2";
  477. linux,phandle = <0x33>;
  478. phandle = <0x33>;
  479. };
  480.  
  481. usbphy3 {
  482. #clock-cells = <0x0>;
  483. compatible = "allwinner,sunxi-periph-clock";
  484. clock-output-names = "usbphy3";
  485. linux,phandle = <0x36>;
  486. phandle = <0x36>;
  487. };
  488.  
  489. usbohci0 {
  490. #clock-cells = <0x0>;
  491. compatible = "allwinner,sunxi-periph-clock";
  492. clock-output-names = "usbohci0";
  493. linux,phandle = <0x2f>;
  494. phandle = <0x2f>;
  495. };
  496.  
  497. usbohci1 {
  498. #clock-cells = <0x0>;
  499. compatible = "allwinner,sunxi-periph-clock";
  500. clock-output-names = "usbohci1";
  501. linux,phandle = <0x32>;
  502. phandle = <0x32>;
  503. };
  504.  
  505. usbohci2 {
  506. #clock-cells = <0x0>;
  507. compatible = "allwinner,sunxi-periph-clock";
  508. clock-output-names = "usbohci2";
  509. linux,phandle = <0x35>;
  510. phandle = <0x35>;
  511. };
  512.  
  513. usbohci3 {
  514. #clock-cells = <0x0>;
  515. compatible = "allwinner,sunxi-periph-clock";
  516. clock-output-names = "usbohci3";
  517. linux,phandle = <0x38>;
  518. phandle = <0x38>;
  519. };
  520.  
  521. de {
  522. #clock-cells = <0x0>;
  523. compatible = "allwinner,sunxi-periph-clock";
  524. assigned-clock-parents = <0x7>;
  525. assigned-clock-rates = <0x19bfcc00>;
  526. clock-output-names = "de";
  527. linux,phandle = <0x63>;
  528. phandle = <0x63>;
  529. };
  530.  
  531. tcon0 {
  532. #clock-cells = <0x0>;
  533. compatible = "allwinner,sunxi-periph-clock";
  534. assigned-clock-parents = <0x3>;
  535. clock-output-names = "tcon0";
  536. linux,phandle = <0x64>;
  537. phandle = <0x64>;
  538. };
  539.  
  540. tcon1 {
  541. #clock-cells = <0x0>;
  542. compatible = "allwinner,sunxi-periph-clock";
  543. clock-output-names = "tcon1";
  544. linux,phandle = <0x65>;
  545. phandle = <0x65>;
  546. };
  547.  
  548. tve {
  549. #clock-cells = <0x0>;
  550. compatible = "allwinner,sunxi-periph-clock";
  551. assigned-clock-parents = <0x7>;
  552. clock-output-names = "tve";
  553. linux,phandle = <0x68>;
  554. phandle = <0x68>;
  555. };
  556.  
  557. deinterlace {
  558. #clock-cells = <0x0>;
  559. compatible = "allwinner,sunxi-periph-clock";
  560. clock-output-names = "deinterlace";
  561. linux,phandle = <0x72>;
  562. phandle = <0x72>;
  563. };
  564.  
  565. csi_s {
  566. #clock-cells = <0x0>;
  567. compatible = "allwinner,sunxi-periph-clock";
  568. clock-output-names = "csi_s";
  569. linux,phandle = <0x6b>;
  570. phandle = <0x6b>;
  571. };
  572.  
  573. csi_m {
  574. #clock-cells = <0x0>;
  575. compatible = "allwinner,sunxi-periph-clock";
  576. clock-output-names = "csi_m";
  577. linux,phandle = <0x6c>;
  578. phandle = <0x6c>;
  579. };
  580.  
  581. csi_misc {
  582. #clock-cells = <0x0>;
  583. compatible = "allwinner,sunxi-periph-clock";
  584. clock-output-names = "csi_misc";
  585. linux,phandle = <0x6d>;
  586. phandle = <0x6d>;
  587. };
  588.  
  589. ve {
  590. #clock-cells = <0x0>;
  591. compatible = "allwinner,sunxi-periph-clock";
  592. clock-output-names = "ve";
  593. linux,phandle = <0x16>;
  594. phandle = <0x16>;
  595. };
  596.  
  597. adda {
  598. #clock-cells = <0x0>;
  599. compatible = "allwinner,sunxi-periph-clock";
  600. clock-output-names = "adda";
  601. linux,phandle = <0x39>;
  602. phandle = <0x39>;
  603. };
  604.  
  605. avs {
  606. #clock-cells = <0x0>;
  607. compatible = "allwinner,sunxi-periph-clock";
  608. clock-output-names = "avs";
  609. };
  610.  
  611. hdmi {
  612. #clock-cells = <0x0>;
  613. compatible = "allwinner,sunxi-periph-clock";
  614. assigned-clock-parents = <0x3>;
  615. clock-output-names = "hdmi";
  616. linux,phandle = <0x66>;
  617. phandle = <0x66>;
  618. };
  619.  
  620. hdmi_slow {
  621. #clock-cells = <0x0>;
  622. compatible = "allwinner,sunxi-periph-clock";
  623. clock-output-names = "hdmi_slow";
  624. linux,phandle = <0x67>;
  625. phandle = <0x67>;
  626. };
  627.  
  628. mbus {
  629. #clock-cells = <0x0>;
  630. compatible = "allwinner,sunxi-periph-clock";
  631. clock-output-names = "mbus";
  632. };
  633.  
  634. gpu {
  635. #clock-cells = <0x0>;
  636. compatible = "allwinner,sunxi-periph-clock";
  637. clock-output-names = "gpu";
  638. linux,phandle = <0x9c>;
  639. phandle = <0x9c>;
  640. };
  641.  
  642. usbehci0 {
  643. #clock-cells = <0x0>;
  644. compatible = "allwinner,sunxi-periph-clock";
  645. clock-output-names = "usbehci0";
  646. linux,phandle = <0x2e>;
  647. phandle = <0x2e>;
  648. };
  649.  
  650. usbehci1 {
  651. #clock-cells = <0x0>;
  652. compatible = "allwinner,sunxi-periph-clock";
  653. clock-output-names = "usbehci1";
  654. linux,phandle = <0x31>;
  655. phandle = <0x31>;
  656. };
  657.  
  658. usbehci2 {
  659. #clock-cells = <0x0>;
  660. compatible = "allwinner,sunxi-periph-clock";
  661. clock-output-names = "usbehci2";
  662. linux,phandle = <0x34>;
  663. phandle = <0x34>;
  664. };
  665.  
  666. usbehci3 {
  667. #clock-cells = <0x0>;
  668. compatible = "allwinner,sunxi-periph-clock";
  669. clock-output-names = "usbehci3";
  670. linux,phandle = <0x37>;
  671. phandle = <0x37>;
  672. };
  673.  
  674. usbotg {
  675. #clock-cells = <0x0>;
  676. compatible = "allwinner,sunxi-periph-clock";
  677. clock-output-names = "usbotg";
  678. linux,phandle = <0x2d>;
  679. phandle = <0x2d>;
  680. };
  681.  
  682. gmac {
  683. #clock-cells = <0x0>;
  684. compatible = "allwinner,sunxi-periph-clock";
  685. clock-output-names = "gmac";
  686. linux,phandle = <0x94>;
  687. phandle = <0x94>;
  688. };
  689.  
  690. ephy {
  691. #clock-cells = <0x0>;
  692. compatible = "allwinner,sunxi-periph-clock";
  693. clock-output-names = "ephy";
  694. linux,phandle = <0x95>;
  695. phandle = <0x95>;
  696. };
  697.  
  698. sdram {
  699. #clock-cells = <0x0>;
  700. compatible = "allwinner,sunxi-periph-clock";
  701. clock-output-names = "sdram";
  702. };
  703.  
  704. dma {
  705. #clock-cells = <0x0>;
  706. compatible = "allwinner,sunxi-periph-clock";
  707. clock-output-names = "dma";
  708. linux,phandle = <0xa>;
  709. phandle = <0xa>;
  710. };
  711.  
  712. hwspinlock_rst {
  713. #clock-cells = <0x0>;
  714. compatible = "allwinner,sunxi-periph-clock";
  715. clock-output-names = "hwspinlock_rst";
  716. linux,phandle = <0xe>;
  717. phandle = <0xe>;
  718. };
  719.  
  720. hwspinlock_bus {
  721. #clock-cells = <0x0>;
  722. compatible = "allwinner,sunxi-periph-clock";
  723. clock-output-names = "hwspinlock_bus";
  724. linux,phandle = <0xf>;
  725. phandle = <0xf>;
  726. };
  727.  
  728. msgbox {
  729. #clock-cells = <0x0>;
  730. compatible = "allwinner,sunxi-periph-clock";
  731. clock-output-names = "msgbox";
  732. linux,phandle = <0xd>;
  733. phandle = <0xd>;
  734. };
  735.  
  736. uart0 {
  737. #clock-cells = <0x0>;
  738. compatible = "allwinner,sunxi-periph-clock";
  739. clock-output-names = "uart0";
  740. linux,phandle = <0x17>;
  741. phandle = <0x17>;
  742. };
  743.  
  744. uart1 {
  745. #clock-cells = <0x0>;
  746. compatible = "allwinner,sunxi-periph-clock";
  747. clock-output-names = "uart1";
  748. linux,phandle = <0x1a>;
  749. phandle = <0x1a>;
  750. };
  751.  
  752. uart2 {
  753. #clock-cells = <0x0>;
  754. compatible = "allwinner,sunxi-periph-clock";
  755. clock-output-names = "uart2";
  756. linux,phandle = <0x1d>;
  757. phandle = <0x1d>;
  758. };
  759.  
  760. uart3 {
  761. #clock-cells = <0x0>;
  762. compatible = "allwinner,sunxi-periph-clock";
  763. clock-output-names = "uart3";
  764. linux,phandle = <0x20>;
  765. phandle = <0x20>;
  766. };
  767.  
  768. scr0 {
  769. #clock-cells = <0x0>;
  770. compatible = "allwinner,sunxi-periph-clock";
  771. clock-output-names = "scr0";
  772. linux,phandle = <0x73>;
  773. phandle = <0x73>;
  774. };
  775.  
  776. scr1 {
  777. #clock-cells = <0x0>;
  778. compatible = "allwinner,sunxi-periph-clock";
  779. clock-output-names = "scr1";
  780. linux,phandle = <0x78>;
  781. phandle = <0x78>;
  782. };
  783.  
  784. twi0 {
  785. #clock-cells = <0x0>;
  786. compatible = "allwinner,sunxi-periph-clock";
  787. clock-output-names = "twi0";
  788. linux,phandle = <0x23>;
  789. phandle = <0x23>;
  790. };
  791.  
  792. twi1 {
  793. #clock-cells = <0x0>;
  794. compatible = "allwinner,sunxi-periph-clock";
  795. clock-output-names = "twi1";
  796. linux,phandle = <0x26>;
  797. phandle = <0x26>;
  798. };
  799.  
  800. twi2 {
  801. #clock-cells = <0x0>;
  802. compatible = "allwinner,sunxi-periph-clock";
  803. clock-output-names = "twi2";
  804. linux,phandle = <0x29>;
  805. phandle = <0x29>;
  806. };
  807.  
  808. pio {
  809. #clock-cells = <0x0>;
  810. compatible = "allwinner,sunxi-periph-clock";
  811. clock-output-names = "pio";
  812. linux,phandle = <0x9>;
  813. phandle = <0x9>;
  814. };
  815.  
  816. cpurcir {
  817. #clock-cells = <0x0>;
  818. compatible = "allwinner,sunxi-periph-cpus-clock";
  819. clock-output-names = "cpurcir";
  820. linux,phandle = <0x11>;
  821. phandle = <0x11>;
  822. };
  823.  
  824. cpurpio {
  825. #clock-cells = <0x0>;
  826. compatible = "allwinner,sunxi-periph-cpus-clock";
  827. clock-output-names = "cpurpio";
  828. linux,phandle = <0x8>;
  829. phandle = <0x8>;
  830. };
  831.  
  832. cpurpll_peri0 {
  833. #clock-cells = <0x0>;
  834. compatible = "allwinner,sunxi-periph-cpus-clock";
  835. clock-output-names = "cpurpll_peri0";
  836. };
  837.  
  838. cpurcpus {
  839. #clock-cells = <0x0>;
  840. compatible = "allwinner,sunxi-periph-cpus-clock";
  841. clock-output-names = "cpurcpus";
  842. };
  843.  
  844. cpurahbs {
  845. #clock-cells = <0x0>;
  846. compatible = "allwinner,sunxi-periph-cpus-clock";
  847. clock-output-names = "cpurahbs";
  848. };
  849.  
  850. cpurapbs {
  851. #clock-cells = <0x0>;
  852. compatible = "allwinner,sunxi-periph-cpus-clock";
  853. clock-output-names = "cpurapbs";
  854. };
  855.  
  856. losc_out {
  857. #clock-cells = <0x0>;
  858. compatible = "allwinner,sunxi-periph-cpus-clock";
  859. clock-output-names = "losc_out";
  860. linux,phandle = <0x9d>;
  861. phandle = <0x9d>;
  862. };
  863. };
  864.  
  865. soc@01c00000 {
  866. compatible = "simple-bus";
  867. #address-cells = <0x2>;
  868. #size-cells = <0x2>;
  869. ranges;
  870. device_type = "soc";
  871.  
  872. pinctrl@01f02c00 {
  873. compatible = "allwinner,sun50iw2p1-r-pinctrl";
  874. reg = <0x0 0x1f02c00 0x0 0x400>;
  875. interrupts = <0x0 0x2d 0x4>;
  876. clocks = <0x8>;
  877. device_type = "r_pio";
  878. gpio-controller;
  879. interrupt-controller;
  880. #interrupt-cells = <0x2>;
  881. #size-cells = <0x0>;
  882. #gpio-cells = <0x6>;
  883. linux,phandle = <0x9e>;
  884. phandle = <0x9e>;
  885.  
  886. s_uart0@0 {
  887. allwinner,pins = "PL2", "PL3";
  888. allwinner,function = "s_uart0";
  889. allwinner,muxsel = <0x2>;
  890. allwinner,drive = <0x1>;
  891. allwinner,pull = <0x1>;
  892. linux,phandle = <0x12>;
  893. phandle = <0x12>;
  894. };
  895.  
  896. s_twi0@0 {
  897. allwinner,pins = "PL0", "PL1";
  898. allwinner,function = "s_twi0";
  899. allwinner,muxsel = <0x2>;
  900. allwinner,drive = <0x2>;
  901. allwinner,pull = <0x1>;
  902. linux,phandle = <0x13>;
  903. phandle = <0x13>;
  904. };
  905.  
  906. s_jtag0@0 {
  907. allwinner,pins = "PL4", "PL5", "PL6", "PL7";
  908. allwinner,function = "s_jtag0";
  909. allwinner,muxsel = <0x2>;
  910. allwinner,drive = <0x2>;
  911. allwinner,pull = <0x1>;
  912. linux,phandle = <0x14>;
  913. phandle = <0x14>;
  914. };
  915.  
  916. s_cir0@0 {
  917. allwinner,pins = "PL11";
  918. allwinner,function = "s_cir0";
  919. allwinner,muxsel = <0x2>;
  920. allwinner,drive = <0x2>;
  921. allwinner,pull = <0x1>;
  922. linux,phandle = <0x10>;
  923. phandle = <0x10>;
  924. };
  925. };
  926.  
  927. pinctrl@01c20800 {
  928. compatible = "allwinner,sun50iw2p1-pinctrl";
  929. reg = <0x0 0x1c20800 0x0 0x400>;
  930. interrupts = <0x0 0xb 0x4 0x0 0x11 0x4 0x0 0x17 0x4>;
  931. device_type = "pio";
  932. clocks = <0x9>;
  933. gpio-controller;
  934. interrupt-controller;
  935. #interrupt-cells = <0x2>;
  936. #size-cells = <0x0>;
  937. #gpio-cells = <0x6>;
  938. linux,phandle = <0x3a>;
  939. phandle = <0x3a>;
  940.  
  941. vdevice@0 {
  942. allwinner,pins = "PA1", "PA2";
  943. allwinner,function = "vdevice";
  944. allwinner,muxsel = <0x5>;
  945. allwinner,drive = <0x1>;
  946. allwinner,pull = <0x1>;
  947. linux,phandle = <0x70>;
  948. phandle = <0x70>;
  949. };
  950.  
  951. uart0@0 {
  952. allwinner,pins = "PA4", "PA5";
  953. allwinner,pname = "uart0_tx", "uart0_rx";
  954. allwinner,function = "uart0";
  955. allwinner,muxsel = <0x2>;
  956. allwinner,drive = <0x1>;
  957. allwinner,pull = <0x1>;
  958. linux,phandle = <0x18>;
  959. phandle = <0x18>;
  960. };
  961.  
  962. uart0@1 {
  963. allwinner,pins = "PA4", "PA5";
  964. allwinner,function = "io_disabled";
  965. allwinner,muxsel = <0x7>;
  966. allwinner,drive = <0x1>;
  967. allwinner,pull = <0x0>;
  968. linux,phandle = <0x19>;
  969. phandle = <0x19>;
  970. };
  971.  
  972. uart1@0 {
  973. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  974. allwinner,pname = "uart1_tx", "uart1_rx", "uart1_rts", "uart1_cts";
  975. allwinner,function = "uart1";
  976. allwinner,muxsel = <0x2>;
  977. allwinner,drive = <0x1>;
  978. allwinner,pull = <0x1>;
  979. linux,phandle = <0x1b>;
  980. phandle = <0x1b>;
  981. };
  982.  
  983. uart1@1 {
  984. allwinner,pins = "PG6", "PG7", "PG8", "PG9";
  985. allwinner,function = "io_disabled";
  986. allwinner,muxsel = <0x7>;
  987. allwinner,drive = <0x1>;
  988. allwinner,pull = <0x0>;
  989. linux,phandle = <0x1c>;
  990. phandle = <0x1c>;
  991. };
  992.  
  993. uart2@0 {
  994. allwinner,pins = "PA0", "PA1", "PA2", "PA3";
  995. allwinner,pname = "uart2_tx", "uart2_rx", "uart2_rts", "uart2_cts";
  996. allwinner,function = "uart2";
  997. allwinner,muxsel = <0x2>;
  998. allwinner,drive = <0x1>;
  999. allwinner,pull = <0x1>;
  1000. linux,phandle = <0x1e>;
  1001. phandle = <0x1e>;
  1002. };
  1003.  
  1004. uart2@1 {
  1005. allwinner,pins = "PA0", "PA1", "PA2", "PA3";
  1006. allwinner,function = "io_disabled";
  1007. allwinner,muxsel = <0x7>;
  1008. allwinner,drive = <0x1>;
  1009. allwinner,pull = <0x0>;
  1010. linux,phandle = <0x1f>;
  1011. phandle = <0x1f>;
  1012. };
  1013.  
  1014. uart3@0 {
  1015. allwinner,pins = "PA13", "PA14", "PA15", "PA16";
  1016. allwinner,pname = "uart3_tx", "uart3_rx", "uart3_rts", "uart3_cts";
  1017. allwinner,function = "uart3";
  1018. allwinner,muxsel = <0x3>;
  1019. allwinner,drive = <0x1>;
  1020. allwinner,pull = <0x1>;
  1021. linux,phandle = <0x21>;
  1022. phandle = <0x21>;
  1023. };
  1024.  
  1025. uart3@1 {
  1026. allwinner,pins = "PA13", "PA14", "PA15", "PA16";
  1027. allwinner,function = "io_disabled";
  1028. allwinner,muxsel = <0x7>;
  1029. allwinner,drive = <0x1>;
  1030. allwinner,pull = <0x0>;
  1031. linux,phandle = <0x22>;
  1032. phandle = <0x22>;
  1033. };
  1034.  
  1035. twi0@0 {
  1036. allwinner,pins = "PA11", "PA12";
  1037. allwinner,pname = "twi0_scl", "twi0_sda";
  1038. allwinner,function = "twi0";
  1039. allwinner,muxsel = <0x2>;
  1040. allwinner,drive = <0x1>;
  1041. allwinner,pull = <0x0>;
  1042. linux,phandle = <0x24>;
  1043. phandle = <0x24>;
  1044. };
  1045.  
  1046. twi0@1 {
  1047. allwinner,pins = "PA11", "PA12";
  1048. allwinner,function = "io_disabled";
  1049. allwinner,muxsel = <0x7>;
  1050. allwinner,drive = <0x1>;
  1051. allwinner,pull = <0x0>;
  1052. linux,phandle = <0x25>;
  1053. phandle = <0x25>;
  1054. };
  1055.  
  1056. twi1@0 {
  1057. allwinner,pins = "PA18", "PA19";
  1058. allwinner,pname = "twi1_scl", "twi1_sda";
  1059. allwinner,function = "twi1";
  1060. allwinner,muxsel = <0x3>;
  1061. allwinner,drive = <0x1>;
  1062. allwinner,pull = <0x0>;
  1063. linux,phandle = <0x27>;
  1064. phandle = <0x27>;
  1065. };
  1066.  
  1067. twi1@1 {
  1068. allwinner,pins = "PA18", "PA19";
  1069. allwinner,function = "io_disabled";
  1070. allwinner,muxsel = <0x7>;
  1071. allwinner,drive = <0x1>;
  1072. allwinner,pull = <0x0>;
  1073. linux,phandle = <0x28>;
  1074. phandle = <0x28>;
  1075. };
  1076.  
  1077. twi2@0 {
  1078. allwinner,pins = "PE12", "PE13";
  1079. allwinner,pname = "twi2_scl", "twi2_sda";
  1080. allwinner,function = "twi2";
  1081. allwinner,muxsel = <0x3>;
  1082. allwinner,drive = <0x1>;
  1083. allwinner,pull = <0x0>;
  1084. linux,phandle = <0x2a>;
  1085. phandle = <0x2a>;
  1086. };
  1087.  
  1088. twi2@1 {
  1089. allwinner,pins = "PE12", "PE13";
  1090. allwinner,function = "io_disabled";
  1091. allwinner,muxsel = <0x7>;
  1092. allwinner,drive = <0x1>;
  1093. allwinner,pull = <0x0>;
  1094. linux,phandle = <0x2b>;
  1095. phandle = <0x2b>;
  1096. };
  1097.  
  1098. ts0@0 {
  1099. allwinner,pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
  1100. allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7";
  1101. allwinner,function = "ts0";
  1102. allwinner,muxsel = <0x3>;
  1103. allwinner,drive = <0x1>;
  1104. allwinner,pull = <0x0>;
  1105. linux,phandle = <0x81>;
  1106. phandle = <0x81>;
  1107. };
  1108.  
  1109. ts0_sleep@0 {
  1110. allwinner,pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11";
  1111. allwinner,pname = "ts0_clk", "ts0_err", "ts0_sync", "ts0_dvld", "ts0_d0", "ts0_d1", "ts0_d2", "ts0_d3", "ts0_d4", "ts0_d5", "ts0_d6", "ts0_d7";
  1112. allwinner,function = "io_disabled";
  1113. allwinner,muxsel = <0x7>;
  1114. allwinner,drive = <0x1>;
  1115. allwinner,pull = <0x0>;
  1116. linux,phandle = <0x85>;
  1117. phandle = <0x85>;
  1118. };
  1119.  
  1120. ts1@0 {
  1121. allwinner,pins = "PE7", "PE8", "PE9", "PE10", "PE11";
  1122. allwinner,pname = "ts1_clk", "ts1_err", "ts1_sync", "ts1_dvld", "ts1_d0";
  1123. allwinner,function = "ts1";
  1124. allwinner,muxsel = <0x4>;
  1125. allwinner,drive = <0x1>;
  1126. allwinner,pull = <0x0>;
  1127. linux,phandle = <0x82>;
  1128. phandle = <0x82>;
  1129. };
  1130.  
  1131. ts1_sleep@0 {
  1132. allwinner,pins = "PE7", "PE8", "PE9", "PE10", "PE11";
  1133. allwinner,pname = "ts1_clk", "ts1_err", "ts1_sync", "ts1_dvld", "ts1_d0";
  1134. allwinner,function = "io_disabled";
  1135. allwinner,muxsel = <0x7>;
  1136. allwinner,drive = <0x1>;
  1137. allwinner,pull = <0x0>;
  1138. linux,phandle = <0x86>;
  1139. phandle = <0x86>;
  1140. };
  1141.  
  1142. ts2@0 {
  1143. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1144. allwinner,pname = "ts2_clk", "ts2_err", "ts2_sync", "ts2_dvld", "ts2_d0", "ts2_d1", "ts2_d2", "ts2_d3", "ts2_d4", "ts2_d5", "ts2_d6", "ts2_d7";
  1145. allwinner,function = "ts2";
  1146. allwinner,muxsel = <0x4>;
  1147. allwinner,drive = <0x1>;
  1148. allwinner,pull = <0x0>;
  1149. linux,phandle = <0x83>;
  1150. phandle = <0x83>;
  1151. };
  1152.  
  1153. ts2_sleep@0 {
  1154. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", "PD10", "PD11";
  1155. allwinner,pname = "ts2_clk", "ts2_err", "ts2_sync", "ts2_dvld", "ts2_d0", "ts2_d1", "ts2_d2", "ts2_d3", "ts2_d4", "ts2_d5", "ts2_d6", "ts2_d7";
  1156. allwinner,function = "io_disabled";
  1157. allwinner,muxsel = <0x7>;
  1158. allwinner,drive = <0x1>;
  1159. allwinner,pull = <0x0>;
  1160. linux,phandle = <0x87>;
  1161. phandle = <0x87>;
  1162. };
  1163.  
  1164. ts3@0 {
  1165. allwinner,pins = "PD7", "PD8", "PD9", "PD10", "PD11";
  1166. allwinner,pname = "ts3_clk", "ts3_err", "ts3_sync", "ts3_dvld", "ts3_d0";
  1167. allwinner,function = "ts3";
  1168. allwinner,muxsel = <0x5>;
  1169. allwinner,drive = <0x1>;
  1170. allwinner,pull = <0x0>;
  1171. linux,phandle = <0x84>;
  1172. phandle = <0x84>;
  1173. };
  1174.  
  1175. ts3_sleep@0 {
  1176. allwinner,pins = "PD7", "PD8", "PD9", "PD10", "PD11";
  1177. allwinner,pname = "ts3_clk", "ts3_err", "ts3_sync", "ts3_dvld", "ts3_d0";
  1178. allwinner,function = "io_disabled";
  1179. allwinner,muxsel = <0x7>;
  1180. allwinner,drive = <0x1>;
  1181. allwinner,pull = <0x0>;
  1182. linux,phandle = <0x88>;
  1183. phandle = <0x88>;
  1184. };
  1185.  
  1186. spi0@0 {
  1187. allwinner,pins = "PC2", "PC0", "PC1";
  1188. allwinner,pname = "spi0_sclk", "spi0_mosi", "spi0_miso";
  1189. allwinner,function = "spi0";
  1190. allwinner,muxsel = <0x3>;
  1191. allwinner,drive = <0x1>;
  1192. allwinner,pull = <0x0>;
  1193. linux,phandle = <0x4c>;
  1194. phandle = <0x4c>;
  1195. };
  1196.  
  1197. spi0@1 {
  1198. allwinner,pins = "PC3";
  1199. allwinner,pname = "spi0_cs0";
  1200. allwinner,function = "spi0";
  1201. allwinner,muxsel = <0x3>;
  1202. allwinner,drive = <0x1>;
  1203. allwinner,pull = <0x1>;
  1204. linux,phandle = <0x4d>;
  1205. phandle = <0x4d>;
  1206. };
  1207.  
  1208. spi0@2 {
  1209. allwinner,pins = "PC3", "PC2", "PC0", "PC1";
  1210. allwinner,function = "io_disabled";
  1211. allwinner,muxsel = <0x7>;
  1212. allwinner,drive = <0x1>;
  1213. allwinner,pull = <0x0>;
  1214. linux,phandle = <0x4e>;
  1215. phandle = <0x4e>;
  1216. };
  1217.  
  1218. spi1@0 {
  1219. allwinner,pins = "PA14", "PA15", "PA16";
  1220. allwinner,pname = "spi1_sclk", "spi1_mosi", "spi1_miso";
  1221. allwinner,function = "spi1";
  1222. allwinner,muxsel = <0x2>;
  1223. allwinner,drive = <0x1>;
  1224. allwinner,pull = <0x0>;
  1225. linux,phandle = <0x50>;
  1226. phandle = <0x50>;
  1227. };
  1228.  
  1229. spi1@1 {
  1230. allwinner,pins = "PA13";
  1231. allwinner,pname = "spi1_cs0";
  1232. allwinner,function = "spi1";
  1233. allwinner,muxsel = <0x2>;
  1234. allwinner,drive = <0x1>;
  1235. allwinner,pull = <0x1>;
  1236. linux,phandle = <0x51>;
  1237. phandle = <0x51>;
  1238. };
  1239.  
  1240. spi1@2 {
  1241. allwinner,pins = "PA13", "PA14", "PA15", "PA16";
  1242. allwinner,function = "io_disabled";
  1243. allwinner,muxsel = <0x7>;
  1244. allwinner,drive = <0x1>;
  1245. allwinner,pull = <0x0>;
  1246. linux,phandle = <0x52>;
  1247. phandle = <0x52>;
  1248. };
  1249.  
  1250. sdc0@0 {
  1251. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1252. allwinner,function = "sdc0";
  1253. allwinner,muxsel = <0x2>;
  1254. allwinner,drive = <0x1>;
  1255. allwinner,pull = <0x1>;
  1256. linux,phandle = <0x5c>;
  1257. phandle = <0x5c>;
  1258. };
  1259.  
  1260. sdc0@1 {
  1261. allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
  1262. allwinner,function = "io_disabled";
  1263. allwinner,muxsel = <0x7>;
  1264. allwinner,drive = <0x1>;
  1265. allwinner,pull = <0x1>;
  1266. linux,phandle = <0x5d>;
  1267. phandle = <0x5d>;
  1268. };
  1269.  
  1270. sdc1@0 {
  1271. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1272. allwinner,function = "sdc1";
  1273. allwinner,muxsel = <0x2>;
  1274. allwinner,drive = <0x3>;
  1275. allwinner,pull = <0x1>;
  1276. linux,phandle = <0x61>;
  1277. phandle = <0x61>;
  1278. };
  1279.  
  1280. sdc1@1 {
  1281. allwinner,pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
  1282. allwinner,function = "io_disabled";
  1283. allwinner,muxsel = <0x7>;
  1284. allwinner,drive = <0x1>;
  1285. allwinner,pull = <0x1>;
  1286. linux,phandle = <0x62>;
  1287. phandle = <0x62>;
  1288. };
  1289.  
  1290. sdc2@0 {
  1291. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1292. allwinner,function = "sdc2";
  1293. allwinner,muxsel = <0x3>;
  1294. allwinner,drive = <0x2>;
  1295. allwinner,pull = <0x1>;
  1296. linux,phandle = <0x57>;
  1297. phandle = <0x57>;
  1298. };
  1299.  
  1300. sdc2@1 {
  1301. allwinner,pins = "PC1", "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1302. allwinner,function = "io_disabled";
  1303. allwinner,muxsel = <0x7>;
  1304. allwinner,drive = <0x1>;
  1305. allwinner,pull = <0x1>;
  1306. linux,phandle = <0x58>;
  1307. phandle = <0x58>;
  1308. };
  1309.  
  1310. daudio0@0 {
  1311. allwinner,pins = "PA20", "PA6", "PA18", "PA19", "PA21";
  1312. allwinner,function = "pcm0";
  1313. allwinner,muxsel = <0x3>;
  1314. allwinner,drive = <0x1>;
  1315. allwinner,pull = <0x0>;
  1316. linux,phandle = <0x3c>;
  1317. phandle = <0x3c>;
  1318. };
  1319.  
  1320. daudio0_sleep@0 {
  1321. allwinner,pins = "PA20", "PA6", "PA18", "PA19", "PA21";
  1322. allwinner,function = "io_disabled";
  1323. allwinner,muxsel = <0x7>;
  1324. allwinner,drive = <0x1>;
  1325. allwinner,pull = <0x0>;
  1326. linux,phandle = <0x3d>;
  1327. phandle = <0x3d>;
  1328. };
  1329.  
  1330. daudio1@0 {
  1331. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1332. allwinner,function = "pcm1";
  1333. allwinner,muxsel = <0x2>;
  1334. allwinner,drive = <0x1>;
  1335. allwinner,pull = <0x0>;
  1336. linux,phandle = <0x3e>;
  1337. phandle = <0x3e>;
  1338. };
  1339.  
  1340. daudio1_sleep@0 {
  1341. allwinner,pins = "PG10", "PG11", "PG12", "PG13";
  1342. allwinner,function = "io_disabled";
  1343. allwinner,muxsel = <0x7>;
  1344. allwinner,drive = <0x1>;
  1345. allwinner,pull = <0x0>;
  1346. linux,phandle = <0x3f>;
  1347. phandle = <0x3f>;
  1348. };
  1349.  
  1350. spdif@0 {
  1351. allwinner,pins = "PA17";
  1352. allwinner,function = "spdif0";
  1353. allwinner,muxsel = <0x2>;
  1354. allwinner,drive = <0x1>;
  1355. allwinner,pull = <0x0>;
  1356. linux,phandle = <0x43>;
  1357. phandle = <0x43>;
  1358. };
  1359.  
  1360. spdif_sleep@0 {
  1361. allwinner,pins = "PA17";
  1362. allwinner,function = "io_disabled";
  1363. allwinner,muxsel = <0x7>;
  1364. allwinner,drive = <0x1>;
  1365. allwinner,pull = <0x0>;
  1366. linux,phandle = <0x44>;
  1367. phandle = <0x44>;
  1368. };
  1369.  
  1370. csi0@0 {
  1371. allwinner,pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13";
  1372. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  1373. allwinner,function = "csi0";
  1374. allwinner,muxsel = <0x2>;
  1375. allwinner,drive = <0x1>;
  1376. allwinner,pull = <0x0>;
  1377. allwinner,data = <0x0>;
  1378. linux,phandle = <0x6e>;
  1379. phandle = <0x6e>;
  1380. };
  1381.  
  1382. csi0_sleep@0 {
  1383. allwinner,pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", "PE12", "PE13";
  1384. allwinner,pname = "csi0_pck", "csi0_hsync", "csi0_vsync", "csi0_d0", "csi0_d1", "csi0_d2", "csi0_d3", "csi0_d4", "csi0_d5", "csi0_d6", "csi0_d7", "csi0_sck", "csi0_sda";
  1385. allwinner,function = "io_disabled";
  1386. allwinner,muxsel = <0x7>;
  1387. allwinner,drive = <0x1>;
  1388. allwinner,pull = <0x0>;
  1389. allwinner,data = <0x0>;
  1390. linux,phandle = <0x6f>;
  1391. phandle = <0x6f>;
  1392. };
  1393.  
  1394. scr0@0 {
  1395. allwinner,pins = "PA9", "PA10", "PA6", "PA7", "PA8";
  1396. allwinner,pname = "scr0_rst", "scr0_det", "scr0_vccen", "scr0_sck", "scr0_sda";
  1397. allwinner,function = "sim0";
  1398. allwinner,muxsel = <0x2>;
  1399. allwinner,drive = <0x1>;
  1400. allwinner,pull = <0x1>;
  1401. linux,phandle = <0x75>;
  1402. phandle = <0x75>;
  1403. };
  1404.  
  1405. scr0@1 {
  1406. allwinner,pins = "PA20", "PA21";
  1407. allwinner,pname = "scr0_vppen", "scr0_vppp";
  1408. allwinner,function = "sim0";
  1409. allwinner,muxsel = <0x3>;
  1410. allwinner,drive = <0x1>;
  1411. allwinner,pull = <0x1>;
  1412. linux,phandle = <0x76>;
  1413. phandle = <0x76>;
  1414. };
  1415.  
  1416. scr0@2 {
  1417. allwinner,pins = "PA9", "PA10", "PA6", "PA7", "PA8", "PA20", "PA21";
  1418. allwinner,function = "io_disabled";
  1419. allwinner,muxsel = <0x7>;
  1420. allwinner,drive = <0x1>;
  1421. allwinner,pull = <0x0>;
  1422. linux,phandle = <0x77>;
  1423. phandle = <0x77>;
  1424. };
  1425.  
  1426. scr1@0 {
  1427. allwinner,pins = "PD15", "PD16", "PD12", "PD13", "PD14";
  1428. allwinner,pname = "scr1_rst", "scr1_det", "scr1_vccen", "scr1_sck", "scr1_sda";
  1429. allwinner,function = "sim1";
  1430. allwinner,muxsel = <0x4>;
  1431. allwinner,drive = <0x1>;
  1432. allwinner,pull = <0x1>;
  1433. linux,phandle = <0x79>;
  1434. phandle = <0x79>;
  1435. };
  1436.  
  1437. scr1@1 {
  1438. allwinner,pins = "PE14", "PE15";
  1439. allwinner,pname = "scr1_vppen", "scr1_vppp";
  1440. allwinner,function = "sim1";
  1441. allwinner,muxsel = <0x3>;
  1442. allwinner,drive = <0x1>;
  1443. allwinner,pull = <0x1>;
  1444. linux,phandle = <0x7a>;
  1445. phandle = <0x7a>;
  1446. };
  1447.  
  1448. scr1@2 {
  1449. allwinner,pins = "PD15", "PD16", "PD12", "PD13", "PD14", "PE14", "PE15";
  1450. allwinner,function = "io_disabled";
  1451. allwinner,muxsel = <0x7>;
  1452. allwinner,drive = <0x1>;
  1453. allwinner,pull = <0x0>;
  1454. linux,phandle = <0x7b>;
  1455. phandle = <0x7b>;
  1456. };
  1457.  
  1458. nand0@0 {
  1459. allwinner,pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16";
  1460. allwinner,pname = "nand0_we", "nand0_ale", "nand0_cle", "nand0_nre", "nand0_d0", "nand0_d1", "nand0_d2", "nand0_d3", "nand0_d4", "nand0_d5", "nand0_d6", "nand0_d7", "nand0_ndqs";
  1461. allwinner,function = "nand0";
  1462. allwinner,muxsel = <0x2>;
  1463. allwinner,drive = <0x1>;
  1464. allwinner,pull = <0x0>;
  1465. linux,phandle = <0x7d>;
  1466. phandle = <0x7d>;
  1467. };
  1468.  
  1469. nand0@1 {
  1470. allwinner,pins = "PC3", "PC4", "PC6", "PC7", "PC17", "PC18";
  1471. allwinner,pname = "nand0_ce1", "nand0_ce0", "nand0_rb0", "nand0_rb1", "nand0_ce2", "nand0_ce3";
  1472. allwinner,function = "nand0";
  1473. allwinner,muxsel = <0x2>;
  1474. allwinner,drive = <0x1>;
  1475. allwinner,pull = <0x1>;
  1476. linux,phandle = <0x7e>;
  1477. phandle = <0x7e>;
  1478. };
  1479.  
  1480. nand0@2 {
  1481. allwinner,pins = "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14", "PC15", "PC16", "PC17", "PC18";
  1482. allwinner,function = "io_disabled";
  1483. allwinner,muxsel = <0x7>;
  1484. allwinner,drive = <0x1>;
  1485. allwinner,pull = <0x0>;
  1486. linux,phandle = <0x7f>;
  1487. phandle = <0x7f>;
  1488. };
  1489.  
  1490. gmac@0 {
  1491. allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", "PD12", "PD13", "PD15", "PD16", "PD17";
  1492. allwinner,function = "gmac0";
  1493. allwinner,muxsel = <0x2>;
  1494. allwinner,drive = <0x3>;
  1495. allwinner,pull = <0x0>;
  1496. linux,phandle = <0x93>;
  1497. phandle = <0x93>;
  1498. };
  1499. };
  1500.  
  1501. dma-controller@01c02000 {
  1502. compatible = "allwinner,sun50i-dma";
  1503. reg = <0x0 0x1c02000 0x0 0x1000>;
  1504. interrupts = <0x0 0x32 0x4>;
  1505. clocks = <0xa>;
  1506. #dma-cells = <0x1>;
  1507. };
  1508.  
  1509. mbus-controller@01c62000 {
  1510. compatible = "allwinner,sun50i-mbus";
  1511. reg = <0x0 0x1c62000 0x0 0x110>;
  1512. #mbus-cells = <0x1>;
  1513. };
  1514.  
  1515. arisc {
  1516. compatible = "allwinner,sunxi-arisc";
  1517. #address-cells = <0x2>;
  1518. #size-cells = <0x2>;
  1519. clocks = <0xb 0xc 0x6 0x4>;
  1520. clock-names = "losc", "iosc", "hosc", "pll_periph0";
  1521. powchk_used = <0x0>;
  1522. power_reg = <0x2309621>;
  1523. system_power = <0x32>;
  1524. };
  1525.  
  1526. arisc_space {
  1527. compatible = "allwinner,arisc_space";
  1528. space1 = <0x48040000 0x0 0x14000>;
  1529. space2 = <0x48100000 0x18000 0x4000>;
  1530. space3 = <0x48104000 0x0 0x1000>;
  1531. space4 = <0x48105000 0x0 0x1000>;
  1532. };
  1533.  
  1534. standby_space {
  1535. compatible = "allwinner,standby_space";
  1536. space1 = <0x40020000 0x0 0x800>;
  1537. };
  1538.  
  1539. msgbox@1c17000 {
  1540. compatible = "allwinner,msgbox";
  1541. clocks = <0xd>;
  1542. clock-names = "clk_msgbox";
  1543. reg = <0x0 0x1c17000 0x0 0x1000>;
  1544. interrupts = <0x0 0x31 0x1>;
  1545. status = "okay";
  1546. };
  1547.  
  1548. hwspinlock@1c18000 {
  1549. compatible = "allwinner,sunxi-hwspinlock";
  1550. clocks = <0xe 0xf>;
  1551. clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
  1552. reg = <0x0 0x1c18000 0x0 0x1000>;
  1553. num-locks = <0x8>;
  1554. status = "okay";
  1555. };
  1556.  
  1557. s_cir@1f02000 {
  1558. compatible = "allwinner,s_cir";
  1559. reg = <0x0 0x1f02000 0x0 0x400>;
  1560. interrupts = <0x0 0x25 0x4>;
  1561. pinctrl-names = "default";
  1562. pinctrl-0 = <0x10>;
  1563. clocks = <0x6 0x11>;
  1564. supply = "vcc-pl";
  1565. supply_vol = <0x325aa0>;
  1566. status = "okay";
  1567. };
  1568.  
  1569. s_uart@1f02800 {
  1570. compatible = "allwinner,s_uart";
  1571. reg = <0x0 0x1f02800 0x0 0x400>;
  1572. interrupts = <0x0 0x26 0x4>;
  1573. pinctrl-names = "default";
  1574. pinctrl-0 = <0x12>;
  1575. status = "okay";
  1576. };
  1577.  
  1578. s_twi@1f03400 {
  1579. compatible = "allwinner,s_twi";
  1580. reg = <0x0 0x1f02400 0x0 0x20>;
  1581. interrupts = <0x0 0x2c 0x4>;
  1582. pinctrl-names = "default";
  1583. pinctrl-0 = <0x13>;
  1584. status = "okay";
  1585. };
  1586.  
  1587. s_jtag0 {
  1588. compatible = "allwinner,s_jtag";
  1589. pinctrl-names = "default";
  1590. pinctrl-0 = <0x14>;
  1591. status = "disable";
  1592. };
  1593.  
  1594. box_start_os0 {
  1595. compatible = "allwinner,box_start_os";
  1596. start_type = <0x0>;
  1597. irkey_used = <0x0>;
  1598. pmukey_used = <0x0>;
  1599. pmukey_num = <0x0>;
  1600. led_power = <0x0>;
  1601. led_state = <0x0>;
  1602. status = "disable";
  1603. };
  1604.  
  1605. timer@1c20c00 {
  1606. compatible = "allwinner,sunxi-timer";
  1607. device_type = "timer";
  1608. reg = <0x0 0x1c20c00 0x0 0x90>;
  1609. interrupts = <0x0 0x12 0x1>;
  1610. clock-frequency = <0x16e3600>;
  1611. timer-prescale = <0x10>;
  1612. };
  1613.  
  1614. rtc@01f00000 {
  1615. compatible = "allwinner,sun50i-rtc";
  1616. device_type = "rtc";
  1617. reg = <0x0 0x1f00000 0x0 0x218>;
  1618. interrupts = <0x0 0x28 0x4>;
  1619. gpr_offset = <0x100>;
  1620. gpr_len = <0x4>;
  1621. };
  1622.  
  1623. watchdog@01c20ca0 {
  1624. compatible = "allwinner,sun50i-wdt";
  1625. reg = <0x0 0x1c20ca0 0x0 0x20>;
  1626. interrupts = <0x0 0x19 0x4>;
  1627. };
  1628.  
  1629. ve@01c0e000 {
  1630. compatible = "allwinner,sunxi-cedar-ve";
  1631. reg = <0x0 0x1c0e000 0x0 0x1000 0x0 0x1c00000 0x0 0x10 0x0 0x1c20000 0x0 0x800>;
  1632. interrupts = <0x0 0x3a 0x4>;
  1633. clocks = <0x15 0x16>;
  1634. };
  1635.  
  1636. uart@01c28000 {
  1637. compatible = "allwinner,sun50i-uart";
  1638. device_type = "uart0";
  1639. reg = <0x0 0x1c28000 0x0 0x400>;
  1640. interrupts = <0x0 0x0 0x4>;
  1641. clocks = <0x17>;
  1642. pinctrl-names = "default", "sleep";
  1643. pinctrl-0 = <0x18>;
  1644. pinctrl-1 = <0x19>;
  1645. uart0_port = <0x0>;
  1646. uart0_type = <0x2>;
  1647. status = "okay";
  1648. };
  1649.  
  1650. uart@01c28400 {
  1651. compatible = "allwinner,sun50i-uart";
  1652. device_type = "uart1";
  1653. reg = <0x0 0x1c28400 0x0 0x400>;
  1654. interrupts = <0x0 0x1 0x4>;
  1655. clocks = <0x1a>;
  1656. pinctrl-names = "default", "sleep";
  1657. pinctrl-0 = <0x1b>;
  1658. pinctrl-1 = <0x1c>;
  1659. uart1_port = <0x1>;
  1660. uart1_type = <0x4>;
  1661. status = "disabled";
  1662. };
  1663.  
  1664. uart@01c28800 {
  1665. compatible = "allwinner,sun50i-uart";
  1666. device_type = "uart2";
  1667. reg = <0x0 0x1c28800 0x0 0x400>;
  1668. interrupts = <0x0 0x2 0x4>;
  1669. clocks = <0x1d>;
  1670. pinctrl-names = "default", "sleep";
  1671. pinctrl-0 = <0x1e>;
  1672. pinctrl-1 = <0x1f>;
  1673. uart2_port = <0x2>;
  1674. uart2_type = <0x4>;
  1675. status = "disabled";
  1676. };
  1677.  
  1678. uart@01c28c00 {
  1679. compatible = "allwinner,sun50i-uart";
  1680. device_type = "uart3";
  1681. reg = <0x0 0x1c28c00 0x0 0x400>;
  1682. interrupts = <0x0 0x3 0x4>;
  1683. clocks = <0x20>;
  1684. pinctrl-names = "default", "sleep";
  1685. pinctrl-0 = <0x21>;
  1686. pinctrl-1 = <0x22>;
  1687. uart3_port = <0x3>;
  1688. uart3_type = <0x4>;
  1689. status = "disabled";
  1690. };
  1691.  
  1692. twi@0x01c2ac00 {
  1693. #address-cells = <0x1>;
  1694. #size-cells = <0x0>;
  1695. compatible = "allwinner,sun50i-twi";
  1696. device_type = "twi0";
  1697. reg = <0x0 0x1c2ac00 0x0 0x400>;
  1698. interrupts = <0x0 0x6 0x4>;
  1699. clocks = <0x23>;
  1700. clock-frequency = <0x61a80>;
  1701. pinctrl-names = "default", "sleep";
  1702. pinctrl-0 = <0x24>;
  1703. pinctrl-1 = <0x25>;
  1704. status = "okay";
  1705. };
  1706.  
  1707. twi@0x01c2b000 {
  1708. #address-cells = <0x1>;
  1709. #size-cells = <0x0>;
  1710. compatible = "allwinner,sun50i-twi";
  1711. device_type = "twi1";
  1712. reg = <0x0 0x1c2b000 0x0 0x400>;
  1713. interrupts = <0x0 0x7 0x4>;
  1714. clocks = <0x26>;
  1715. clock-frequency = <0x30d40>;
  1716. pinctrl-names = "default", "sleep";
  1717. pinctrl-0 = <0x27>;
  1718. pinctrl-1 = <0x28>;
  1719. status = "okay";
  1720. };
  1721.  
  1722. twi@0x01c2b400 {
  1723. #address-cells = <0x1>;
  1724. #size-cells = <0x0>;
  1725. compatible = "allwinner,sun50i-twi";
  1726. device_type = "twi2";
  1727. reg = <0x0 0x1c2b400 0x0 0x400>;
  1728. interrupts = <0x0 0x8 0x4>;
  1729. clocks = <0x29>;
  1730. clock-frequency = <0x30d40>;
  1731. pinctrl-names = "default", "sleep";
  1732. pinctrl-0 = <0x2a>;
  1733. pinctrl-1 = <0x2b>;
  1734. status = "disabled";
  1735. };
  1736.  
  1737. usbc0@0 {
  1738. device_type = "usbc0";
  1739. compatible = "allwinner,sunxi-otg-manager";
  1740. usb_port_type = <0x2>;
  1741. usb_detect_type = <0x0>;
  1742. usb_id_gpio;
  1743. usb_det_vbus_gpio;
  1744. usb_drv_vbus_gpio;
  1745. usb_host_init_state = <0x0>;
  1746. usb_regulator_io = "nocare";
  1747. usb_wakeup_suspend = <0x0>;
  1748. usb_luns = <0x3>;
  1749. usb_serial_unique = <0x0>;
  1750. usb_serial_number = "20080411";
  1751. rndis_wceis = <0x1>;
  1752. status = "okay";
  1753. };
  1754.  
  1755. udc-controller@0x01c19000 {
  1756. compatible = "allwinner,sunxi-udc";
  1757. reg = <0x0 0x1c19000 0x0 0x1000 0x0 0x1c00000 0x0 0x100>;
  1758. interrupts = <0x0 0x47 0x4>;
  1759. clocks = <0x2c 0x2d>;
  1760. status = "okay";
  1761. };
  1762.  
  1763. ehci0-controller@0x01c1a000 {
  1764. compatible = "allwinner,sunxi-ehci0";
  1765. reg = <0x0 0x1c1a000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1766. interrupts = <0x0 0x48 0x4>;
  1767. clocks = <0x2c 0x2e>;
  1768. hci_ctrl_no = <0x0>;
  1769. status = "okay";
  1770. };
  1771.  
  1772. ohci0-controller@0x01c1a400 {
  1773. compatible = "allwinner,sunxi-ohci0";
  1774. reg = <0x0 0x1c1a000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1775. interrupts = <0x0 0x49 0x4>;
  1776. clocks = <0x2c 0x2f>;
  1777. hci_ctrl_no = <0x0>;
  1778. status = "okay";
  1779. };
  1780.  
  1781. usbc1@0 {
  1782. device_type = "usbc1";
  1783. usb_drv_vbus_gpio;
  1784. usb_host_init_state = <0x1>;
  1785. usb_regulator_io = "nocare";
  1786. usb_wakeup_suspend = <0x0>;
  1787. status = "okay";
  1788. };
  1789.  
  1790. ehci1-controller@0x01c1b000 {
  1791. compatible = "allwinner,sunxi-ehci1";
  1792. reg = <0x0 0x1c1b000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1793. interrupts = <0x0 0x4a 0x4>;
  1794. clocks = <0x30 0x31>;
  1795. hci_ctrl_no = <0x1>;
  1796. status = "okay";
  1797. };
  1798.  
  1799. ohci1-controller@0x01c1b400 {
  1800. compatible = "allwinner,sunxi-ohci1";
  1801. reg = <0x0 0x1c1b000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1802. interrupts = <0x0 0x4b 0x4>;
  1803. clocks = <0x30 0x32>;
  1804. hci_ctrl_no = <0x1>;
  1805. status = "okay";
  1806. };
  1807.  
  1808. usbc2@0 {
  1809. device_type = "usbc2";
  1810. usb_drv_vbus_gpio;
  1811. usb_host_init_state = <0x1>;
  1812. usb_regulator_io = "nocare";
  1813. usb_wakeup_suspend = <0x0>;
  1814. status = "okay";
  1815. };
  1816.  
  1817. ehci2-controller@0x01c1c000 {
  1818. compatible = "allwinner,sunxi-ehci2";
  1819. reg = <0x0 0x1c1c000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1820. interrupts = <0x0 0x4c 0x4>;
  1821. clocks = <0x33 0x34>;
  1822. hci_ctrl_no = <0x2>;
  1823. status = "okay";
  1824. };
  1825.  
  1826. ohci2-controller@0x01c1c400 {
  1827. compatible = "allwinner,sunxi-ohci2";
  1828. reg = <0x0 0x1c1c000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1829. interrupts = <0x0 0x4d 0x4>;
  1830. clocks = <0x33 0x35>;
  1831. hci_ctrl_no = <0x2>;
  1832. status = "okay";
  1833. };
  1834.  
  1835. usbc3@0 {
  1836. device_type = "usbc3";
  1837. usb_drv_vbus_gpio;
  1838. usb_host_init_state = <0x1>;
  1839. usb_regulator_io = "nocare";
  1840. usb_wakeup_suspend = <0x0>;
  1841. status = "okay";
  1842. };
  1843.  
  1844. ehci3-controller@0x01c1d000 {
  1845. compatible = "allwinner,sunxi-ehci3";
  1846. reg = <0x0 0x1c1d000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1847. interrupts = <0x0 0x4e 0x4>;
  1848. clocks = <0x36 0x37>;
  1849. hci_ctrl_no = <0x3>;
  1850. status = "okay";
  1851. };
  1852.  
  1853. ohci3-controller@0x01c1d400 {
  1854. compatible = "allwinner,sunxi-ohci3";
  1855. reg = <0x0 0x1c1d000 0x0 0xfff 0x0 0x1c00000 0x0 0x100 0x0 0x1c19000 0x0 0x1000>;
  1856. interrupts = <0x0 0x4f 0x4>;
  1857. clocks = <0x36 0x38>;
  1858. hci_ctrl_no = <0x3>;
  1859. status = "okay";
  1860. };
  1861.  
  1862. codec@0x01c22c00 {
  1863. compatible = "allwinner,sunxi-internal-codec";
  1864. reg = <0x0 0x1c22c00 0x0 0x478 0x0 0x1f015c0 0x0 0x0>;
  1865. clocks = <0x2 0x39>;
  1866. gpio-spk = <0x3a 0x0 0x10 0x1 0x1 0x1 0x1>;
  1867. spkervol = <0x1f>;
  1868. maingain = <0x4>;
  1869. adcagc_cfg = <0x0>;
  1870. adcdrc_cfg = <0x0>;
  1871. adchpf_cfg = <0x0>;
  1872. dacdrc_cfg = <0x0>;
  1873. dachpf_cfg = <0x0>;
  1874. pa_sleep_time = <0x15e>;
  1875. dac_digital_vol = <0xa0a0>;
  1876. status = "okay";
  1877. linux,phandle = <0x46>;
  1878. phandle = <0x46>;
  1879. };
  1880.  
  1881. cpudai0-controller@0x01c22c00 {
  1882. compatible = "allwinner,sunxi-internal-cpudai";
  1883. reg = <0x0 0x1c22c00 0x0 0x2bc>;
  1884. status = "okay";
  1885. linux,phandle = <0x45>;
  1886. phandle = <0x45>;
  1887. };
  1888.  
  1889. daudio@0x01c22000 {
  1890. compatible = "allwinner,sunxi-daudio";
  1891. reg = <0x0 0x1c22000 0x0 0x58>;
  1892. clocks = <0x2 0x3b>;
  1893. pinctrl-names = "default", "sleep";
  1894. pinctrl-0 = <0x3c>;
  1895. pinctrl-1 = <0x3d>;
  1896. pcm_lrck_period = <0x20>;
  1897. pcm_lrckr_period = <0x1>;
  1898. slot_width_select = <0x20>;
  1899. pcm_lsb_first = <0x0>;
  1900. tx_data_mode = <0x0>;
  1901. rx_data_mode = <0x0>;
  1902. daudio_master = <0x4>;
  1903. audio_format = <0x1>;
  1904. signal_inversion = <0x1>;
  1905. frametype = <0x0>;
  1906. tdm_config = <0x1>;
  1907. tdm_num = <0x0>;
  1908. mclk_div = <0x0>;
  1909. status = "okay";
  1910. linux,phandle = <0x47>;
  1911. phandle = <0x47>;
  1912. };
  1913.  
  1914. daudio@0x01c22400 {
  1915. compatible = "allwinner,sunxi-daudio";
  1916. reg = <0x0 0x1c22400 0x0 0x58>;
  1917. pinctrl-names = "default", "sleep";
  1918. pinctrl-0 = <0x3e>;
  1919. pinctrl-1 = <0x3f>;
  1920. clocks = <0x2 0x40>;
  1921. pcm_lrck_period = <0x20>;
  1922. pcm_lrckr_period = <0x1>;
  1923. slot_width_select = <0x20>;
  1924. pcm_lsb_first = <0x0>;
  1925. tx_data_mode = <0x0>;
  1926. rx_data_mode = <0x0>;
  1927. daudio_master = <0x4>;
  1928. audio_format = <0x1>;
  1929. signal_inversion = <0x1>;
  1930. frametype = <0x0>;
  1931. tdm_config = <0x1>;
  1932. tdm_num = <0x1>;
  1933. mclk_div = <0x0>;
  1934. status = "okay";
  1935. linux,phandle = <0x48>;
  1936. phandle = <0x48>;
  1937. };
  1938.  
  1939. daudio@0x01c22800 {
  1940. compatible = "allwinner,sunxi-tdmhdmi";
  1941. reg = <0x0 0x1c22800 0x0 0x58>;
  1942. clocks = <0x2 0x41>;
  1943. status = "okay";
  1944. linux,phandle = <0x49>;
  1945. phandle = <0x49>;
  1946. };
  1947.  
  1948. spdif-controller@0x01c21000 {
  1949. compatible = "allwinner,sunxi-spdif";
  1950. reg = <0x0 0x1c21000 0x0 0x38>;
  1951. clocks = <0x2 0x42>;
  1952. pinctrl-names = "default", "sleep";
  1953. pinctrl-0 = <0x43>;
  1954. pinctrl-1 = <0x44>;
  1955. status = "okay";
  1956. linux,phandle = <0x4a>;
  1957. phandle = <0x4a>;
  1958. };
  1959.  
  1960. sound@0 {
  1961. compatible = "allwinner,sunxi-codec-machine";
  1962. sunxi,cpudai-controller = <0x45>;
  1963. sunxi,audio-codec = <0x46>;
  1964. status = "okay";
  1965. };
  1966.  
  1967. sound@1 {
  1968. compatible = "allwinner,sunxi-daudio0-machine";
  1969. sunxi,daudio0-controller = <0x47>;
  1970. status = "okay";
  1971. };
  1972.  
  1973. sound@2 {
  1974. compatible = "allwinner,sunxi-daudio1-machine";
  1975. sunxi,daudio1-controller = <0x48>;
  1976. status = "okay";
  1977. };
  1978.  
  1979. sound@3 {
  1980. compatible = "allwinner,sunxi-hdmi-machine";
  1981. sunxi,hdmi-controller = <0x49>;
  1982. status = "okay";
  1983. };
  1984.  
  1985. sound@4 {
  1986. compatible = "allwinner,sunxi-spdif-machine";
  1987. sunxi,spdif-controller = <0x4a>;
  1988. status = "okay";
  1989. };
  1990.  
  1991. spi@01c68000 {
  1992. #address-cells = <0x1>;
  1993. #size-cells = <0x0>;
  1994. compatible = "allwinner,sun50i-spi";
  1995. device_type = "spi0";
  1996. reg = <0x0 0x1c68000 0x0 0x1000>;
  1997. interrupts = <0x0 0x41 0x4>;
  1998. clocks = <0x4 0x4b>;
  1999. clock-frequency = <0x5f5e100>;
  2000. pinctrl-names = "default", "sleep";
  2001. pinctrl-0 = <0x4c 0x4d>;
  2002. pinctrl-1 = <0x4e>;
  2003. spi0_cs_number = <0x1>;
  2004. spi0_cs_bitmap = <0x1>;
  2005. status = "disabled";
  2006. };
  2007.  
  2008. spi@01c69000 {
  2009. #address-cells = <0x1>;
  2010. #size-cells = <0x0>;
  2011. compatible = "allwinner,sun50i-spi";
  2012. device_type = "spi1";
  2013. reg = <0x0 0x1c69000 0x0 0x1000>;
  2014. interrupts = <0x0 0x42 0x4>;
  2015. clocks = <0x4 0x4f>;
  2016. clock-frequency = <0x5f5e100>;
  2017. pinctrl-names = "default", "sleep";
  2018. pinctrl-0 = <0x50 0x51>;
  2019. pinctrl-1 = <0x52>;
  2020. spi1_cs_number = <0x1>;
  2021. spi1_cs_bitmap = <0x1>;
  2022. status = "disabled";
  2023. };
  2024.  
  2025. sdmmc@01C11000 {
  2026. compatible = "allwinner,sunxi-mmc-v4p5x";
  2027. device_type = "sdc2";
  2028. reg = <0x0 0x1c11000 0x0 0x1000>;
  2029. interrupts = <0x0 0x3e 0x104>;
  2030. clocks = <0x6 0x53 0x54 0x55 0x56>;
  2031. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2032. pinctrl-names = "default", "sleep";
  2033. pinctrl-0 = <0x57>;
  2034. pinctrl-1 = <0x58>;
  2035. bus-width = <0x8>;
  2036. max-frequency = <0x2faf080>;
  2037. sdc_tm4_sm0_freq0 = <0x0>;
  2038. sdc_tm4_sm0_freq1 = <0x0>;
  2039. sdc_tm4_sm1_freq0 = <0x0>;
  2040. sdc_tm4_sm1_freq1 = <0x0>;
  2041. sdc_tm4_sm2_freq0 = <0x0>;
  2042. sdc_tm4_sm2_freq1 = <0x0>;
  2043. sdc_tm4_sm3_freq0 = <0x5000000>;
  2044. sdc_tm4_sm3_freq1 = <0x5>;
  2045. sdc_tm4_sm4_freq0 = <0x50000>;
  2046. sdc_tm4_sm4_freq1 = <0x4>;
  2047. status = "okay";
  2048. };
  2049.  
  2050. sdmmc@01c0f000 {
  2051. compatible = "allwinner,sunxi-mmc-v4p1x";
  2052. device_type = "sdc0";
  2053. reg = <0x0 0x1c0f000 0x0 0x1000>;
  2054. interrupts = <0x0 0x3c 0x104>;
  2055. clocks = <0x6 0x53 0x59 0x5a 0x5b>;
  2056. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2057. pinctrl-names = "default", "sleep";
  2058. pinctrl-0 = <0x5c>;
  2059. pinctrl-1 = <0x5d>;
  2060. max-frequency = <0x2faf080>;
  2061. bus-width = <0x4>;
  2062. cd-gpios = <0x3a 0x5 0x6 0x0 0x1 0x2 0x0>;
  2063. status = "okay";
  2064. };
  2065.  
  2066. sdmmc@1C10000 {
  2067. compatible = "allwinner,sunxi-mmc-v4p1x";
  2068. device_type = "sdc1";
  2069. reg = <0x0 0x1c10000 0x0 0x1000>;
  2070. interrupts = <0x0 0x3d 0x104>;
  2071. clocks = <0x6 0x53 0x5e 0x5f 0x60>;
  2072. clock-names = "osc24m", "pll_periph", "mmc", "ahb", "rst";
  2073. pinctrl-names = "default", "sleep";
  2074. pinctrl-0 = <0x61>;
  2075. pinctrl-1 = <0x62>;
  2076. max-frequency = <0x2faf080>;
  2077. bus-width = <0x4>;
  2078. sunxi-dly-52M-ddr4 = <0x1 0x0 0x0 0x0 0x2>;
  2079. sunxi-dly-104M = <0x1 0x0 0x0 0x0 0x1>;
  2080. sunxi-dly-208M = <0x1 0x0 0x0 0x0 0x1>;
  2081. status = "disabled";
  2082. };
  2083.  
  2084. disp@01000000 {
  2085. compatible = "allwinner,sunxi-disp";
  2086. reg = <0x0 0x1000000 0x0 0x300000 0x0 0x1c0c000 0x0 0x7fc 0x0 0x1c0d000 0x0 0x7fc>;
  2087. interrupts = <0x0 0x56 0x104 0x0 0x57 0x104>;
  2088. clocks = <0x63 0x64 0x65>;
  2089. boot_disp = <0x0>;
  2090. fb_base = <0x0>;
  2091. status = "okay";
  2092. };
  2093.  
  2094. lcd0@01c0c000 {
  2095. compatible = "allwinner,sunxi-lcd0";
  2096. pinctrl-names = "active", "sleep";
  2097. status = "okay";
  2098. };
  2099.  
  2100. hdmi@01ee0000 {
  2101. compatible = "allwinner,sunxi-hdmi";
  2102. reg = <0x0 0x1ee0000 0x0 0x20000>;
  2103. clocks = <0x66 0x67>;
  2104. };
  2105.  
  2106. tv0@01c94000 {
  2107. compatible = "allwinner,sunxi-tv";
  2108. reg = <0x0 0x1e40000 0x0 0x1000>;
  2109. clocks = <0x68>;
  2110. status = "disabled";
  2111. };
  2112.  
  2113. tr@01000000 {
  2114. compatible = "allwinner,sun50i-tr";
  2115. reg = <0x0 0x1000000 0x0 0x200bc>;
  2116. interrupts = <0x0 0x60 0x104>;
  2117. clocks = <0x63>;
  2118. status = "okay";
  2119. };
  2120.  
  2121. pwm@01c21400 {
  2122. compatible = "allwinner,sunxi-pwm";
  2123. reg = <0x0 0x1c21400 0x0 0x3c>;
  2124. pwm-number = <0x1>;
  2125. pwm-base = <0x0>;
  2126. pwms = <0x69>;
  2127. };
  2128.  
  2129. pwm0@01c21400 {
  2130. compatible = "allwinner,sunxi-pwm0";
  2131. pinctrl-names = "active", "sleep";
  2132. reg_base = <0x1c21400>;
  2133. reg_busy_offset = <0x0>;
  2134. reg_busy_shift = <0x1c>;
  2135. reg_enable_offset = <0x0>;
  2136. reg_enable_shift = <0x4>;
  2137. reg_clk_gating_offset = <0x0>;
  2138. reg_clk_gating_shift = <0x6>;
  2139. reg_bypass_offset = <0x0>;
  2140. reg_bypass_shift = <0x9>;
  2141. reg_pulse_start_offset = <0x0>;
  2142. reg_pulse_start_shift = <0x8>;
  2143. reg_mode_offset = <0x0>;
  2144. reg_mode_shift = <0x7>;
  2145. reg_polarity_offset = <0x0>;
  2146. reg_polarity_shift = <0x5>;
  2147. reg_period_offset = <0x4>;
  2148. reg_period_shift = <0x10>;
  2149. reg_period_width = <0x10>;
  2150. reg_active_offset = <0x4>;
  2151. reg_active_shift = <0x0>;
  2152. reg_active_width = <0x10>;
  2153. reg_prescal_offset = <0x0>;
  2154. reg_prescal_shift = <0x0>;
  2155. reg_prescal_width = <0x4>;
  2156. linux,phandle = <0x69>;
  2157. phandle = <0x69>;
  2158. };
  2159.  
  2160. s_pwm@1f03800 {
  2161. compatible = "allwinner,sunxi-s_pwm";
  2162. reg = <0x0 0x1f03800 0x0 0x3c>;
  2163. pwm-number = <0x1>;
  2164. pwm-base = <0x10>;
  2165. pwms = <0x6a>;
  2166. };
  2167.  
  2168. spwm0@0x01f03800 {
  2169. compatible = "allwinner,sunxi-pwm16";
  2170. pinctrl-names = "active", "sleep";
  2171. reg_base = <0x1f03800>;
  2172. reg_busy_offset = <0x0>;
  2173. reg_busy_shift = <0x1c>;
  2174. reg_enable_offset = <0x0>;
  2175. reg_enable_shift = <0x4>;
  2176. reg_clk_gating_offset = <0x0>;
  2177. reg_clk_gating_shift = <0x6>;
  2178. reg_bypass_offset = <0x0>;
  2179. reg_bypass_shift = <0x9>;
  2180. reg_pulse_start_offset = <0x0>;
  2181. reg_pulse_start_shift = <0x8>;
  2182. reg_mode_offset = <0x0>;
  2183. reg_mode_shift = <0x7>;
  2184. reg_polarity_offset = <0x0>;
  2185. reg_polarity_shift = <0x5>;
  2186. reg_period_offset = <0x4>;
  2187. reg_period_shift = <0x10>;
  2188. reg_period_width = <0x10>;
  2189. reg_active_offset = <0x4>;
  2190. reg_active_shift = <0x0>;
  2191. reg_active_width = <0x10>;
  2192. reg_prescal_offset = <0x0>;
  2193. reg_prescal_shift = <0x0>;
  2194. reg_prescal_width = <0x4>;
  2195. linux,phandle = <0x6a>;
  2196. phandle = <0x6a>;
  2197. };
  2198.  
  2199. boot_disp {
  2200. compatible = "allwinner,boot_disp";
  2201. };
  2202.  
  2203. ac200 {
  2204. compatible = "allwinner,sunxi-ac200";
  2205. clocks = <0x64>;
  2206. pinctrl-names = "active", "sleep";
  2207. status = "okay";
  2208. };
  2209.  
  2210. cci@0x01cb3000 {
  2211. compatible = "allwinner,sunxi-csi_cci";
  2212. reg = <0x0 0x1cb3000 0x0 0x1000>;
  2213. interrupts = <0x0 0x55 0x4>;
  2214. status = "okay";
  2215. };
  2216.  
  2217. csi_res@0x01cb0000 {
  2218. compatible = "allwinner,sunxi-csi";
  2219. reg = <0x0 0x1cb0000 0x0 0x1000>;
  2220. clocks = <0x6b 0x6c 0x6d 0x4 0x6 0x5>;
  2221. clocks-index = <0x0 0x1 0x2 0x3 0x4 0x5>;
  2222. status = "okay";
  2223. };
  2224.  
  2225. isp@0x01cb8000 {
  2226. compatible = "allwinner,sunxi-isp";
  2227. reg = <0x0 0x1cb8000 0x0 0x1000>;
  2228. status = "okay";
  2229. };
  2230.  
  2231. vfe@0 {
  2232. device_type = "csi0";
  2233. compatible = "allwinner,sunxi-vfe";
  2234. interrupts = <0x0 0x54 0x4>;
  2235. pinctrl-names = "default", "sleep";
  2236. pinctrl-0 = <0x6e>;
  2237. pinctrl-1 = <0x6f>;
  2238. cci_sel = <0x0>;
  2239. csi_sel = <0x0>;
  2240. mipi_sel = <0x0>;
  2241. isp_sel = <0x0>;
  2242. csi0_sensor_list = <0x0>;
  2243. csi0_mck = <0x3a 0x4 0x1 0x1 0x0 0x1 0x0>;
  2244. status = "okay";
  2245.  
  2246. dev@0 {
  2247. csi0_dev0_mname = "gc2035";
  2248. csi0_dev0_twi_addr = <0x78>;
  2249. csi0_dev0_pos = "rear";
  2250. csi0_dev0_isp_used = <0x1>;
  2251. csi0_dev0_fmt = <0x0>;
  2252. csi0_dev0_stby_mode = <0x0>;
  2253. csi0_dev0_vflip = <0x0>;
  2254. csi0_dev0_hflip = <0x0>;
  2255. csi0_dev0_iovdd = [00];
  2256. csi0_dev0_iovdd_vol = <0x2ab980>;
  2257. csi0_dev0_avdd = [00];
  2258. csi0_dev0_avdd_vol = <0x2ab980>;
  2259. csi0_dev0_dvdd = [00];
  2260. csi0_dev0_dvdd_vol = <0x16e360>;
  2261. csi0_dev0_afvdd = [00];
  2262. csi0_dev0_afvdd_vol;
  2263. csi0_dev0_power_en = <0x3a 0x0 0x11 0x1 0x0 0x1 0x0>;
  2264. csi0_dev0_reset = <0x3a 0x4 0xe 0x1 0x0 0x1 0x0>;
  2265. csi0_dev0_pwdn = <0x3a 0x4 0xf 0x1 0x0 0x1 0x0>;
  2266. csi0_dev0_flash_used = <0x1>;
  2267. csi0_dev0_flash_type = <0x2>;
  2268. csi0_dev0_flash_en;
  2269. csi0_dev0_flash_mode;
  2270. csi0_dev0_flvdd = [00];
  2271. csi0_dev0_flvdd_vol = <0x325aa0>;
  2272. csi0_dev0_af_pwdn;
  2273. csi0_dev0_act_used = <0x0>;
  2274. csi0_dev0_act_name = [00];
  2275. csi0_dev0_act_slave = <0x18>;
  2276. status = "okay";
  2277. };
  2278.  
  2279. dev@1 {
  2280. csi0_dev1_mname = [00];
  2281. csi0_dev1_twi_addr = <0x78>;
  2282. csi0_dev1_pos = "rear";
  2283. csi0_dev1_isp_used = <0x1>;
  2284. csi0_dev1_fmt = <0x0>;
  2285. csi0_dev1_stby_mode = <0x0>;
  2286. csi0_dev1_vflip = <0x0>;
  2287. csi0_dev1_hflip = <0x0>;
  2288. csi0_dev1_iovdd = "iovdd-csi";
  2289. csi0_dev1_iovdd_vol = <0x2ab980>;
  2290. csi0_dev1_avdd = "avdd-csi";
  2291. csi0_dev1_avdd_vol = <0x2ab980>;
  2292. csi0_dev1_dvdd = "dvdd-csi-18";
  2293. csi0_dev1_dvdd_vol = <0x16e360>;
  2294. csi0_dev1_afvdd = [00];
  2295. csi0_dev1_afvdd_vol;
  2296. csi0_dev1_power_en;
  2297. csi0_dev1_reset;
  2298. csi0_dev1_pwdn;
  2299. csi0_dev1_flash_used = <0x1>;
  2300. csi0_dev1_flash_type = <0x2>;
  2301. csi0_dev1_flash_en;
  2302. csi0_dev1_flash_mode;
  2303. csi0_dev1_flvdd = "vdd-csi-led";
  2304. csi0_dev1_flvdd_vol = <0x325aa0>;
  2305. csi0_dev1_af_pwdn;
  2306. csi0_dev1_act_used = <0x0>;
  2307. csi0_dev1_act_name = "ad5820_act";
  2308. csi0_dev1_act_slave = <0x18>;
  2309. status = "disabled";
  2310. };
  2311. };
  2312.  
  2313. vdevice@0 {
  2314. compatible = "allwinner,sun50i-vdevice";
  2315. device_type = "Vdevice";
  2316. pinctrl-names = "default";
  2317. pinctrl-0 = <0x70>;
  2318. test-gpios = <0x3a 0x0 0x0 0x1 0x2 0x2 0x1>;
  2319. status = "okay";
  2320. };
  2321.  
  2322. ce@1c15000 {
  2323. compatible = "allwinner,sunxi-ce";
  2324. reg = <0x0 0x1c15000 0x0 0x80 0x0 0x1c15800 0x0 0x80>;
  2325. interrupts = <0x0 0x5e 0xff01 0x0 0x50 0xff01>;
  2326. clock-frequency = <0x11e1a300 0xbebc200>;
  2327. clocks = <0x71 0x4>;
  2328. };
  2329.  
  2330. deinterlace@0x01e00000 {
  2331. #address-cells = <0x1>;
  2332. #size-cells = <0x0>;
  2333. compatible = "allwinner,sunxi-deinterlace";
  2334. reg = <0x0 0x1e00000 0x0 0x77c>;
  2335. interrupts = <0x0 0x5d 0x4>;
  2336. clocks = <0x72 0x4>;
  2337. status = "okay";
  2338. };
  2339.  
  2340. smartcard@0x01c2c400 {
  2341. #address-cells = <0x1>;
  2342. #size-cells = <0x0>;
  2343. compatible = "allwinner,sunxi-scr";
  2344. device_type = "scr0";
  2345. reg = <0x0 0x1c2c400 0x0 0x400>;
  2346. interrupts = <0x0 0x53 0x4>;
  2347. clocks = <0x73 0x74>;
  2348. clock-frequency = <0x16e3600>;
  2349. pinctrl-names = "default", "sleep";
  2350. pinctrl-0 = <0x75 0x76>;
  2351. pinctrl-1 = <0x77>;
  2352. status = "okay";
  2353. };
  2354.  
  2355. smartcard@0x01c2c800 {
  2356. #address-cells = <0x1>;
  2357. #size-cells = <0x0>;
  2358. compatible = "allwinner,sunxi-scr";
  2359. device_type = "scr1";
  2360. reg = <0x0 0x1c2c800 0x0 0x400>;
  2361. interrupts = <0x0 0x59 0x4>;
  2362. clocks = <0x78 0x74>;
  2363. clock-frequency = <0x16e3600>;
  2364. pinctrl-names = "default", "sleep";
  2365. pinctrl-0 = <0x79 0x7a>;
  2366. pinctrl-1 = <0x7b>;
  2367. status = "disabled";
  2368. };
  2369.  
  2370. pmu@0 {
  2371. interrupts = <0x0 0x20 0x4>;
  2372. status = "okay";
  2373.  
  2374. powerkey@0 {
  2375. status = "okay";
  2376. };
  2377.  
  2378. regulator@0 {
  2379. status = "okay";
  2380. };
  2381.  
  2382. axp_gpio@0 {
  2383. gpio-controller;
  2384. #size-cells = <0x0>;
  2385. #gpio-cells = <0x6>;
  2386. status = "okay";
  2387. device_type = "axp_pio";
  2388. };
  2389.  
  2390. charger@0 {
  2391. status = "disabled";
  2392. };
  2393. };
  2394.  
  2395. nmi@0x01f00c00 {
  2396. #address-cells = <0x1>;
  2397. #size-cells = <0x0>;
  2398. compatible = "allwinner,sunxi-nmi";
  2399. reg = <0x0 0x1f00c00 0x0 0x50>;
  2400. nmi_irq_ctrl = <0xc>;
  2401. nmi_irq_en = <0x40>;
  2402. nmi_irq_status = <0x10>;
  2403. nmi_irq_mask = <0x50>;
  2404. status = "okay";
  2405. };
  2406.  
  2407. nand0@01c03000 {
  2408. compatible = "allwinner,sun50iw2-nand";
  2409. device_type = "nand0";
  2410. reg = <0x0 0x1c03000 0x0 0x1000>;
  2411. interrupts = <0x0 0x46 0x4>;
  2412. clocks = <0x4 0x7c>;
  2413. pinctrl-names = "default", "sleep";
  2414. pinctrl-0 = <0x7d 0x7e>;
  2415. pinctrl-1 = <0x7f>;
  2416. nand0_regulator1 = "vcc-nand";
  2417. nand0_regulator2 = "none";
  2418. nand0_cache_level = <0x55aaaa55>;
  2419. nand0_flush_cache_num = <0x55aaaa55>;
  2420. nand0_capacity_level = <0x55aaaa55>;
  2421. nand0_id_number_ctl = <0x55aaaa55>;
  2422. nand0_print_level = <0x55aaaa55>;
  2423. nand0_p0 = <0x55aaaa55>;
  2424. nand0_p1 = <0x55aaaa55>;
  2425. nand0_p2 = <0x55aaaa55>;
  2426. nand0_p3 = <0x55aaaa55>;
  2427. status = "okay";
  2428. };
  2429.  
  2430. ts0@01c06000 {
  2431. compatible = "allwinner,sun50i-tsc";
  2432. device_type = "ts0";
  2433. reg = <0x0 0x1c06000 0x0 0x1000>;
  2434. interrupts = <0x0 0x51 0x4>;
  2435. clocks = <0x4 0x80>;
  2436. pinctrl-names = "ts0-default", "ts1-default", "ts2-default", "ts3-default", "ts0-sleep", "ts1-sleep", "ts2-sleep", "ts3-sleep";
  2437. pinctrl-0 = <0x81>;
  2438. pinctrl-1 = <0x82>;
  2439. pinctrl-2 = <0x83>;
  2440. pinctrl-3 = <0x84>;
  2441. pinctrl-4 = <0x85>;
  2442. pinctrl-5 = <0x86>;
  2443. pinctrl-6 = <0x87>;
  2444. pinctrl-7 = <0x88>;
  2445. ts0config = <0x1>;
  2446. ts1config = <0x0>;
  2447. ts2config = <0x1>;
  2448. ts3config = <0x0>;
  2449. status = "okay";
  2450. };
  2451.  
  2452. thermal_sensor {
  2453. compatible = "allwinner,thermal_sensor";
  2454. reg = <0x0 0x1c25000 0x0 0x84>;
  2455. interrupts = <0x0 0x1f 0x0>;
  2456. clocks = <0x6 0x89>;
  2457. sensor_num = <0x2>;
  2458. shut_temp = <0x6e>;
  2459. status = "okay";
  2460.  
  2461. combine0 {
  2462. #thermal-sensor-cells = <0x1>;
  2463. combine_cnt = <0x2>;
  2464. combine_type = "max";
  2465. combine_chn = <0x0 0x1>;
  2466. linux,phandle = <0x8a>;
  2467. phandle = <0x8a>;
  2468. };
  2469. };
  2470.  
  2471. cpu_budget_cool {
  2472. compatible = "allwinner,budget_cooling";
  2473. #cooling-cells = <0x2>;
  2474. status = "okay";
  2475. state_cnt = <0x5>;
  2476. cluster_num = <0x1>;
  2477. state0 = <0xf6180 0x4>;
  2478. state1 = <0xc7380 0x4>;
  2479. state2 = <0x9e340 0x2>;
  2480. state3 = <0x75300 0x2>;
  2481. state4 = <0x75300 0x1>;
  2482. linux,phandle = <0x8c>;
  2483. phandle = <0x8c>;
  2484. };
  2485.  
  2486. gpu_cooling {
  2487. compatible = "allwinner,gpu_cooling";
  2488. reg = <0x0 0x0 0x0 0x0>;
  2489. #cooling-cells = <0x2>;
  2490. status = "okay";
  2491. state_cnt = <0x4>;
  2492. state0 = <0x1c8>;
  2493. state1 = <0x180>;
  2494. state2 = <0x108>;
  2495. state3 = <0x90>;
  2496. linux,phandle = <0x90>;
  2497. phandle = <0x90>;
  2498. };
  2499.  
  2500. thermal-zones {
  2501.  
  2502. soc_thermal {
  2503. polling-delay-passive = <0x3e8>;
  2504. polling-delay = <0x2710>;
  2505. thermal-sensors = <0x8a 0x0>;
  2506.  
  2507. trips {
  2508.  
  2509. t0 {
  2510. temperature = <0x5a>;
  2511. type = "passive";
  2512. hysteresis = <0x0>;
  2513. linux,phandle = <0x8b>;
  2514. phandle = <0x8b>;
  2515. };
  2516.  
  2517. t1 {
  2518. temperature = <0x64>;
  2519. type = "passive";
  2520. hysteresis = <0x0>;
  2521. linux,phandle = <0x8d>;
  2522. phandle = <0x8d>;
  2523. };
  2524.  
  2525. t2 {
  2526. temperature = <0x6e>;
  2527. type = "passive";
  2528. hysteresis = <0x0>;
  2529. linux,phandle = <0x8e>;
  2530. phandle = <0x8e>;
  2531. };
  2532.  
  2533. t3 {
  2534. temperature = <0x50>;
  2535. type = "passive";
  2536. hysteresis = <0x0>;
  2537. linux,phandle = <0x8f>;
  2538. phandle = <0x8f>;
  2539. };
  2540.  
  2541. t4 {
  2542. temperature = <0x5a>;
  2543. type = "passive";
  2544. hysteresis = <0x0>;
  2545. linux,phandle = <0x91>;
  2546. phandle = <0x91>;
  2547. };
  2548.  
  2549. t5 {
  2550. temperature = <0x64>;
  2551. type = "passive";
  2552. hysteresis = <0x0>;
  2553. linux,phandle = <0x92>;
  2554. phandle = <0x92>;
  2555. };
  2556.  
  2557. t6 {
  2558. temperature = <0x73>;
  2559. type = "critical";
  2560. hysteresis = <0x0>;
  2561. };
  2562. };
  2563.  
  2564. cooling-maps {
  2565.  
  2566. bind0 {
  2567. contribution = <0x0>;
  2568. trip = <0x8b>;
  2569. cooling-device = <0x8c 0x1 0x1>;
  2570. };
  2571.  
  2572. bind1 {
  2573. contribution = <0x0>;
  2574. trip = <0x8d>;
  2575. cooling-device = <0x8c 0x2 0x2>;
  2576. };
  2577.  
  2578. bind2 {
  2579. contribution = <0x0>;
  2580. trip = <0x8e>;
  2581. cooling-device = <0x8c 0x3 0x4>;
  2582. };
  2583.  
  2584. bind3 {
  2585. contribution = <0x0>;
  2586. trip = <0x8f>;
  2587. cooling-device = <0x90 0x1 0x1>;
  2588. };
  2589.  
  2590. bind4 {
  2591. contribution = <0x0>;
  2592. trip = <0x91>;
  2593. cooling-device = <0x90 0x2 0x2>;
  2594. };
  2595.  
  2596. bind5 {
  2597. contribution = <0x0>;
  2598. trip = <0x92>;
  2599. cooling-device = <0x90 0x3 0x3>;
  2600. };
  2601. };
  2602. };
  2603. };
  2604.  
  2605. keyboard {
  2606. compatible = "allwinner,keyboard_2000mv";
  2607. reg = <0x0 0x1c21800 0x0 0x400>;
  2608. interrupts = <0x0 0x1e 0x0>;
  2609. status = "okay";
  2610. key_cnt = <0x5>;
  2611. key1 = <0xf0 0x73>;
  2612. key2 = <0x1f4 0x72>;
  2613. key3 = <0x2bc 0x8b>;
  2614. key4 = <0x37a 0x1c>;
  2615. key5 = <0x7d0 0x66>;
  2616. };
  2617.  
  2618. eth@01c30000 {
  2619. compatible = "allwinner,sunxi-gmac";
  2620. reg = <0x0 0x1c30000 0x0 0x4000 0x0 0x1c00030 0x0 0x1>;
  2621. pinctrl-names = "default";
  2622. pinctrl-0 = <0x93>;
  2623. interrupts = <0x0 0x52 0x4>;
  2624. interrupt-names = "gmacirq";
  2625. clocks = <0x94 0x95>;
  2626. clock-names = "gmac", "ephy";
  2627. phy-mode = "rgmii";
  2628. tx-delay = <0x7>;
  2629. rx-delay = <0x1f>;
  2630. gmac_power1 = "axp81x_dldo2:2500000";
  2631. gmac_power2 = "axp81x_eldo2:1800000";
  2632. gmac_power3 = "axp81x_fldo1:1200000";
  2633. phy_power_on = <0x3a 0x3 0x6 0x1 0x0 0x0 0x0>;
  2634. status = "okay";
  2635. };
  2636. };
  2637.  
  2638. aliases {
  2639. serial0 = "/soc@01c00000/uart@01c28000";
  2640. serial1 = "/soc@01c00000/uart@01c28400";
  2641. serial2 = "/soc@01c00000/uart@01c28800";
  2642. serial3 = "/soc@01c00000/uart@01c28c00";
  2643. twi0 = "/soc@01c00000/twi@0x01c2ac00";
  2644. twi1 = "/soc@01c00000/twi@0x01c2b000";
  2645. twi2 = "/soc@01c00000/twi@0x01c2b400";
  2646. spi0 = "/soc@01c00000/spi@01c68000";
  2647. spi1 = "/soc@01c00000/spi@01c69000";
  2648. scr0 = "/soc@01c00000/smartcard@0x01c2c400";
  2649. scr1 = "/soc@01c00000/smartcard@0x01c2c800";
  2650. global_timer0 = "/soc@01c00000/timer@1c20c00";
  2651. cci0 = "/soc@01c00000/cci@0x01cb3000";
  2652. csi_res0 = "/soc@01c00000/csi_res@0x01cb0000";
  2653. isp0 = "/soc@01c00000/isp@0x01cb8000";
  2654. vfe0 = "/soc@01c00000/vfe@0";
  2655. mmc0 = "/soc@01c00000/sdmmc@01c0f000";
  2656. mmc2 = "/soc@01c00000/sdmmc@01C11000";
  2657. nand0 = "/soc@01c00000/nand0@01c03000";
  2658. disp = "/soc@01c00000/disp@01000000";
  2659. lcd0 = "/soc@01c00000/lcd0@01c0c000";
  2660. hdmi = "/soc@01c00000/hdmi@01ee0000";
  2661. pwm = "/soc@01c00000/pwm@01c21400";
  2662. pwm0 = "/soc@01c00000/pwm0@01c21400";
  2663. tv0 = "/soc@01c00000/tv0@01c94000";
  2664. s_pwm = "/soc@01c00000/s_pwm@1f03800";
  2665. spwm0 = "/soc@01c00000/spwm0@0x01f03800";
  2666. boot_disp = "/soc@01c00000/boot_disp";
  2667. charger0 = "/soc@01c00000/pmu@0/charger@0";
  2668. regulator0 = "/soc@01c00000/pmu@0/regulator@0";
  2669. };
  2670.  
  2671. chosen {
  2672. bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
  2673. linux,initrd-start = <0x0 0x0>;
  2674. linux,initrd-end = <0x0 0x0>;
  2675. };
  2676.  
  2677. cpus {
  2678. #address-cells = <0x2>;
  2679. #size-cells = <0x0>;
  2680.  
  2681. cpu@0 {
  2682. device_type = "cpu";
  2683. compatible = "arm,cortex-a53", "arm,armv8";
  2684. reg = <0x0 0x0>;
  2685. enable-method = "psci";
  2686. cpufreq_tbl = <0x75300 0x9e340 0xafc80 0xc7380 0xdea80 0xf6180 0x10d880 0x119400 0x124f80>;
  2687. clock-latency = <0x1e8480>;
  2688. clock-frequency = <0x3c14dc00>;
  2689. cpu-idle-states = <0x96 0x97 0x98>;
  2690. };
  2691.  
  2692. cpu@1 {
  2693. device_type = "cpu";
  2694. compatible = "arm,cortex-a53", "arm,armv8";
  2695. reg = <0x0 0x1>;
  2696. enable-method = "psci";
  2697. clock-frequency = <0x3c14dc00>;
  2698. cpu-idle-states = <0x96 0x97 0x98>;
  2699. };
  2700.  
  2701. cpu@2 {
  2702. device_type = "cpu";
  2703. compatible = "arm,cortex-a53", "arm,armv8";
  2704. reg = <0x0 0x2>;
  2705. enable-method = "psci";
  2706. clock-frequency = <0x3c14dc00>;
  2707. cpu-idle-states = <0x96 0x97 0x98>;
  2708. };
  2709.  
  2710. cpu@3 {
  2711. device_type = "cpu";
  2712. compatible = "arm,cortex-a53", "arm,armv8";
  2713. reg = <0x0 0x3>;
  2714. enable-method = "psci";
  2715. clock-frequency = <0x3c14dc00>;
  2716. cpu-idle-states = <0x96 0x97 0x98>;
  2717. };
  2718.  
  2719. idle-states {
  2720. entry-method = "arm,psci";
  2721.  
  2722. cpu-sleep-0 {
  2723. compatible = "arm,idle-state";
  2724. arm,psci-suspend-param = <0x10000>;
  2725. entry-latency-us = <0x28>;
  2726. exit-latency-us = <0x64>;
  2727. min-residency-us = <0x96>;
  2728. linux,phandle = <0x96>;
  2729. phandle = <0x96>;
  2730. };
  2731.  
  2732. cluster-sleep-0 {
  2733. compatible = "arm,idle-state";
  2734. arm,psci-suspend-param = <0x1010000>;
  2735. entry-latency-us = <0x1f4>;
  2736. exit-latency-us = <0x3e8>;
  2737. min-residency-us = <0x9c4>;
  2738. linux,phandle = <0x97>;
  2739. phandle = <0x97>;
  2740. };
  2741.  
  2742. sys-sleep-0 {
  2743. compatible = "arm,idle-state";
  2744. arm,psci-suspend-param = <0x2010000>;
  2745. entry-latency-us = <0x3e8>;
  2746. exit-latency-us = <0x7d0>;
  2747. min-residency-us = <0x1194>;
  2748. linux,phandle = <0x98>;
  2749. phandle = <0x98>;
  2750. };
  2751. };
  2752. };
  2753.  
  2754. psci {
  2755. compatible = "arm,psci-0.2";
  2756. method = "smc";
  2757. psci_version = <0x84000000>;
  2758. cpu_suspend = <0xc4000001>;
  2759. cpu_off = <0x84000002>;
  2760. cpu_on = <0xc4000003>;
  2761. affinity_info = <0xc4000004>;
  2762. migrate = <0xc4000005>;
  2763. migrate_info_type = <0x84000006>;
  2764. migrate_info_up_cpu = <0xc4000007>;
  2765. system_off = <0x84000008>;
  2766. system_reset = <0x84000009>;
  2767. };
  2768.  
  2769. n_brom {
  2770. compatible = "allwinner,n-brom";
  2771. reg = <0x0 0x0 0x0 0xc000>;
  2772. };
  2773.  
  2774. s_brom {
  2775. compatible = "allwinner,s-brom";
  2776. reg = <0x0 0x0 0x0 0x10000>;
  2777. };
  2778.  
  2779. sram_ctrl {
  2780. device_type = "sram_ctrl";
  2781. compatible = "allwinner,sram_ctrl";
  2782. reg = <0x0 0x1c00000 0x0 0x100>;
  2783. };
  2784.  
  2785. sram_a1 {
  2786. compatible = "allwinner,sram_a1";
  2787. reg = <0x0 0x10000 0x0 0x10000>;
  2788. };
  2789.  
  2790. sram_a2 {
  2791. compatible = "allwinner,sram_a2";
  2792. reg = <0x0 0x40000 0x0 0x14000>;
  2793. };
  2794.  
  2795. prcm {
  2796. compatible = "allwinner,prcm";
  2797. reg = <0x0 0x1f01400 0x0 0x400>;
  2798. };
  2799.  
  2800. cpuscfg {
  2801. compatible = "allwinner,cpuscfg";
  2802. reg = <0x0 0x1f01c00 0x0 0x400>;
  2803. };
  2804.  
  2805. ion {
  2806. compatible = "allwinner,sunxi-ion";
  2807.  
  2808. system {
  2809. type = <0x0>;
  2810. };
  2811.  
  2812. system_contig {
  2813. type = <0x1>;
  2814. };
  2815.  
  2816. cma {
  2817. type = <0x4>;
  2818. };
  2819. };
  2820.  
  2821. dram {
  2822. compatible = "allwinner,dram";
  2823. clocks = <0x99>;
  2824. clock-names = "pll_ddr";
  2825. dram_clk = <0x2a0>;
  2826. dram_type = <0x3>;
  2827. dram_zq = <0x3f3fdd>;
  2828. dram_odt_en = <0x1>;
  2829. dram_para1 = <0x10f41000>;
  2830. dram_para2 = <0x1200>;
  2831. dram_mr0 = <0x1a50>;
  2832. dram_mr1 = <0x40>;
  2833. dram_mr2 = <0x10>;
  2834. dram_mr3 = <0x0>;
  2835. dram_tpr0 = <0x4e214ea>;
  2836. dram_tpr1 = <0x4214ad>;
  2837. dram_tpr2 = <0x10a75030>;
  2838. dram_tpr3 = <0x0>;
  2839. dram_tpr4 = <0x0>;
  2840. dram_tpr5 = <0x0>;
  2841. dram_tpr6 = <0x0>;
  2842. dram_tpr7 = <0x0>;
  2843. dram_tpr8 = <0x0>;
  2844. dram_tpr9 = <0x0>;
  2845. dram_tpr10 = <0x0>;
  2846. dram_tpr11 = <0x0>;
  2847. dram_tpr12 = <0xa8>;
  2848. dram_tpr13 = <0x823>;
  2849. };
  2850.  
  2851. memory@40000000 {
  2852. device_type = "memory";
  2853. reg = <0x0 0x41000000 0x0 0x3f000000>;
  2854. };
  2855.  
  2856. interrupt-controller@1c81000 {
  2857. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  2858. #interrupt-cells = <0x3>;
  2859. #address-cells = <0x0>;
  2860. device_type = "gic";
  2861. interrupt-controller;
  2862. reg = <0x0 0x1c81000 0x0 0x1000 0x0 0x1c82000 0x0 0x2000 0x0 0x1c84000 0x0 0x2000 0x0 0x1c86000 0x0 0x2000>;
  2863. interrupts = <0x1 0x9 0xf04>;
  2864. linux,phandle = <0x1>;
  2865. phandle = <0x1>;
  2866. };
  2867.  
  2868. sunxi-sid@1c14000 {
  2869. compatible = "allwinner,sunxi-sid";
  2870. device_type = "sid";
  2871. reg = <0x0 0x1c14000 0x0 0x200>;
  2872. };
  2873.  
  2874. sunxi-chipid@1c14200 {
  2875. compatible = "allwinner,sunxi-chipid";
  2876. device_type = "chipid";
  2877. reg = <0x0 0x1c14200 0x0 0x200>;
  2878. };
  2879.  
  2880. timer {
  2881. compatible = "arm,armv8-timer";
  2882. interrupts = <0x1 0xd 0xff01 0x1 0xe 0xff01 0x1 0xb 0xff01 0x1 0xa 0xff01>;
  2883. clock-frequency = <0x16e3600>;
  2884. };
  2885.  
  2886. pmu {
  2887. compatible = "arm,armv8-pmuv3";
  2888. interrupts = <0x0 0x78 0x4 0x0 0x79 0x4 0x0 0x7a 0x4 0x0 0x7b 0x4>;
  2889. };
  2890.  
  2891. dvfs_table {
  2892. compatible = "allwinner,dvfs_table";
  2893. max_freq = <0x47868c00>;
  2894. min_freq = <0x1c9c3800>;
  2895. lv_count = <0x8>;
  2896. lv1_freq = <0x47868c00>;
  2897. lv1_volt = <0x44c>;
  2898. lv2_freq = <0x3c14dc00>;
  2899. lv2_volt = <0x44c>;
  2900. lv3_freq = <0x30a32c00>;
  2901. lv3_volt = <0x44c>;
  2902. lv4_freq = <0x269fb200>;
  2903. lv4_volt = <0x44c>;
  2904. lv5_freq = <0x0>;
  2905. lv5_volt = <0x44c>;
  2906. lv6_freq = <0x0>;
  2907. lv6_volt = <0x44c>;
  2908. lv7_freq = <0x0>;
  2909. lv7_volt = <0x44c>;
  2910. lv8_freq = <0x0>;
  2911. lv8_volt = <0x44c>;
  2912. };
  2913.  
  2914. dramfreq {
  2915. compatible = "allwinner,sunxi-dramfreq";
  2916. reg = <0x0 0x1c62000 0x0 0x1000 0x0 0x1c63000 0x0 0x1000 0x0 0x1c20000 0x0 0x800>;
  2917. };
  2918.  
  2919. wlan {
  2920. compatible = "allwinner,sunxi-wlan";
  2921. clocks = <0x9d>;
  2922. wlan_power = "vcc-wifi";
  2923. wlan_io_regulator = "vcc-wifi-io";
  2924. wlan_busnum = <0x1>;
  2925. wlan_regon = <0x9e 0x2 0xe 0x1 0x1 0x1 0x0>;
  2926. wlan_hostwake = <0x9e 0xb 0x7 0x0 0x0 0x0 0x0>;
  2927. status = "disabled";
  2928. };
  2929.  
  2930. bt {
  2931. compatible = "allwinner,sunxi-bt";
  2932. clocks = <0x9d>;
  2933. bt_power = "vcc-wifi";
  2934. bt_io_regulator = "vcc-wifi-io";
  2935. bt_rst_n = <0x9e 0x2 0x10 0x1 0x1 0x1 0x0>;
  2936. status = "disabled";
  2937. };
  2938.  
  2939. btlpm {
  2940. compatible = "allwinner,sunxi-btlpm";
  2941. uart_index = <0x1>;
  2942. bt_wake = <0x9e 0x2 0xf 0x1 0x1 0x1 0x1>;
  2943. bt_hostwake = <0x9e 0xb 0x6 0x0 0x0 0x0 0x0>;
  2944. status = "disabled";
  2945. };
  2946. };
  2947. root@Orangepi:/boot/orangepi#
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