/dts-v1/;

/ {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	compatible = "rockchip,rk3288";
	rockchip,sram = <0x1>;
	interrupt-parent = <0x2>;

	chosen {
	};

	aliases {
		serial0 = "/serial@ff180000";
		serial1 = "/serial@ff190000";
		serial2 = "/serial@ff690000";
		serial3 = "/serial@ff1b0000";
		serial4 = "/serial@ff1c0000";
		i2c0 = "/i2c@ff650000";
		i2c1 = "/i2c@ff140000";
		i2c2 = "/i2c@ff660000";
		i2c3 = "/i2c@ff150000";
		i2c4 = "/i2c@ff160000";
		i2c5 = "/i2c@ff170000";
		lcdc0 = "/lcdc@ff930000";
		lcdc1 = "/lcdc@ff940000";
		spi0 = "/spi@ff110000";
		spi1 = "/spi@ff120000";
		spi2 = "/spi@ff130000";
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	pinctrl@ff770000 {
		compatible = "rockchip,rk3288-pinctrl";
		reg = <0xff770000 0x140 0xff770140 0x80 0xff7701c0 0x80>;
		reg-names = "base", "pull", "drv";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;
		init-gpios = <0x3 0x1 0x0 0x4 0x9 0x0 0x5 0x8 0x0>;

		gpio0@ff750000 {
			compatible = "rockchip,rk3288-gpio-bank0";
			reg = <0xff750000 0x100 0xff730084 0xc 0xff730064 0xc 0xff730070 0xc>;
			reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
			interrupts = <0x0 0x51 0x4>;
			clocks = <0x6 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			linux,phandle = <0x95>;
			phandle = <0x95>;
		};

		gpio1@ff780000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff780000 0x100>;
			interrupts = <0x0 0x52 0x4>;
			clocks = <0x7 0x1>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio2@ff790000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff790000 0x100>;
			interrupts = <0x0 0x53 0x4>;
			clocks = <0x7 0x2>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			linux,phandle = <0x96>;
			phandle = <0x96>;
		};

		gpio3@ff7a0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7a0000 0x100>;
			interrupts = <0x0 0x54 0x4>;
			clocks = <0x7 0x3>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio4@ff7b0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7b0000 0x100>;
			interrupts = <0x0 0x55 0x4>;
			clocks = <0x7 0x4>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			linux,phandle = <0x5>;
			phandle = <0x5>;
		};

		gpio5@ff7c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7c0000 0x100>;
			interrupts = <0x0 0x56 0x4>;
			clocks = <0x7 0x5>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio6@ff7d0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7d0000 0x100>;
			interrupts = <0x0 0x57 0x4>;
			clocks = <0x7 0x6>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			linux,phandle = <0x81>;
			phandle = <0x81>;
		};

		gpio7@ff7e0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7e0000 0x100>;
			interrupts = <0x0 0x58 0x4>;
			clocks = <0x7 0x7>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			linux,phandle = <0x4>;
			phandle = <0x4>;
		};

		gpio8@ff7f0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7f0000 0x100>;
			interrupts = <0x0 0x59 0x4>;
			clocks = <0x7 0x8>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			linux,phandle = <0x3>;
			phandle = <0x3>;
		};

		gpio15@ff7f2000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff7f2000 0x100>;
			interrupts = <0x0 0x7f 0x4>;
			clocks = <0x7 0x8>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		pcfg_pull_up {
			bias-pull-up;
		};

		pcfg_pull_down {
			bias-pull-down;
		};

		pcfg_pull_none {
			bias-disable;
		};

		gpio4_uart0 {

			uart0-xfer {
				rockchip,pins = <0x4c01 0x4c11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x9f>;
				phandle = <0x9f>;
			};

			uart0-cts {
				rockchip,pins = <0x4c21>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xa0>;
				phandle = <0xa0>;
			};

			uart0-rts {
				rockchip,pins = <0x4c31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x112>;
				phandle = <0x112>;
			};

			uart0-rts-gpio {
				rockchip,pins = <0x4c30>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x113>;
				phandle = <0x113>;
			};
		};

		gpio5_uart1 {

			uart1-xfer {
				rockchip,pins = <0x5b01 0x5b11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xa2>;
				phandle = <0xa2>;
			};

			uart1-cts {
				rockchip,pins = <0x5b21>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xa3>;
				phandle = <0xa3>;
			};

			uart1-rts {
				rockchip,pins = <0x5b31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xa4>;
				phandle = <0xa4>;
			};

			uart1-rts-gpio {
				rockchip,pins = <0x5b30>;
				rockchip,drive = <0x0>;
			};
		};

		gpio7_uart2 {

			uart2-xfer {
				rockchip,pins = <0x7c61 0x7c71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xa8>;
				phandle = <0xa8>;
			};
		};

		gpio7_uart3 {

			uart3-xfer {
				rockchip,pins = <0x7a71 0x7b01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xaa>;
				phandle = <0xaa>;
			};

			uart3-cts {
				rockchip,pins = <0x7b11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xab>;
				phandle = <0xab>;
			};

			uart3-rts {
				rockchip,pins = <0x7b21>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xac>;
				phandle = <0xac>;
			};
		};

		gpio5_uart4 {

			uart4-xfer {
				rockchip,pins = <0x5b73 0x5b63>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xae>;
				phandle = <0xae>;
			};

			uart4-cts {
				rockchip,pins = <0x5b43>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xaf>;
				phandle = <0xaf>;
			};

			uart4-rts {
				rockchip,pins = <0x5b53>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xb0>;
				phandle = <0xb0>;
			};
		};

		gpio0_i2c0 {

			i2c0-sda {
				rockchip,pins = <0xb71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xb7>;
				phandle = <0xb7>;
			};

			i2c0-scl {
				rockchip,pins = <0xc01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xb8>;
				phandle = <0xb8>;
			};

			i2c0-gpio {
				rockchip,pins = <0xb70 0xc00>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xb9>;
				phandle = <0xb9>;
			};
		};

		gpio8_i2c1 {

			i2c1-sda {
				rockchip,pins = <0x8a41>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xba>;
				phandle = <0xba>;
			};

			i2c1-scl {
				rockchip,pins = <0x8a51>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xbb>;
				phandle = <0xbb>;
			};

			i2c1-gpio {
				rockchip,pins = <0x8a40 0x8a50>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xbc>;
				phandle = <0xbc>;
			};
		};

		gpio6_i2c2 {

			i2c2-sda {
				rockchip,pins = <0x6b11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xbd>;
				phandle = <0xbd>;
			};

			i2c2-scl {
				rockchip,pins = <0x6b21>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xbe>;
				phandle = <0xbe>;
			};

			i2c2-gpio {
				rockchip,pins = <0x6b10 0x6b20>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xbf>;
				phandle = <0xbf>;
			};
		};

		gpio2_i2c3 {

			i2c3-sda {
				rockchip,pins = <0x2c11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc0>;
				phandle = <0xc0>;
			};

			i2c3-scl {
				rockchip,pins = <0x2c01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc1>;
				phandle = <0xc1>;
			};

			i2c3-gpio {
				rockchip,pins = <0x2c10 0x2c00>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc2>;
				phandle = <0xc2>;
			};
		};

		gpio7_i2c4 {

			i2c4-sda {
				rockchip,pins = <0x7c11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc3>;
				phandle = <0xc3>;
			};

			i2c4-scl {
				rockchip,pins = <0x7c21>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc4>;
				phandle = <0xc4>;
			};

			i2c4-gpio {
				rockchip,pins = <0x7c10 0x7c20>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc5>;
				phandle = <0xc5>;
			};
		};

		gpio7_i2c5 {

			i2c5-sda {
				rockchip,pins = <0x7c32>;
				rockchip,pull = <0x0>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc6>;
				phandle = <0xc6>;
			};

			i2c5-scl {
				rockchip,pins = <0x7c42>;
				rockchip,pull = <0x0>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc7>;
				phandle = <0xc7>;
			};

			i2c5-gpio {
				rockchip,pins = <0x7c30 0x7c40>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xc8>;
				phandle = <0xc8>;
			};
		};

		gpio5_spi0 {

			spi0-txd {
				rockchip,pins = <0x5b61>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x8b>;
				phandle = <0x8b>;
			};

			spi0-rxd {
				rockchip,pins = <0x5b71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x8c>;
				phandle = <0x8c>;
			};

			spi0-clk {
				rockchip,pins = <0x5b41>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x8d>;
				phandle = <0x8d>;
			};

			spi0-cs0 {
				rockchip,pins = <0x5b51>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x8e>;
				phandle = <0x8e>;
			};

			spi0-cs1 {
				rockchip,pins = <0x5c01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x8f>;
				phandle = <0x8f>;
			};
		};

		gpio7_spi1 {

			spi1-txd {
				rockchip,pins = <0x7b72>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x91>;
				phandle = <0x91>;
			};

			spi1-rxd {
				rockchip,pins = <0x7b62>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x92>;
				phandle = <0x92>;
			};

			spi1-clk {
				rockchip,pins = <0x7b42>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x93>;
				phandle = <0x93>;
			};

			spi1-cs0 {
				rockchip,pins = <0x7b52>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x94>;
				phandle = <0x94>;
			};
		};

		gpio8_spi2 {

			spi2-txd {
				rockchip,pins = <0x8b11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x97>;
				phandle = <0x97>;
			};

			spi2-rxd {
				rockchip,pins = <0x8b01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x98>;
				phandle = <0x98>;
			};

			spi2-clk {
				rockchip,pins = <0x8a61>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x99>;
				phandle = <0x99>;
			};

			spi2-cs0 {
				rockchip,pins = <0x8a71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x9a>;
				phandle = <0x9a>;
			};

			spi2-cs1 {
				rockchip,pins = <0x8a31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x9b>;
				phandle = <0x9b>;
			};
		};

		gpio6_i2s {

			i2s-mclk {
				rockchip,pins = <0x6b01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd1>;
				phandle = <0xd1>;
			};

			i2s-sclk {
				rockchip,pins = <0x6a01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd2>;
				phandle = <0xd2>;
			};

			i2s-lrckrx {
				rockchip,pins = <0x6a11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd3>;
				phandle = <0xd3>;
			};

			i2s-lrcktx {
				rockchip,pins = <0x6a21>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd4>;
				phandle = <0xd4>;
			};

			i2s-sdo0 {
				rockchip,pins = <0x6a41>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd6>;
				phandle = <0xd6>;
			};

			i2s-sdo1 {
				rockchip,pins = <0x6a51>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd7>;
				phandle = <0xd7>;
			};

			i2s-sdo2 {
				rockchip,pins = <0x6a61>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd8>;
				phandle = <0xd8>;
			};

			i2s-sdo3 {
				rockchip,pins = <0x6a71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd9>;
				phandle = <0xd9>;
			};

			i2s-sdi {
				rockchip,pins = <0x6a31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xd5>;
				phandle = <0xd5>;
			};

			i2s-gpio {
				rockchip,pins = <0x6b00 0x6a00 0x6a10 0x6a20 0x6a40 0x6a50 0x6a60 0x6a70 0x6a30>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xda>;
				phandle = <0xda>;
			};
		};

		gpio1_lcdc0 {

			lcdc0-lcdc {
				rockchip,pins = <0x1d31 0x1d21 0x1d01 0x1d11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xcd>;
				phandle = <0xcd>;
			};

			lcdc0-gpio {
				rockchip,pins = <0x1d30 0x1d20 0x1d00 0x1d10>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xce>;
				phandle = <0xce>;
			};
		};

		gpio6_spdif {

			spdif-tx {
				rockchip,pins = <0x6b31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xdb>;
				phandle = <0xdb>;
			};

			spdif-gpio {
				rockchip,pins = <0x6b30>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xdc>;
				phandle = <0xdc>;
			};
		};

		gpio7_pwm {

			vop0-pwm {
				rockchip,pins = <0x7a02>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xde>;
				phandle = <0xde>;
			};

			vop1-pwm {
				rockchip,pins = <0x7a03>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xdd>;
				phandle = <0xdd>;
			};

			pwm0 {
				rockchip,pins = <0x7a01>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xdf>;
				phandle = <0xdf>;
			};

			pwm1 {
				rockchip,pins = <0x7a11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xe0>;
				phandle = <0xe0>;
			};

			pwm2 {
				rockchip,pins = <0x7c63>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xe1>;
				phandle = <0xe1>;
			};

			pwm3 {
				rockchip,pins = <0x7c73>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xe2>;
				phandle = <0xe2>;
			};
		};

		gpio3_emmc0 {

			emmc0-clk {
				rockchip,pins = <0x3c22>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x2>;
			};

			emmc0-cmd {
				rockchip,pins = <0x3c02>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x2>;
			};

			emmc0-rstnout {
				rockchip,pins = <0x3c12>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x2>;
			};

			emmc0-pwr {
				rockchip,pins = <0x3b12>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
			};

			emmc0-bus-width1 {
				rockchip,pins = <0x3a02>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x2>;
			};

			emmc0-bus-width4 {
				rockchip,pins = <0x3a02 0x3a12 0x3a22 0x3a32>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x2>;
			};
		};

		gpio6_sdmmc0 {

			sdmmc0-clk {
				rockchip,pins = <0x6c41>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x7c>;
				phandle = <0x7c>;
			};

			sdmmc0-cmd {
				rockchip,pins = <0x6c51>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x7d>;
				phandle = <0x7d>;
			};

			sdmmc0-dectn {
				rockchip,pins = <0x6c61>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x7e>;
				phandle = <0x7e>;
			};

			sdmmc0-bus-width1 {
				rockchip,pins = <0x6c01>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
			};

			sdmmc0-bus-width4 {
				rockchip,pins = <0x6c01 0x6c11 0x6c21 0x6c31>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x7f>;
				phandle = <0x7f>;
			};

			sdmmc0_gpio {
				rockchip,pins = <0x6c40 0x6c50 0x6c60 0x6c00 0x6c10 0x6c20 0x6c30>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x80>;
				phandle = <0x80>;
			};
		};

		gpio4_sdio0 {

			sdio0_clk {
				rockchip,pins = <0x4d11>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x83>;
				phandle = <0x83>;
			};

			sdio0_cmd {
				rockchip,pins = <0x4d01>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x84>;
				phandle = <0x84>;
			};

			sdio0-dectn {
				rockchip,pins = <0x4d21>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x0>;
			};

			sdio0_wrprt {
				rockchip,pins = <0x4d31>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x85>;
				phandle = <0x85>;
			};

			sdio0-pwren {
				rockchip,pins = <0x4d41>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x86>;
				phandle = <0x86>;
			};

			sdio0-bkpwr {
				rockchip,pins = <0x4d51>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x87>;
				phandle = <0x87>;
			};

			sdio0-intn {
				rockchip,pins = <0x4d61>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x88>;
				phandle = <0x88>;
			};

			sdio0-bus-width1 {
				rockchip,pins = <0x4c41>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
			};

			sdio0-bus-width4 {
				rockchip,pins = <0x4c41 0x4c51 0x4c61 0x4c71>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x89>;
				phandle = <0x89>;
			};

			sdio0-all-gpio {
				rockchip,pins = <0x4d10 0x4d00 0x4d20 0x4d30 0x4d40 0x4d50 0x4d60 0x4c40 0x4c50 0x4c60 0x4c70>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x1>;
				linux,phandle = <0x8a>;
				phandle = <0x8a>;
			};
		};

		gpio2_gps {

			gps-mag {
				rockchip,pins = <0x7a72>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
			};

			gps-sig {
				rockchip,pins = <0x7b02>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
			};

			gps-rfclk {
				rockchip,pins = <0x7b12>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
			};
		};

		gpio4_gmac {

			mac-clk {
				rockchip,pins = <0x4a33>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x3>;
				linux,phandle = <0xe6>;
				phandle = <0xe6>;
			};

			mac-txpins {
				rockchip,pins = <0x3d43 0x3d53 0x3d03 0x3d13 0x4a43 0x4b13>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x3>;
				linux,phandle = <0xe7>;
				phandle = <0xe7>;
			};

			mac-rxpins {
				rockchip,pins = <0x3d63 0x3d73 0x3d23 0x3d33 0x4a13 0x4a23 0x4a63 0x4b03>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x3>;
				linux,phandle = <0xe8>;
				phandle = <0xe8>;
			};

			mac-crs {
				rockchip,pins = <0x4a73>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x3>;
			};

			mac-mdpins {
				rockchip,pins = <0x4a53 0x4a03>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x3>;
				linux,phandle = <0xe9>;
				phandle = <0xe9>;
			};
		};

		gpio7_cec {

			hdmi-cec {
				rockchip,pins = <0x7c02>;
				rockchip,pull = <0x0>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xcb>;
				phandle = <0xcb>;
			};

			hdmi-cec-gpio {
				rockchip,pins = <0x7c00>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
			};
		};

		vol_domain {

			lcdc-vcc {
				rockchip,pins = <0xfa00>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xf3>;
				phandle = <0xf3>;
			};

			dvp-vcc {
				rockchip,pins = <0xfa10>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xf6>;
				phandle = <0xf6>;
			};

			flash0-vcc {
				rockchip,pins = <0xfa20>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xf9>;
				phandle = <0xf9>;
			};

			flash1-vcc {
				rockchip,pins = <0xfa30>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xfc>;
				phandle = <0xfc>;
			};

			wifi-vcc {
				rockchip,pins = <0xfa40>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xff>;
				phandle = <0xff>;
			};

			bb-vcc {
				rockchip,pins = <0xfa50>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x102>;
				phandle = <0x102>;
			};

			audio-vcc {
				rockchip,pins = <0xfa60>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x105>;
				phandle = <0x105>;
			};

			sdcard-vcc {
				rockchip,pins = <0xfa70>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x10e>;
				phandle = <0x10e>;
			};

			gpio30-vcc {
				rockchip,pins = <0xfb00>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x108>;
				phandle = <0x108>;
			};

			gpio1830-vcc {
				rockchip,pins = <0xfb10>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x10b>;
				phandle = <0x10b>;
			};

			lcdc-vcc-18 {
				rockchip,pins = <0xfa00>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0xf4>;
				phandle = <0xf4>;
			};

			dvp-vcc-18 {
				rockchip,pins = <0xfa10>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0xf7>;
				phandle = <0xf7>;
			};

			flash0-vcc-18 {
				rockchip,pins = <0xfa20>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0xfa>;
				phandle = <0xfa>;
			};

			flash1-vcc-18 {
				rockchip,pins = <0xfa30>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0xfd>;
				phandle = <0xfd>;
			};

			wifi-vcc-18 {
				rockchip,pins = <0xfa40>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0x100>;
				phandle = <0x100>;
			};

			bb-vcc-18 {
				rockchip,pins = <0xfa50>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0x103>;
				phandle = <0x103>;
			};

			audio-vcc-18 {
				rockchip,pins = <0xfa60>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0x106>;
				phandle = <0x106>;
			};

			sdcard-vcc-18 {
				rockchip,pins = <0xfa70>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0x10f>;
				phandle = <0x10f>;
			};

			gpio30-vcc-18 {
				rockchip,pins = <0xfb00>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0x109>;
				phandle = <0x109>;
			};

			gpio1830-vcc-18 {
				rockchip,pins = <0xfb10>;
				rockchip,voltage = <0x1>;
				linux,phandle = <0x10c>;
				phandle = <0x10c>;
			};

			lcdc-vcc-33 {
				rockchip,pins = <0xfa00>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xf5>;
				phandle = <0xf5>;
			};

			dvp-vcc-33 {
				rockchip,pins = <0xfa10>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xf8>;
				phandle = <0xf8>;
			};

			flash0-vcc-33 {
				rockchip,pins = <0xfa20>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xfb>;
				phandle = <0xfb>;
			};

			flash1-vcc-33 {
				rockchip,pins = <0xfa30>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0xfe>;
				phandle = <0xfe>;
			};

			wifi-vcc-33 {
				rockchip,pins = <0xfa40>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x101>;
				phandle = <0x101>;
			};

			bb-vcc-33 {
				rockchip,pins = <0xfa50>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x104>;
				phandle = <0x104>;
			};

			audio-vcc-33 {
				rockchip,pins = <0xfa60>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x107>;
				phandle = <0x107>;
			};

			sdcard-vcc-33 {
				rockchip,pins = <0xfa70>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x110>;
				phandle = <0x110>;
			};

			gpio30-vcc-33 {
				rockchip,pins = <0xfb00>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x10a>;
				phandle = <0x10a>;
			};

			gpio1830-vcc-33 {
				rockchip,pins = <0xfb10>;
				rockchip,voltage = <0x0>;
				linux,phandle = <0x10d>;
				phandle = <0x10d>;
			};
		};

		isp_pin {

			isp_mipi {
				rockchip,pins = <0x2b31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xec>;
				phandle = <0xec>;
			};

			isp_dvp_d2d9 {
				rockchip,pins = <0x2a01 0x2a11 0x2a21 0x2a31 0x2a41 0x2a51 0x2a61 0x2a71 0x2b01 0x2b11 0x2b21 0x2b31>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xed>;
				phandle = <0xed>;
			};

			isp_d0d1 {
				rockchip,pins = <0x2b41 0x2b51>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xee>;
				phandle = <0xee>;
			};

			isp_d10d11 {
				rockchip,pins = <0x2b61 0x2b71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xef>;
				phandle = <0xef>;
			};

			isp_d0d7 {
				rockchip,pins = <0x2b41 0x2b51 0x2a01 0x2a11 0x2a21 0x2a31 0x2a41 0x2a51>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xf0>;
				phandle = <0xf0>;
			};

			isp_shutter {
				rockchip,pins = <0x7b41 0x7b71>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
			};

			isp_flash_trigger {
				rockchip,pins = <0x7b51>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xf1>;
				phandle = <0xf1>;
			};

			isp_prelight {
				rockchip,pins = <0x7b61>;
				rockchip,pull = <0x4>;
				rockchip,drive = <0x0>;
				linux,phandle = <0xf2>;
				phandle = <0xf2>;
			};

			isp_hsadc {
				rockchip,pins = <0x2a03 0x2a13 0x2a23 0x2a33 0x2a43 0x2a53 0x2a63 0x2a73 0x2b03 0x2b13 0x2b23 0x2b33>;
				rockchip,pull = <0x1>;
				rockchip,drive = <0x0>;
				linux,phandle = <0x9c>;
				phandle = <0x9c>;
			};
		};

		gpio0_gpio {

			gpio0-c2 {
				rockchip,pins = <0xc20>;
				rockchip,pull = <0x2>;
			};
		};

		gpio7_gpio {

			gpio7-b7 {
				rockchip,pins = <0x7b70>;
				rockchip,pull = <0x1>;
			};
		};
	};

	clocks {
		compatible = "rockchip,rk-clocks";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x0 0xff760000 0x1b0>;

		fixed_rate_cons {
			compatible = "rockchip,rk-fixed-rate-cons";

			xin24m {
				compatible = "rockchip,rk-fixed-clock";
				clock-output-names = "xin24m";
				clock-frequency = <0x16e3600>;
				#clock-cells = <0x0>;
				linux,phandle = <0x8>;
				phandle = <0x8>;
			};

			xin12m {
				compatible = "rockchip,rk-fixed-clock";
				clocks = <0x8>;
				clock-output-names = "xin12m";
				clock-frequency = <0xb71b00>;
				#clock-cells = <0x0>;
				linux,phandle = <0x1f>;
				phandle = <0x1f>;
			};

			xin32k {
				compatible = "rockchip,rk-fixed-clock";
				clock-output-names = "xin32k";
				clock-frequency = <0x7d00>;
				#clock-cells = <0x0>;
				linux,phandle = <0x17>;
				phandle = <0x17>;
			};

			io_27m_in {
				compatible = "rockchip,rk-fixed-clock";
				clock-output-names = "io_27m_in";
				clock-frequency = <0x19bfcc0>;
				#clock-cells = <0x0>;
				linux,phandle = <0x53>;
				phandle = <0x53>;
			};

			dummy {
				compatible = "rockchip,rk-fixed-clock";
				clock-output-names = "dummy";
				clock-frequency = <0x0>;
				#clock-cells = <0x0>;
				linux,phandle = <0x18>;
				phandle = <0x18>;
			};

			dummy_cpll {
				compatible = "rockchip,rk-fixed-clock";
				clock-output-names = "dummy_cpll";
				clock-frequency = <0x0>;
				#clock-cells = <0x0>;
				linux,phandle = <0x15>;
				phandle = <0x15>;
			};

			i2s_clkin {
				compatible = "rockchip,rk-fixed-clock";
				clock-output-names = "i2s_clkin";
				clock-frequency = <0x0>;
				#clock-cells = <0x0>;
				linux,phandle = <0x1e>;
				phandle = <0x1e>;
			};

			edp_24m_clkin {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "edp_24m_clkin";
				clock-frequency = <0x0>;
				linux,phandle = <0x47>;
				phandle = <0x47>;
			};

			gmac_clkin {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "gmac_clkin";
				clock-frequency = <0x7735940>;
				linux,phandle = <0x39>;
				phandle = <0x39>;
			};

			clk_hsadc_ext {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "clk_hsadc_ext";
				clock-frequency = <0x0>;
				linux,phandle = <0x3b>;
				phandle = <0x3b>;
			};

			jtag_clkin {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "jtag_clkin";
				clock-frequency = <0x0>;
				linux,phandle = <0x66>;
				phandle = <0x66>;
			};

			pclkin_cif {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "pclkin_cif";
				clock-frequency = <0x0>;
				linux,phandle = <0x77>;
				phandle = <0x77>;
			};

			pclkin_isp {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "pclkin_isp";
				clock-frequency = <0x0>;
				linux,phandle = <0x78>;
				phandle = <0x78>;
			};

			hsadc_0_tsp {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "hsadc_0_tsp";
				clock-frequency = <0x0>;
				linux,phandle = <0x6a>;
				phandle = <0x6a>;
			};

			hsadc_1_tsp {
				compatible = "rockchip,rk-fixed-clock";
				#clock-cells = <0x0>;
				clock-output-names = "hsadc_1_tsp";
				clock-frequency = <0x0>;
				linux,phandle = <0x6b>;
				phandle = <0x6b>;
			};
		};

		fixed_factor_cons {
			compatible = "rockchip,rk-fixed-factor-cons";

			otgphy0_480m {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0x9 0x4>;
				clock-output-names = "otgphy0_480m";
				clock-div = <0x1>;
				clock-mult = <0x14>;
				#clock-cells = <0x0>;
				linux,phandle = <0x30>;
				phandle = <0x30>;
			};

			otgphy1_480m {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0x9 0x5>;
				clock-output-names = "otgphy1_480m";
				clock-div = <0x1>;
				clock-mult = <0x14>;
				#clock-cells = <0x0>;
				linux,phandle = <0x2e>;
				phandle = <0x2e>;
			};

			otgphy2_480m {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0x9 0x6>;
				clock-output-names = "otgphy2_480m";
				clock-div = <0x1>;
				clock-mult = <0x14>;
				#clock-cells = <0x0>;
				linux,phandle = <0x2f>;
				phandle = <0x2f>;
			};

			clk_hsadc_inv {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0xa>;
				clock-output-names = "clk_hsadc_inv";
				clock-div = <0x1>;
				clock-mult = <0x1>;
				#clock-cells = <0x0>;
				linux,phandle = <0x3c>;
				phandle = <0x3c>;
			};

			pclkin_cif_inv {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0xb 0x0>;
				clock-output-names = "pclkin_cif_inv";
				clock-div = <0x1>;
				clock-mult = <0x1>;
				#clock-cells = <0x0>;
				linux,phandle = <0x4a>;
				phandle = <0x4a>;
			};

			pclkin_isp_inv {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0xb 0x3>;
				clock-output-names = "pclkin_isp_inv";
				clock-div = <0x1>;
				clock-mult = <0x1>;
				#clock-cells = <0x0>;
				linux,phandle = <0x49>;
				phandle = <0x49>;
			};

			hclk_vepu {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0xc>;
				clock-output-names = "hclk_vepu";
				clock-div = <0x4>;
				clock-mult = <0x1>;
				#clock-cells = <0x0>;
			};

			hclk_vdpu {
				compatible = "rockchip,rk-fixed-factor-clock";
				clocks = <0xd>;
				clock-output-names = "hclk_vdpu";
				clock-div = <0x4>;
				clock-mult = <0x1>;
				#clock-cells = <0x0>;
				linux,phandle = <0xe3>;
				phandle = <0xe3>;
			};
		};

		pd_cons {
			compatible = "rockchip,rk-pd-cons";

			pd_gpu {
				compatible = "rockchip,rk-pd-clock";
				clock-output-names = "pd_gpu";
				rockchip,pd-id = <0x8>;
				#clock-cells = <0x0>;
			};

			pd_video {
				compatible = "rockchip,rk-pd-clock";
				clock-output-names = "pd_video";
				rockchip,pd-id = <0xc>;
				#clock-cells = <0x0>;
			};

			pd_vio {
				compatible = "rockchip,rk-pd-clock";
				clock-output-names = "pd_vio";
				rockchip,pd-id = <0xd>;
				#clock-cells = <0x0>;
				linux,phandle = <0xe>;
				phandle = <0xe>;
			};

			pd_hevc {
				compatible = "rockchip,rk-pd-clock";
				clock-output-names = "pd_hevc";
				rockchip,pd-id = <0x9>;
				#clock-cells = <0x0>;
			};

			pd_edp {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_edp";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
			};

			pd_vop0 {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_vop0";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
				linux,phandle = <0xcc>;
				phandle = <0xcc>;
			};

			pd_vop1 {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_vop1";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
				linux,phandle = <0xcf>;
				phandle = <0xcf>;
			};

			pd_isp {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_isp";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
				linux,phandle = <0xeb>;
				phandle = <0xeb>;
			};

			pd_iep {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_iep";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
			};

			pd_rga {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_rga";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
			};

			pd_mipicsi {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_mipicsi";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
			};

			pd_mipidsi {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_mipidsi";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
				linux,phandle = <0xca>;
				phandle = <0xca>;
			};

			pd_lvds {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_lvds";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
			};

			pd_hdmi {
				compatible = "rockchip,rk-pd-clock";
				clocks = <0xe>;
				clock-output-names = "pd_hdmi";
				rockchip,pd-id = <0xff>;
				#clock-cells = <0x0>;
			};
		};

		clock_regs {
			compatible = "rockchip,rk-clock-regs";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			reg = <0x0 0x3ff>;
			ranges;

			pll_cons {
				compatible = "rockchip,rk-pll-cons";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;

				pll-clk@0000 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x0 0x10>;
					mode-reg = <0x50 0x0>;
					status-reg = <0x284 0x6>;
					clocks = <0x8>;
					clock-output-names = "clk_apll";
					rockchip,pll-type = <0x10>;
					#clock-cells = <0x0>;
					linux,phandle = <0x10>;
					phandle = <0x10>;
				};

				pll-clk@0010 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x10 0x10>;
					mode-reg = <0x50 0x4>;
					status-reg = <0x284 0x5>;
					clocks = <0x8>;
					clock-output-names = "clk_dpll";
					rockchip,pll-type = <0x4>;
					#clock-cells = <0x0>;
					linux,phandle = <0x40>;
					phandle = <0x40>;
				};

				pll-clk@0020 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x20 0x10>;
					mode-reg = <0x50 0x8>;
					status-reg = <0x284 0x7>;
					clocks = <0x8>;
					clock-output-names = "clk_cpll";
					rockchip,pll-type = <0x20>;
					#clock-cells = <0x0>;
					#clock-init-cells = <0x1>;
					linux,phandle = <0x43>;
					phandle = <0x43>;
				};

				pll-clk@0030 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x30 0x10>;
					mode-reg = <0x50 0xc>;
					status-reg = <0x284 0x8>;
					clocks = <0x8>;
					clock-output-names = "clk_gpll";
					rockchip,pll-type = <0x4>;
					#clock-cells = <0x0>;
					#clock-init-cells = <0x1>;
					linux,phandle = <0x16>;
					phandle = <0x16>;
				};

				pll-clk@0040 {
					compatible = "rockchip,rk3188-pll-clk";
					reg = <0x40 0x10>;
					mode-reg = <0x50 0xe>;
					status-reg = <0x284 0x9>;
					clocks = <0x8>;
					clock-output-names = "clk_npll";
					rockchip,pll-type = <0x4>;
					#clock-cells = <0x0>;
					#clock-init-cells = <0x1>;
					linux,phandle = <0x25>;
					phandle = <0x25>;
				};
			};

			clk_sel_cons {
				compatible = "rockchip,rk-sel-cons";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;

				sel-con@0060 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x60 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					aclk_core_m0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x4>;
						clocks = <0xf>;
						clock-output-names = "aclk_core_m0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x71>;
						phandle = <0x71>;
					};

					aclk_core_mp_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x4 0x4>;
						clocks = <0xf>;
						clock-output-names = "aclk_core_mp";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x72>;
						phandle = <0x72>;
					};

					clk_core_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0xf>;
						clock-output-names = "clk_core";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xb>;
						rockchip,flags = <0xc0>;
					};

					clk_core_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x10 0x11 0x2>;
						clock-output-names = "clk_core";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0xf>;
						phandle = <0xf>;
					};
				};

				sel-con@0064 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x64 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					aclk_bus_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x3>;
						clocks = <0x12>;
						clock-output-names = "aclk_bus";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x14>;
						phandle = <0x14>;
					};

					aclk_bus_src_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x3 0x5>;
						clocks = <0x13>;
						clock-output-names = "aclk_bus_src";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x80>;
						linux,phandle = <0x12>;
						phandle = <0x12>;
					};

					hclk_bus_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x14>;
						clock-output-names = "hclk_bus";
						rockchip,div-type = <0x80>;
						rockchip,div-relations = <0x0 0x1 0x1 0x2 0x3 0x4>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x5c>;
						phandle = <0x5c>;
					};

					pclk_bus_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0xc 0x3>;
						clocks = <0x14>;
						clock-output-names = "pclk_bus";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x5d>;
						phandle = <0x5d>;
					};

					aclk_bus_src_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "aclk_bus_src";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x13>;
						phandle = <0x13>;
					};
				};

				sel-con@0068 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x68 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_tsadc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x6>;
						clocks = <0x17>;
						clock-output-names = "clk_tsadc";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x60>;
						phandle = <0x60>;
					};

					testout_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x18>;
						clock-output-names = "testout_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
					};
				};

				sel-con@006c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x6c 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_uart4_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x19>;
						clock-output-names = "clk_uart4_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x1a>;
						phandle = <0x1a>;
					};

					uart4_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x1a 0x1b 0x8 0x18>;
						clock-output-names = "clk_uart4";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0xad>;
						phandle = <0xad>;
					};
				};

				sel-con@0070 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x70 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					i2s_pll_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x1c>;
						clock-output-names = "clk_i2s_pll";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x80>;
					};

					i2s_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x1c 0x1d 0x1e 0x1f>;
						clock-output-names = "clk_i2s";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0x20>;
						phandle = <0x20>;
					};

					i2s_outclk_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xc 0x1>;
						clocks = <0x20 0x1f>;
						clock-output-names = "clk_i2s_out";
						#clock-cells = <0x0>;
						linux,phandle = <0x63>;
						phandle = <0x63>;
					};

					i2s_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_i2s_pll";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x1c>;
						phandle = <0x1c>;
					};
				};

				sel-con@0074 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x74 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					spdif_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x21>;
						clock-output-names = "spdif_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x22>;
						phandle = <0x22>;
					};

					spdif_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x22 0x23 0x1f 0x18>;
						clock-output-names = "clk_spdif";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0x64>;
						phandle = <0x64>;
					};

					spdif_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_spdif_pll";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x21>;
						phandle = <0x21>;
					};
				};

				sel-con@0078 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x78 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_isp_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x6>;
						clocks = <0x24>;
						clock-output-names = "clk_isp";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_isp_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "clk_isp";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x24>;
						phandle = <0x24>;
					};

					clk_isp_jpe_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x6>;
						clocks = <0x26>;
						clock-output-names = "clk_isp_jpe";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_isp_jpe_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "clk_isp_jpe";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x26>;
						phandle = <0x26>;
					};
				};

				sel-con@007c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x7c 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					uart4_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x1a>;
						clock-output-names = "uart4_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x1b>;
						phandle = <0x1b>;
					};
				};

				sel-con@0080 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x80 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					i2s_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x1c>;
						clock-output-names = "i2s_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x1d>;
						phandle = <0x1d>;
					};
				};

				sel-con@0084 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x84 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					spdif_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x22>;
						clock-output-names = "spdif_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x23>;
						phandle = <0x23>;
					};
				};

				sel-con@0088 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x88 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					aclk_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x27>;
						clock-output-names = "aclk_peri";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x80>;
					};

					hclk_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x27>;
						clock-output-names = "hclk_peri";
						rockchip,div-type = <0x80>;
						rockchip,div-relations = <0x0 0x1 0x1 0x2 0x2 0x4>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x5e>;
						phandle = <0x5e>;
					};

					pclk_peri_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0xc 0x2>;
						clocks = <0x27>;
						clock-output-names = "pclk_peri";
						rockchip,div-type = <0x80>;
						rockchip,div-relations = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x5f>;
						phandle = <0x5f>;
					};

					aclk_peri_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "aclk_peri";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x27>;
						phandle = <0x27>;
					};
				};

				sel-con@008c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x8c 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_sdmmc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x6>;
						clocks = <0x28>;
						clock-output-names = "clk_sdmmc";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x3>;
					};

					clk_sdmmc_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x8>;
						clock-output-names = "clk_sdmmc";
						#clock-cells = <0x0>;
						linux,phandle = <0x28>;
						phandle = <0x28>;
					};

					hsicphy_12m_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x6>;
						clocks = <0x29>;
						clock-output-names = "hsicphy_12m_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x48>;
						phandle = <0x48>;
					};
				};

				sel-con@0090 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x90 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_sdio0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x6>;
						clocks = <0x2a>;
						clock-output-names = "clk_sdio0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x3>;
					};

					clk_sdio0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x8>;
						clock-output-names = "clk_sdio0";
						#clock-cells = <0x0>;
						linux,phandle = <0x2a>;
						phandle = <0x2a>;
					};

					clk_emmc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x6>;
						clocks = <0x2b>;
						clock-output-names = "clk_emmc";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x3>;
					};

					clk_emmc_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x8>;
						clock-output-names = "clk_emmc";
						#clock-cells = <0x0>;
						linux,phandle = <0x2b>;
						phandle = <0x2b>;
					};
				};

				sel-con@0094 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x94 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_uart0_pll_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x2c>;
						clock-output-names = "clk_uart0_pll";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					uart0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x2c 0x2d 0x8 0x18>;
						clock-output-names = "clk_uart0";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0x9e>;
						phandle = <0x9e>;
					};

					usbphy_480m_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xb 0x2>;
						clocks = <0x2e 0x2f 0x30>;
						clock-output-names = "usbphy_480m";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xf>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x31>;
						phandle = <0x31>;
					};

					clk_uart0_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xd 0x2>;
						clocks = <0x15 0x16 0x31 0x25>;
						clock-output-names = "clk_uart0_pll";
						#clock-cells = <0x0>;
						linux,phandle = <0x2c>;
						phandle = <0x2c>;
					};

					uart_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "uart_pll_mux";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x19>;
						phandle = <0x19>;
					};
				};

				sel-con@0098 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x98 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_uart1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x19>;
						clock-output-names = "clk_uart1_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x32>;
						phandle = <0x32>;
					};

					uart1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x32 0x33 0x8 0x18>;
						clock-output-names = "clk_uart1";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0xa1>;
						phandle = <0xa1>;
					};
				};

				sel-con@009c {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x9c 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_uart2_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x19>;
						clock-output-names = "clk_uart2_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x34>;
						phandle = <0x34>;
					};

					uart2_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x34 0x35 0x8 0x18>;
						clock-output-names = "clk_uart2";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0xa5>;
						phandle = <0xa5>;
					};
				};

				sel-con@00a0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xa0 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_uart3_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x19>;
						clock-output-names = "clk_uart3_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x36>;
						phandle = <0x36>;
					};

					uart3_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x36 0x37 0x8 0x18>;
						clock-output-names = "clk_uart3";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0xa9>;
						phandle = <0xa9>;
					};
				};

				sel-con@00a4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xa4 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					uart0_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x2c>;
						clock-output-names = "uart0_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x2d>;
						phandle = <0x2d>;
					};
				};

				sel-con@00a8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xa8 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					uart1_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x32>;
						clock-output-names = "uart1_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x33>;
						phandle = <0x33>;
					};
				};

				sel-con@00ac {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xac 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					uart2_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x34>;
						clock-output-names = "uart2_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x35>;
						phandle = <0x35>;
					};
				};

				sel-con@00b0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xb0 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					uart3_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x36>;
						clock-output-names = "uart3_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x37>;
						phandle = <0x37>;
					};
				};

				sel-con@00b4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xb4 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_mac_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x0 0x2>;
						clocks = <0x25 0x15 0x16>;
						clock-output-names = "clk_mac_pll";
						#clock-cells = <0x0>;
						linux,phandle = <0x38>;
						phandle = <0x38>;
					};

					clk_mac_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x4 0x1>;
						clocks = <0x38 0x39>;
						clock-output-names = "clk_mac";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xa>;
						rockchip,flags = <0x4>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x67>;
						phandle = <0x67>;
					};

					clk_mac_pll_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x38>;
						clock-output-names = "clk_mac_pll";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};
				};

				sel-con@00b8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xb8 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_hsadc_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x0 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_hsadc_pll";
						#clock-cells = <0x0>;
						linux,phandle = <0x3a>;
						phandle = <0x3a>;
					};

					clk_hsadc_out {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x4 0x1>;
						clocks = <0x3a 0x3b>;
						clock-output-names = "clk_hsadc_out";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x9>;
						rockchip,flags = <0x4>;
						linux,phandle = <0xa>;
						phandle = <0xa>;
					};

					clk_hsadc {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x7 0x1>;
						clocks = <0xa 0x3c>;
						clock-output-names = "clk_hsadc";
						#clock-cells = <0x0>;
					};

					clk_hsadc_pll_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x8>;
						clocks = <0x3a>;
						clock-output-names = "clk_hsadc_pll";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};
				};

				sel-con@00c0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xc0 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_saradc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x8>;
						clocks = <0x8>;
						clock-output-names = "clk_saradc";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x61>;
						phandle = <0x61>;
					};
				};

				sel-con@00c4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xc4 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_spi0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x3d>;
						clock-output-names = "clk_spi0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_spi0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x7 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_spi0";
						#clock-cells = <0x0>;
						linux,phandle = <0x3d>;
						phandle = <0x3d>;
					};

					clk_spi1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x7>;
						clocks = <0x3e>;
						clock-output-names = "clk_spi1";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_spi1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_spi1";
						#clock-cells = <0x0>;
						linux,phandle = <0x3e>;
						phandle = <0x3e>;
					};
				};

				sel-con@00c8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xc8 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					ddr_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x2>;
						clocks = <0x3f>;
						clock-output-names = "clk_ddr";
						rockchip,div-type = <0x80>;
						rockchip,div-relations = <0x0 0x1 0x1 0x2 0x3 0x4>;
						#clock-cells = <0x0>;
						rockchip,flags = <0xc0>;
						rockchip,clkops-idx = <0xd>;
					};

					ddr_clk_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x2 0x1>;
						clocks = <0x40 0x16>;
						clock-output-names = "clk_ddr";
						#clock-cells = <0x0>;
						linux,phandle = <0x3f>;
						phandle = <0x3f>;
					};

					crypto_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x14>;
						clock-output-names = "clk_crypto";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x68>;
						phandle = <0x68>;
					};

					clk_cif_pll_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_cif_pll";
						#clock-cells = <0x0>;
						linux,phandle = <0x42>;
						phandle = <0x42>;
					};

					clk_cif_out_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x9 0x5>;
						clocks = <0x41>;
						clock-output-names = "clk_cif_out";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_cif_out_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x42 0x8>;
						clock-output-names = "clk_cif_out";
						#clock-cells = <0x0>;
						linux,phandle = <0x41>;
						phandle = <0x41>;
					};
				};

				sel-con@00cc {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xcc 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					dclk_lcdc0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x0 0x2>;
						clocks = <0x43 0x16 0x25>;
						clock-output-names = "dclk_lcdc0";
						#clock-cells = <0x0>;
						linux,phandle = <0x44>;
						phandle = <0x44>;
					};

					dclk_lcdc0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x8>;
						clocks = <0x44>;
						clock-output-names = "dclk_lcdc0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x10>;
						rockchip,flags = <0x4>;
					};
				};

				sel-con@00d0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xd0 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_edp_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x6>;
						clocks = <0x45>;
						clock-output-names = "clk_edp";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_edp_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "clk_edp";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x45>;
						phandle = <0x45>;
					};

					hclk_vio_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x46>;
						clock-output-names = "hclk_vio";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x76>;
						phandle = <0x76>;
					};

					edp_24m_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x47 0x8>;
						clock-output-names = "clk_edp_24m";
						#clock-cells = <0x0>;
						linux,phandle = <0x62>;
						phandle = <0x62>;
					};
				};

				sel-con@00d4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xd4 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					hsicphy_480m_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x0 0x2>;
						clocks = <0x15 0x16 0x31>;
						clock-output-names = "hsicphy_480m";
						#clock-cells = <0x0>;
						linux,phandle = <0x29>;
						phandle = <0x29>;
					};

					hsicphy_12m_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x2 0x1>;
						clocks = <0x9 0x9 0x48>;
						clock-output-names = "hsicphy_12m";
						#clock-cells = <0x0>;
						linux,phandle = <0xe5>;
						phandle = <0xe5>;
					};

					clkin_isp {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x3 0x1>;
						clocks = <0xb 0x3 0x49>;
						clock-output-names = "clkin_isp";
						#clock-cells = <0x0>;
						linux,phandle = <0xea>;
						phandle = <0xea>;
					};

					clkin_cif {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x4 0x1>;
						clocks = <0xb 0x0 0x4a>;
						clock-output-names = "clkin_cif";
						#clock-cells = <0x0>;
					};

					dclk_lcdc1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x43 0x16 0x25>;
						clock-output-names = "dclk_lcdc1";
						#clock-cells = <0x0>;
						linux,phandle = <0x4b>;
						phandle = <0x4b>;
					};

					dclk_lcdc1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x8>;
						clocks = <0x4b>;
						clock-output-names = "dclk_lcdc1";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x11>;
						rockchip,flags = <0x4>;
					};
				};

				sel-con@00d8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xd8 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					aclk_rga_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x4c>;
						clock-output-names = "aclk_rga";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					aclk_rga_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x31>;
						clock-output-names = "aclk_rga";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x4c>;
						phandle = <0x4c>;
					};

					clk_rga_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x4d>;
						clock-output-names = "clk_rga";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_rga_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x31>;
						clock-output-names = "clk_rga";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x4d>;
						phandle = <0x4d>;
					};
				};

				sel-con@00dc {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xdc 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					aclk_vio0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x46>;
						clock-output-names = "aclk_vio0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x80>;
					};

					aclk_vio0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x43 0x16 0x31>;
						clock-output-names = "aclk_vio0";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x46>;
						phandle = <0x46>;
					};

					aclk_vio1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x4e>;
						clock-output-names = "aclk_vio1";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x80>;
					};

					aclk_vio1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x43 0x16 0x31>;
						clock-output-names = "aclk_vio1";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x4e>;
						phandle = <0x4e>;
					};
				};

				sel-con@00e0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xe0 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_vepu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0xc>;
						clock-output-names = "clk_vepu";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_vepu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x31>;
						clock-output-names = "clk_vepu";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0xc>;
						phandle = <0xc>;
					};

					clk_vdpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0xd>;
						clock-output-names = "clk_vdpu";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_vdpu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x31>;
						clock-output-names = "clk_vdpu";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0xd>;
						phandle = <0xd>;
					};
				};

				sel-con@00e4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xe4 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					pclk_pd_pmu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x16>;
						clock-output-names = "pclk_pd_pmu";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x69>;
						phandle = <0x69>;
					};

					pclk_pd_alive {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x16>;
						clock-output-names = "pclk_pd_alive";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x75>;
						phandle = <0x75>;
					};
				};

				sel-con@00e8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xe8 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_gpu_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x4f>;
						clock-output-names = "clk_gpu";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x100>;
					};

					clk_gpu_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x31 0x25>;
						clock-output-names = "clk_gpu";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x4f>;
						phandle = <0x4f>;
					};

					clk_sdio1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x6>;
						clocks = <0x50>;
						clock-output-names = "clk_sdio1";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x3>;
					};

					clk_sdio1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x8>;
						clock-output-names = "clk_sdio1";
						#clock-cells = <0x0>;
						linux,phandle = <0x50>;
						phandle = <0x50>;
					};
				};

				sel-con@00ec {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xec 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_tsp_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x51>;
						clock-output-names = "clk_tsp";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_tsp_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "clk_tsp";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x51>;
						phandle = <0x51>;
					};

					clk_tspout_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x52>;
						clock-output-names = "clk_tspout";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_tspout_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x25 0x53>;
						clock-output-names = "clk_tspout";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x52>;
						phandle = <0x52>;
					};
				};

				sel-con@00f0 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xf0 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_core0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x3>;
						clocks = <0xf>;
						clock-output-names = "clk_core0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x6c>;
						phandle = <0x6c>;
					};

					clk_core1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x4 0x3>;
						clocks = <0xf>;
						clock-output-names = "clk_core1";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x6d>;
						phandle = <0x6d>;
					};

					clk_core2_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x3>;
						clocks = <0xf>;
						clock-output-names = "clk_core2";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x6e>;
						phandle = <0x6e>;
					};

					clk_core3_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0xc 0x3>;
						clocks = <0xf>;
						clock-output-names = "clk_core3";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x6f>;
						phandle = <0x6f>;
					};
				};

				sel-con@00f4 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xf4 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_l2ram_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x3>;
						clocks = <0xf>;
						clock-output-names = "clk_l2ram";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x70>;
						phandle = <0x70>;
					};

					atclk_core_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x4 0x5>;
						clocks = <0xf>;
						clock-output-names = "atclk_core";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x73>;
						phandle = <0x73>;
					};

					pclk_core_dbg_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x9 0x5>;
						clocks = <0xf>;
						clock-output-names = "pclk_dbg_src";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xc>;
						linux,phandle = <0x74>;
						phandle = <0x74>;
					};
				};

				sel-con@00f8 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xf8 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_nandc0_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x54>;
						clock-output-names = "clk_nandc0";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_nandc0_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x7 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_nandc0";
						#clock-cells = <0x0>;
						linux,phandle = <0x54>;
						phandle = <0x54>;
					};

					clk_nandc1_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x55>;
						clock-output-names = "clk_nandc1";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_nandc1_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xf 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_nandc1";
						#clock-cells = <0x0>;
						linux,phandle = <0x55>;
						phandle = <0x55>;
					};
				};

				sel-con@00fc {
					compatible = "rockchip,rk3188-selcon";
					reg = <0xfc 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_spi2_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x56>;
						clock-output-names = "clk_spi2";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
					};

					clk_spi2_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x7 0x1>;
						clocks = <0x15 0x16>;
						clock-output-names = "clk_spi2";
						#clock-cells = <0x0>;
						linux,phandle = <0x56>;
						phandle = <0x56>;
					};

					aclk_hevc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x57>;
						clock-output-names = "aclk_hevc";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x100>;
					};

					aclk_hevc_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "aclk_hevc";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x57>;
						phandle = <0x57>;
					};
				};

				sel-con@0100 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x100 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					spdif_8ch_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x7>;
						clocks = <0x21>;
						clock-output-names = "spdif_8ch_div";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						linux,phandle = <0x58>;
						phandle = <0x58>;
					};

					spdif_8ch_clk_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x8 0x2>;
						clocks = <0x58 0x59 0x1f>;
						clock-output-names = "clk_spdif_8ch";
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0xe>;
						rockchip,flags = <0x4>;
						linux,phandle = <0x65>;
						phandle = <0x65>;
					};

					hclk_hevc_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0xc 0x2>;
						clocks = <0x57>;
						clock-output-names = "hclk_hevc";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0xb1>;
						phandle = <0xb1>;
					};
				};

				sel-con@0104 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x104 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					spdif_8ch_frac {
						compatible = "rockchip,rk3188-frac-con";
						clocks = <0x58>;
						clock-output-names = "spdif_8ch_frac";
						rockchip,bits = <0x0 0x20>;
						rockchip,clkops-idx = <0x5>;
						#clock-cells = <0x0>;
						linux,phandle = <0x59>;
						phandle = <0x59>;
					};
				};

				sel-con@0108 {
					compatible = "rockchip,rk3188-selcon";
					reg = <0x108 0x4>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					clk_hevc_cabac_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x0 0x5>;
						clocks = <0x5a>;
						clock-output-names = "clk_hevc_cabac";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x100>;
					};

					clk_hevc_cabac_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0x6 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "clk_hevc_cabac";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x5a>;
						phandle = <0x5a>;
					};

					clk_hevc_core_div {
						compatible = "rockchip,rk3188-div-con";
						rockchip,bits = <0x8 0x5>;
						clocks = <0x5b>;
						clock-output-names = "clk_hevc_core";
						rockchip,div-type = <0x0>;
						#clock-cells = <0x0>;
						rockchip,clkops-idx = <0x1>;
						rockchip,flags = <0x100>;
					};

					clk_hevc_core_mux {
						compatible = "rockchip,rk3188-mux-con";
						rockchip,bits = <0xe 0x2>;
						clocks = <0x15 0x16 0x25>;
						clock-output-names = "clk_hevc_core";
						#clock-cells = <0x0>;
						#clock-init-cells = <0x1>;
						linux,phandle = <0x5b>;
						phandle = <0x5b>;
					};
				};
			};

			clk_gate_cons {
				compatible = "rockchip,rk-gate-cons";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;

				gate-clk@0160 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x160 0x4>;
					clocks = <0x18 0x10 0x16 0x14 0x5c 0x5d 0x18 0x14 0x40 0x16 0x16 0x43 0x8 0x18 0x18 0x18>;
					clock-output-names = "reserved", "reserved", "clk_arm_gpll", "g_aclk_bus", "hclk_bus", "pclk_bus", "reserved", "aclk_bus_2pmu", "reserved", "reserved", "reserved", "reserved", "clk_acc_efuse", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0xfff 0xfff>;
					#clock-cells = <0x1>;
					linux,phandle = <0x11>;
					phandle = <0x11>;
				};

				gate-clk@0164 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x164 0x4>;
					clocks = <0x8 0x8 0x8 0x8 0x8 0x8 0x18 0x18 0x2c 0x2d 0x32 0x33 0x34 0x35 0x36 0x37>;
					clock-output-names = "clk_timer0", "clk_timer1", "clk_timer2", "clk_timer3", "clk_timer4", "clk_timer5", "reserved", "reserved", "clk_uart0_pll", "uart0_frac", "clk_uart1_div", "uart1_frac", "clk_uart2_div", "uart2_frac", "clk_uart3_div", "uart3_frac";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
					linux,phandle = <0xb3>;
					phandle = <0xb3>;
				};

				gate-clk@0168 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x168 0x4>;
					clocks = <0x27 0x27 0x5e 0x5f 0x18 0x38 0x3a 0x60 0x61 0x3d 0x3e 0x56 0x1a 0x1b 0x18 0x18>;
					clock-output-names = "aclk_peri", "reserved", "hclk_peri", "pclk_peri", "reserved", "clk_mac_pll", "clk_hsadc_pll", "clk_tsadc", "clk_saradc", "clk_spi0", "clk_spi1", "clk_spi2", "clk_uart4_div", "uart4_frac", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0xf 0xf>;
					#clock-cells = <0x1>;
					linux,phandle = <0xb6>;
					phandle = <0xb6>;
				};

				gate-clk@016c {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x16c 0x4>;
					clocks = <0x46 0x44 0x4e 0x4b 0x4d 0x4c 0x29 0x42 0x18 0xc 0x18 0xd 0x62 0x45 0x24 0x26>;
					clock-output-names = "aclk_vio0", "dclk_lcdc0", "aclk_vio1", "dclk_lcdc1", "clk_rga", "aclk_rga", "hsicphy_480m", "clk_cif_pll", "reserved", "clk_vepu", "reserved", "clk_vdpu", "clk_edp_24m", "clk_edp", "clk_isp", "clk_isp_jpe";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
				};

				gate-clk@0170 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x170 0x4>;
					clocks = <0x63 0x1c 0x1d 0x20 0x22 0x23 0x64 0x58 0x59 0x65 0x51 0x52 0x3f 0x3f 0x66 0x18>;
					clock-output-names = "clk_i2s_out", "clk_i2s_pll", "i2s_frac", "clk_i2s", "spdif_div", "spdif_frac", "clk_spdif", "spdif_8ch_div", "spdif_8ch_frac", "clk_spdif_8ch", "clk_tsp", "clk_tspout", "reserved", "reserved", "clk_jtag", "reserved";
					rockchip,suspend-clkgating-setting = <0xf000 0xf000>;
					#clock-cells = <0x1>;
				};

				gate-clk@0174 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x174 0x4>;
					clocks = <0x67 0x67 0x67 0x67 0x68 0x54 0x55 0x4f 0x69 0x8 0x8 0x17 0x8 0x8 0x31 0x8>;
					clock-output-names = "g_clk_mac_rx", "g_clk_mac_tx", "g_clk_mac_ref", "g_mac_refout", "clk_crypto", "clk_nandc0", "clk_nandc1", "clk_gpu", "pclk_pd_pmu", "g_clk_pvtm_core", "g_clk_pvtm_gpu", "g_hdmi_cec_clk", "g_hdmi_hdcp_clk", "g_ps2c_clk", "usbphy_480m", "g_mipidsi_24m";
					rockchip,suspend-clkgating-setting = <0x100 0x100>;
					#clock-cells = <0x1>;
					linux,phandle = <0x79>;
					phandle = <0x79>;
				};

				gate-clk@0178 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x178 0x4>;
					clocks = <0x5e 0x5f 0x27 0x27 0x5f 0x5f 0x5f 0x5f 0x5f 0x5f 0x18 0x5f 0x5f 0x5f 0x5f 0x5f>;
					clock-output-names = "g_hp_matrix", "g_pp_axi_matrix", "g_ap_axi_matrix", "g_aclk_dmac2", "g_pclk_spi0", "g_pclk_spi1", "g_pclk_spi2", "g_pclk_ps2c", "g_pclk_uart0", "g_pclk_uart1", "reserved", "g_pclk_uart3", "g_pclk_uart4", "g_pclk_i2c2", "g_pclk_i2c3", "g_pclk_i2c4";
					rockchip,suspend-clkgating-setting = <0x3 0x3>;
					#clock-cells = <0x1>;
					linux,phandle = <0x90>;
					phandle = <0x90>;
				};

				gate-clk@017c {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x17c 0x4>;
					clocks = <0x5f 0x5f 0x5f 0x5f 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x27 0x5e 0x5e 0x5e 0x5e>;
					clock-output-names = "g_pclk_i2c5", "g_pclk_saradc", "g_pclk_tsadc", "g_pclk_sim", "g_hclk_otg0", "g_pmu_hclk_otg0", "g_hclk_host0", "g_hclk_host1", "g_hclk_hsic", "g_hclk_usb_peri", "g_hp_ahb_arbi", "g_aclk_peri_niu", "g_h_emem_peri", "g_hclk_mem_peri", "g_hclk_nandc0", "g_hclk_nandc1";
					rockchip,suspend-clkgating-setting = <0xc00 0xc000>;
					#clock-cells = <0x1>;
					linux,phandle = <0x7a>;
					phandle = <0x7a>;
				};

				gate-clk@0180 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x180 0x4>;
					clocks = <0x27 0x5f 0x27 0x5e 0x5e 0x5e 0x5e 0x5e 0x5e 0x6a 0x6b 0x53 0x27 0x18 0x18 0x18>;
					clock-output-names = "g_aclk_gmac", "g_pclk_gmac", "g_hclk_gps", "g_hclk_sdmmc", "g_hclk_sdio0", "g_hclk_sdio1", "g_hclk_emmc", "g_hclk_hsadc", "g_hclk_tsp", "g_hsadc_0_tsp", "g_hsadc_1_tsp", "g_clk_27m_tsp", "g_aclk_peri_mmu", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
					linux,phandle = <0x7b>;
					phandle = <0x7b>;
				};

				gate-clk@0184 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x184 0x4>;
					clocks = <0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18>;
					clock-output-names = "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
				};

				gate-clk@0188 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x188 0x4>;
					clocks = <0x5d 0x5d 0x5d 0x5d 0x14 0x14 0x14 0x14 0x5c 0x5c 0x5c 0x5c 0x14 0x14 0x5d 0x5d>;
					clock-output-names = "g_pclk_pwm", "g_pclk_timer", "g_pclk_i2c0", "g_pclk_i2c1", "g_aclk_intmem", "g_clk_intmem0", "g_clk_intmem1", "g_clk_intmem2", "g_hclk_i2s", "g_hclk_rom", "g_hclk_spdif", "g_h_spdif_8ch", "g_aclk_dmac1", "g_aclk_strc_sys", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0xf2f1 0xf2f1>;
					#clock-cells = <0x1>;
					linux,phandle = <0xb4>;
					phandle = <0xb4>;
				};

				gate-clk@018c {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x18c 0x4>;
					clocks = <0x5d 0x5d 0x5d 0x5d 0x18 0x18 0x14 0x5c 0x14 0x5d 0x5d 0x5d 0x18 0x18 0x18 0x18>;
					clock-output-names = "reserved", "reserved", "g_p_efuse_1024", "g_pclk_tzpc", "reserved", "reserved", "g_aclk_crypto", "g_hclk_crypto", "g_aclk_ccp", "g_pclk_uart2", "g_p_efuse_256", "g_pclk_rkpwm", "reserved", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x833 0x833>;
					#clock-cells = <0x1>;
					linux,phandle = <0xa6>;
					phandle = <0xa6>;
				};

				gate-clk@0190 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x190 0x4>;
					clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x74 0x74 0x74 0x18 0x18 0x18 0x18>;
					clock-output-names = "clk_core0", "clk_core1", "clk_core2", "clk_core3", "clk_l2ram", "aclk_core_m0", "aclk_core_mp", "atclk_core", "pclk_dbg_src", "g_dbg_core_clk", "g_cs_dbg_clk", "g_pclk_core_niu", "reserved", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0xff1 0xff1>;
					#clock-cells = <0x1>;
					linux,phandle = <0xb2>;
					phandle = <0xb2>;
				};

				gate-clk@0194 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x194 0x4>;
					clocks = <0x28 0x2a 0x50 0x2b 0x8 0x8 0x8 0x17 0x13 0x1f 0x8 0x8 0x18 0x57 0x5a 0x5b>;
					clock-output-names = "clk_sdmmc", "clk_sdio0", "clk_sdio1", "clk_emmc", "clk_otgphy0", "clk_otgphy1", "clk_otgphy2", "clk_otg_adp", "g_clk_c2c_host", "g_clk_hsic_12m", "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1", "g_clk_wifi", "aclk_hevc", "clk_hevc_cabac", "clk_hevc_core";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
					linux,phandle = <0x9>;
					phandle = <0x9>;
				};

				gate-clk@0198 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x198 0x4>;
					clocks = <0x18 0x75 0x75 0x75 0x75 0x75 0x75 0x75 0x75 0x18 0x18 0x75 0x75 0x18 0x18 0x18>;
					clock-output-names = "reserved", "g_pclk_gpio1", "g_pclk_gpio2", "g_pclk_gpio3", "g_pclk_gpio4", "g_pclk_gpio5", "g_pclk_gpio6", "g_pclk_gpio7", "g_pclk_gpio8", "reserved", "reserved", "g_pclk_grf", "g_p_alive_niu", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x19fe 0x19fe>;
					#clock-cells = <0x1>;
					linux,phandle = <0x7>;
					phandle = <0x7>;
				};

				gate-clk@019c {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x19c 0x4>;
					clocks = <0x4c 0x76 0x46 0x76 0x18 0x46 0x76 0x4e 0x76 0x76 0x76 0x46 0x4e 0x4c 0x46 0x76>;
					clock-output-names = "reserved", "g_hclk_rga", "g_aclk_iep", "g_hclk_iep", "g_aclk_lcdc_iep", "g_aclk_lcdc0", "g_hclk_lcdc0", "g_aclk_lcdc1", "g_hclk_lcdc1", "g_h_vio_ahb", "g_hclk_vio_niu", "g_aclk_vio0_niu", "g_aclk_vio1_niu", "reserved", "g_aclk_vip", "g_hclk_vip";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
					linux,phandle = <0xb5>;
					phandle = <0xb5>;
				};

				gate-clk@01a0 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x1a0 0x4>;
					clocks = <0x77 0x76 0x4e 0x78 0x76 0x76 0x76 0x76 0x76 0x76 0x76 0x76 0x18 0x18 0x18 0x18>;
					clock-output-names = "g_pclkin_cif", "g_hclk_isp", "g_aclk_isp", "g_pclkin_isp", "g_p_mipi_dsi0", "g_p_mipi_dsi1", "g_p_mipi_csi", "g_pclk_lvds_phy", "g_pclk_edp_ctrl", "g_p_hdmi_ctrl", "g_hclk_vio2_h2p", "g_pclk_vio2_h2p", "reserved", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
					linux,phandle = <0xb>;
					phandle = <0xb>;
				};

				gate-clk@01a4 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x1a4 0x4>;
					clocks = <0x69 0x69 0x69 0x69 0x69 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18>;
					clock-output-names = "g_pclk_pmu", "g_pclk_intmem1", "g_pclk_pmu_niu", "g_pclk_sgrf", "g_pclk_gpio0", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x1f 0x1f>;
					#clock-cells = <0x1>;
					linux,phandle = <0x6>;
					phandle = <0x6>;
				};

				gate-clk@01a8 {
					compatible = "rockchip,rk3188-gate-clk";
					reg = <0x1a8 0x4>;
					clocks = <0x4f 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18 0x18>;
					clock-output-names = "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved";
					rockchip,suspend-clkgating-setting = <0x0 0x0>;
					#clock-cells = <0x1>;
				};
			};
		};
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x500>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x501>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x502>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x503>;
		};
	};

	interrupt-controller@ffc01000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		#address-cells = <0x0>;
		reg = <0xffc01000 0x1000 0xffc02000 0x1000>;
		linux,phandle = <0x2>;
		phandle = <0x2>;
	};

	arm-pmu {
		compatible = "arm,cortex-a12-pmu";
		interrupts = <0x0 0x97 0x4 0x0 0x98 0x4 0x0 0x99 0x4 0x0 0x9a 0x4>;
	};

	cpu_axi_bus {
		compatible = "rockchip,cpu_axi_bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		qos {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;

			cpup {
				reg = <0xffa80000 0x20>;
			};

			cpum_r {
				reg = <0xffa80080 0x20>;
			};

			cpum_w {
				reg = <0xffa80100 0x20>;
			};

			bus_dmac {
				reg = <0xffa90000 0x20>;
			};

			host {
				reg = <0xffa90080 0x20>;
			};

			crypto {
				reg = <0xffa90100 0x20>;
			};

			ccp {
				reg = <0xffa90180 0x20>;
			};

			ccs {
				reg = <0xffa90200 0x20>;
			};

			gpu_r {
				reg = <0xffaa0000 0x20>;
			};

			gpu_w {
				reg = <0xffaa0080 0x20>;
			};

			peri {
				reg = <0xffab0000 0x20>;
			};

			vio1_vop {
				reg = <0xffad0000 0x20>;
				rockchip,priority = <0x2 0x2>;
			};

			vio1_isp_w0 {
				reg = <0xffad0100 0x20>;
				rockchip,priority = <0x2 0x2>;
			};

			vio1_isp_w1 {
				reg = <0xffad0180 0x20>;
			};

			vio0_vop {
				reg = <0xffad0400 0x20>;
				rockchip,priority = <0x2 0x2>;
			};

			vio0_vip {
				reg = <0xffad0480 0x20>;
			};

			vio0_iep {
				reg = <0xffad0500 0x20>;
			};

			vio2_rga_r {
				reg = <0xffad0800 0x20>;
			};

			vio2_rga_w {
				reg = <0xffad0880 0x20>;
			};

			vio1_isp_r {
				reg = <0xffad0900 0x20>;
			};

			video {
				reg = <0xffae0000 0x20>;
			};

			hevc_r {
				reg = <0xffaf0000 0x20>;
			};

			hevc_w {
				reg = <0xffaf0080 0x20>;
			};
		};

		msch {
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;

			msch@0 {
				reg = <0xffac0000 0x40>;
				rockchip,read-latency = <0x34>;
			};

			msch@1 {
				reg = <0xffac0080 0x40>;
				rockchip,read-latency = <0x34>;
			};
		};
	};

	sram@ff710000 {
		compatible = "mmio-sram";
		reg = <0xff710000 0x8000>;
		map-exec;
		linux,phandle = <0x1>;
		phandle = <0x1>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04>;
		clock-frequency = <0x16e3600>;
	};

	timer@ff810000 {
		compatible = "rockchip,timer";
		reg = <0xff810000 0x20>;
		interrupts = <0x0 0x48 0x4>;
		rockchip,broadcast = <0x1>;
	};

	wdt@2004c000 {
		compatible = "rockchip,watch dog";
		reg = <0xff800000 0x100>;
		clocks = <0x75>;
		clock-names = "pclk_wdt";
		interrupts = <0x0 0x4f 0x4>;
		rockchip,irq = <0x0>;
		rockchip,timeout = <0x2>;
		rockchip,atboot = <0x1>;
		rockchip,debug = <0x0>;
		status = "disabled";
	};

	amba {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <0x2>;
		ranges;

		pdma@ffb20000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xffb20000 0x4000>;
			interrupts = <0x0 0x0 0x4 0x0 0x1 0x4>;
			#dma-cells = <0x1>;
			linux,phandle = <0xa7>;
			phandle = <0xa7>;
		};

		pdma@ff250000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xff250000 0x4000>;
			interrupts = <0x0 0x2 0x4 0x0 0x3 0x4>;
			#dma-cells = <0x1>;
			linux,phandle = <0x9d>;
			phandle = <0x9d>;
		};
	};

	reset@ff7601b8 {
		compatible = "rockchip,reset";
		reg = <0xff7601b8 0x30>;
		rockchip,reset-flag = <0x1>;
		#reset-cells = <0x1>;
		linux,phandle = <0xe4>;
		phandle = <0xe4>;
	};

	nandc@0xff400000 {
		compatible = "rockchip,rk-nandc";
		reg = <0xff400000 0x4000>;
		interrupts = <0x0 0x26 0x4>;
		nandc_id = <0x0>;
		clocks = <0x54 0x79 0x5 0x7a 0xe>;
		clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
		status = "okay";
	};

	nandc@0xff410000 {
		compatible = "rockchip,rk-nandc";
		reg = <0xff410000 0x4000>;
		interrupts = <0x0 0x28 0x4>;
		nandc_id = <0x1>;
		clocks = <0x55 0x79 0x6 0x7a 0xf>;
		clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
		status = "disabled";
	};

	nandc0@0xff400000 {
		compatible = "rockchip,rk-nandc";
		reg = <0xff400000 0x4000>;
		status = "disabled";
	};

	rksdmmc@ff0f0000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
		reg = <0xff0f0000 0x4000>;
		interrupts = <0x0 0x23 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		clocks = <0x2b 0x7b 0x6>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <0x1>;
		fifo-depth = <0x100>;
		bus-width = <0x8>;
		clock-frequency = <0x5f5e100>;
		clock-freq-min-max = <0x61a80 0x5f5e100>;
		supports-highspeed;
		supports-emmc;
		bootpart-no-access;
		supports-DDR_MODE;
		caps2-mmc-hs200;
		ignore-pm-notify;
		keep-power-in-suspend;
		status = "okay";
	};

	rksdmmc@ff0c0000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
		reg = <0xff0c0000 0x4000>;
		interrupts = <0x0 0x20 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "idle";
		pinctrl-0 = <0x7c 0x7d 0x7e 0x7f>;
		pinctrl-1 = <0x80>;
		cd-gpios = <0x81 0x16 0x0>;
		clocks = <0x28 0x7b 0x3>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <0x1>;
		fifo-depth = <0x100>;
		bus-width = <0x4>;
		clock-frequency = <0x2faf080>;
		lock-freq-min-max = <0x61a80 0x2faf080>;
		supports-highspeed;
		supports-sd;
		broken-cd;
		card-detect-delay = <0xc8>;
		ignore-pm-notify;
		keep-power-in-suspend;
		vmmc-supply = <0x82>;
		status = "okay";
	};

	rksdmmc@ff0d0000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
		reg = <0xff0d0000 0x4000>;
		interrupts = <0x0 0x21 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "idle";
		pinctrl-0 = <0x83 0x84 0x85 0x86 0x87 0x88 0x89>;
		pinctrl-1 = <0x8a>;
		clocks = <0x2a 0x7b 0x4>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <0x1>;
		fifo-depth = <0x100>;
		bus-width = <0x4>;
		clock-frequency = <0x2faf080>;
		clock-freq-min-max = <0x30d40 0x2faf080>;
		supports-highspeed;
		supports-sdio;
		ignore-pm-notify;
		keep-power-in-suspend;
		status = "okay";
	};

	rksdmmc@ff0e0000 {
		compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
		reg = <0xff0e0000 0x4000>;
		interrupts = <0x0 0x22 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		clocks = <0x50 0x7b 0x5>;
		clock-names = "clk_mmc", "hclk_mmc";
		num-slots = <0x1>;
		fifo-depth = <0x100>;
		bus-width = <0x4>;
		status = "disabled";
	};

	spi@ff110000 {
		compatible = "rockchip,rockchip-spi";
		reg = <0xff110000 0x1000>;
		interrupts = <0x0 0x2c 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default";
		pinctrl-0 = <0x8b 0x8c 0x8d 0x8e 0x8f>;
		rockchip,spi-src-clk = <0x0>;
		num-cs = <0x2>;
		clocks = <0x3d 0x90 0x4>;
		clock-names = "spi", "pclk_spi0";
		status = "disabled";
		max-freq = <0x2dc6c00>;
	};

	spi@ff120000 {
		compatible = "rockchip,rockchip-spi";
		reg = <0xff120000 0x1000>;
		interrupts = <0x0 0x2d 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default";
		pinctrl-0 = <0x91 0x92 0x93 0x94>;
		rockchip,spi-src-clk = <0x1>;
		num-cs = <0x1>;
		clocks = <0x3e 0x90 0x5>;
		clock-names = "spi", "pclk_spi1";
		status = "disabled";
		max-freq = <0x2dc6c00>;

		tstv-ctrl@00 {
			compatible = "rockchip,dtv_spi_ctrl";
			gpio-powerup = <0x95 0x1f 0x0>;
			gpio-powerdown = <0x96 0xe 0x0>;
			gpio-reset = <0x96 0xf 0x0>;
			gpio-nreset = <0x96 0xc 0x0>;
			spi-max-frequency = <0xb71b00>;
			reg = <0x0>;
			poll_mode = <0x0>;
			type = <0x0>;
			enable_dma = <0x0>;
		};
	};

	spi@ff130000 {
		compatible = "rockchip,rockchip-spi";
		reg = <0xff130000 0x1000>;
		interrupts = <0x0 0x2e 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default";
		pinctrl-0 = <0x97 0x98 0x99 0x9a 0x9b>;
		rockchip,spi-src-clk = <0x2>;
		num-cs = <0x2>;
		clocks = <0x56 0x90 0x6>;
		clock-names = "spi", "pclk_spi2";
		status = "disabled";
		max-freq = <0x2dc6c00>;
	};

	rockchip-hsadc@ff080000 {
		compatible = "rockchip-hsadc";
		reg = <0xff080000 0x4000>;
		interrupts = <0x0 0x1f 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default";
		pinctrl-0 = <0x9c>;
		clocks = <0x7b 0x7 0xa 0x3b>;
		clock-names = "hclk_hsadc", "clk_hsadc_out", "clk_hsadc_ext";
		dmas = <0x9d 0x0>;
		dma-names = "data";
		status = "disabled";
	};

	serial@ff180000 {
		compatible = "rockchip,serial";
		reg = <0xff180000 0x100>;
		interrupts = <0x0 0x37 0x4>;
		clock-frequency = <0x16e3600>;
		clocks = <0x9e 0x90 0x8>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x9d 0x1 0x9d 0x2>;
		#dma-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0x9f 0xa0>;
		status = "okay";
		dma-names = "!tx", "!rx";
	};

	serial@ff190000 {
		compatible = "rockchip,serial";
		reg = <0xff190000 0x100>;
		interrupts = <0x0 0x38 0x4>;
		clock-frequency = <0x16e3600>;
		clocks = <0xa1 0x90 0x9>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x9d 0x3 0x9d 0x4>;
		#dma-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xa2 0xa3 0xa4>;
		status = "disabled";
	};

	serial@ff690000 {
		compatible = "rockchip,serial";
		reg = <0xff690000 0x100>;
		interrupts = <0x0 0x39 0x4>;
		clock-frequency = <0x16e3600>;
		clocks = <0xa5 0xa6 0x9>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0xa7 0x4 0xa7 0x5>;
		#dma-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xa8>;
		status = "disabled";
	};

	serial@ff1b0000 {
		compatible = "rockchip,serial";
		reg = <0xff1b0000 0x100>;
		interrupts = <0x0 0x3a 0x4>;
		clock-frequency = <0x16e3600>;
		clocks = <0xa9 0x90 0xb>;
		clock-names = "sclk_uart", "pclk_uart";
		current-speed = <0x1c200>;
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x9d 0x7 0x9d 0x8>;
		#dma-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xaa 0xab 0xac>;
		status = "disabled";
	};

	serial@ff1c0000 {
		compatible = "rockchip,serial";
		reg = <0xff1c0000 0x100>;
		interrupts = <0x0 0x3b 0x4>;
		clock-frequency = <0x16e3600>;
		clocks = <0xad 0x90 0xc>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x9d 0x9 0x9d 0xa>;
		#dma-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xae 0xaf 0xb0>;
		status = "disabled";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <0x2>;
		rockchip,signal-irq = <0x6a>;
		rockchip,wake-irq = <0x0>;
		status = "okay";
	};

	clocks-init {
		compatible = "rockchip,clocks-init";
		rockchip,clocks-init-parent = <0xf 0x10 0x13 0x16 0x27 0x16 0x19 0x16 0x1c 0x16 0x21 0x16 0x31 0x2f>;
		rockchip,clocks-init-rate = <0xf 0xcdfe600 0x16 0x23c34600 0x43 0x1c52fa0 0x25 0x4a817c80 0x13 0x11e1a300 0x14 0x11e1a300 0x5c 0x8f0d180 0x5d 0x47868c0 0x68 0x8f0d180 0x27 0x11e1a300 0x5e 0x8f0d180 0x5f 0x47868c0 0x4f 0xbebc200 0x46 0x11e1a300 0x4e 0x11e1a300 0x76 0x47868c0 0x75 0x5f5e100 0x69 0x5f5e100 0x57 0x17d78400 0xb1 0xbebc200 0x5a 0x11e1a300 0x5b 0x11e1a300 0x4c 0x11e1a300 0x4d 0x11e1a300 0xc 0x11e1a300 0xd 0x11e1a300 0x45 0xbebc200 0x24 0xbebc200 0x26 0x17d78400 0x51 0x4c4b400 0x52 0x4c4b400 0x67 0x7735940>;
	};

	clocks-enable {
		compatible = "rockchip,clocks-enable";
		clocks = <0x11 0x2 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0xb2 0x9 0xb2 0xa 0xb2 0xb 0x14 0x11 0x3 0x5c 0x5d 0x9 0x8 0x68 0x11 0x7 0xb3 0x0 0xb3 0x1 0xb3 0x2 0xb3 0x3 0xb3 0x4 0xb3 0x5 0x75 0x69 0x27 0x5e 0x5f 0xb4 0x5 0xb4 0x6 0xb4 0x7 0xb4 0xc 0xb4 0xd 0xb4 0x4 0xa6 0x6 0xa6 0x8 0xa6 0x7 0xb4 0x9 0xb4 0x1 0xb4 0x9 0xb4 0xd 0xb2 0x8 0x90 0x2 0x90 0x3 0x7a 0xb 0x7b 0xc 0x90 0x0 0x7a 0xa 0x7a 0xc 0x7a 0xd 0x90 0x1 0x7 0xb 0x7 0xc 0x6 0x0 0x6 0x1 0x6 0x2 0x6 0x3 0xb5 0x9 0xb5 0xa 0xb 0xa 0xb 0xb 0xb5 0xb 0xb5 0xc 0xa6 0x9 0xb6 0x6 0x7b 0x7 0x31>;
	};

	i2c@ff650000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff650000 0x1000>;
		interrupts = <0x0 0x3c 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xb7 0xb8>;
		pinctrl-1 = <0xb9>;
		gpios = <0x95 0xf 0x1 0x95 0x10 0x1>;
		clocks = <0xb4 0x2>;
		rockchip,check-idle = <0x1>;
		status = "okay";

		rk808@1b {
			reg = <0x1b>;
			status = "okay";
			compatible = "rockchip,rk808";
			gpios = <0x95 0x4 0x0 0x95 0xb 0x1>;
			rk808,system-power-controller;

			regulators {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				regulator@0 {
					reg = <0x0>;
					regulator-compatible = "rk_dcdc1";
					regulator-min-microvolt = <0xaae60>;
					regulator-max-microvolt = <0x16e360>;
					regulator-initial-mode = <0x2>;
					regulator-initial-state = <0x3>;
					regulator-name = "vdd_arm";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-mode = <0x2>;
						regulator-state-disabled;
						regulator-state-uv = <0xdbba0>;
					};
				};

				regulator@1 {
					reg = <0x1>;
					regulator-compatible = "rk_dcdc2";
					regulator-min-microvolt = <0xaae60>;
					regulator-max-microvolt = <0x16e360>;
					regulator-initial-mode = <0x2>;
					regulator-initial-state = <0x3>;
					regulator-name = "vdd_gpu";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-mode = <0x2>;
						regulator-state-disabled;
						regulator-state-uv = <0xdbba0>;
					};
				};

				regulator@2 {
					reg = <0x2>;
					regulator-compatible = "rk_dcdc3";
					regulator-initial-mode = <0x2>;
					regulator-initial-state = <0x3>;
					regulator-name = "rk_dcdc3";
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-mode = <0x2>;
						regulator-state-enabled;
						regulator-state-uv = <0x124f80>;
					};
				};

				regulator@3 {
					reg = <0x3>;
					regulator-compatible = "rk_dcdc4";
					regulator-initial-mode = <0x2>;
					regulator-initial-state = <0x3>;
					regulator-name = "vccio";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-mode = <0x2>;
						regulator-state-enabled;
						regulator-state-uv = <0x2ab980>;
					};
				};

				regulator@4 {
					reg = <0x4>;
					regulator-compatible = "rk_ldo1";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo1";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x325aa0>;
					};
				};

				regulator@5 {
					reg = <0x5>;
					regulator-compatible = "rk_ldo2";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo2";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x325aa0>;
					};
				};

				regulator@6 {
					reg = <0x6>;
					regulator-compatible = "rk_ldo3";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo3";
					regulator-min-microvolt = <0xf4240>;
					regulator-max-microvolt = <0xf4240>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0xf4240>;
					};
				};

				regulator@7 {
					reg = <0x7>;
					regulator-compatible = "rk_ldo4";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo4";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-disabled;
						regulator-state-uv = <0x1b7740>;
					};
				};

				regulator@8 {
					reg = <0x8>;
					regulator-compatible = "rk_ldo5";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo5";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x2ab980>;
					};
				};

				regulator@9 {
					reg = <0x9>;
					regulator-compatible = "rk_ldo6";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo6";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-disabled;
						regulator-state-uv = <0xf4240>;
					};
				};

				regulator@10 {
					reg = <0xa>;
					regulator-compatible = "rk_ldo7";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo7";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x1b7740>;
					};
				};

				regulator@11 {
					reg = <0xb>;
					regulator-compatible = "rk_ldo8";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo8";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x325aa0>;
					};
				};

				regulator@12 {
					reg = <0xc>;
					regulator-compatible = "rk_ldo9";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo9";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-enabled;
					};
				};

				regulator@13 {
					reg = <0xd>;
					regulator-compatible = "rk_ldo10";
					regulator-initial-state = <0x3>;
					regulator-name = "rk_ldo10";
					regulator-always-on;
					regulator-boot-on;

					regulator-state-mem {
						regulator-state-disabled;
					};
				};
			};
		};

		syr827@40 {
			compatible = "silergy,syr82x";
			reg = <0x40>;
			status = "okay";

			regulators {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				regulator@0 {
					reg = <0x0>;
					regulator-compatible = "syr82x_dcdc1";
					regulator-name = "vdd_arm";
					regulator-min-microvolt = <0xadf34>;
					regulator-max-microvolt = <0x16e360>;
					regulator-always-on;
					regulator-boot-on;
					regulator-initial-mode = <0x2>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-mode = <0x2>;
						regulator-state-enabled;
						regulator-state-uv = <0xdbba0>;
					};
				};
			};
		};

		syr828@41 {
			compatible = "silergy,syr82x";
			reg = <0x41>;
			status = "okay";

			regulators {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				regulator@0 {
					reg = <0x0>;
					regulator-compatible = "syr82x_dcdc1";
					regulator-name = "vdd_gpu";
					regulator-min-microvolt = <0xadf34>;
					regulator-max-microvolt = <0x16e360>;
					regulator-always-on;
					regulator-boot-on;
					regulator-initial-mode = <0x2>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-mode = <0x2>;
						regulator-state-disabled;
						regulator-state-uv = <0xdbba0>;
					};
				};
			};
		};

		act8846@5a {
			reg = <0x5a>;
			status = "okay";
			compatible = "act,act8846";
			gpios = <0x4 0x1 0x1 0x95 0x2 0x1 0x95 0x1 0x1>;
			act8846,system-power-controller;

			regulators {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				regulator@0 {
					reg = <0x0>;
					regulator-compatible = "act_dcdc1";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "act_dcdc1";
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
				};

				regulator@1 {
					reg = <0x1>;
					regulator-compatible = "act_dcdc2";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vccio";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x325aa0>;
					};
				};

				regulator@2 {
					reg = <0x2>;
					regulator-compatible = "act_dcdc3";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vdd_logic";
					regulator-min-microvolt = <0xaae60>;
					regulator-max-microvolt = <0x16e360>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x124f80>;
					};
				};

				regulator@3 {
					reg = <0x3>;
					regulator-compatible = "act_dcdc4";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "act_dcdc4";
					regulator-min-microvolt = <0x1e8480>;
					regulator-max-microvolt = <0x1e8480>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-enabled;
						regulator-state-uv = <0x1e8480>;
					};
				};

				regulator@4 {
					reg = <0x4>;
					regulator-compatible = "act_ldo1";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vccio_sd";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					linux,phandle = <0x82>;
					phandle = <0x82>;
				};

				regulator@5 {
					reg = <0x5>;
					regulator-compatible = "act_ldo2";
					regulator-boot-on;
					regulator-name = "act_ldo2";
					regulator-min-microvolt = <0x100590>;
					regulator-max-microvolt = <0x100590>;
				};

				regulator@6 {
					reg = <0x6>;
					regulator-compatible = "act_ldo3";
					regulator-boot-on;
					regulator-name = "act_ldo3";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
				};

				regulator@7 {
					reg = <0x7>;
					regulator-compatible = "act_ldo4";
					regulator-boot-on;
					regulator-name = "act_ldo4";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
				};

				regulator@8 {
					reg = <0x8>;
					regulator-compatible = "act_ldo5";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "act_ldo5";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
				};

				regulator@9 {
					reg = <0x9>;
					regulator-compatible = "act_ldo6";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "act_ldo6";
					regulator-min-microvolt = <0x10c8e0>;
					regulator-max-microvolt = <0x10c8e0>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-enabled;
					};
				};

				regulator@10 {
					reg = <0xa>;
					regulator-compatible = "act_ldo7";
					regulator-always-on;
					regulator-boot-on;
					regulator-name = "vcc_18";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-initial-state = <0x3>;

					regulator-state-mem {
						regulator-state-enabled;
					};
				};

				regulator@11 {
					reg = <0xb>;
					regulator-compatible = "act_ldo8";
					regulator-boot-on;
					regulator-name = "act_ldo8";
					regulator-min-microvolt = <0x1c3a90>;
					regulator-max-microvolt = <0x1c3a90>;
				};
			};
		};

		rtc@51 {
			compatible = "rtc,hym8563";
			reg = <0x51>;
			irq_gpio = <0x95 0x4 0x2>;
		};
	};

	i2c@ff140000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff140000 0x1000>;
		interrupts = <0x0 0x3e 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xba 0xbb>;
		pinctrl-1 = <0xbc>;
		gpios = <0x3 0x4 0x1 0x3 0x5 0x1>;
		clocks = <0xb4 0x3>;
		rockchip,check-idle = <0x1>;
		status = "okay";

		lt8641ex@3f {
			compatible = "tchip,lt8641ex";
			gpio-sw = <0x4 0xa 0x1>;
			reg = <0x3f>;
		};

		rtc@51 {
			compatible = "nxp,pcf8563";
			reg = <0x51>;
		};
	};

	i2c@ff660000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff660000 0x1000>;
		interrupts = <0x0 0x3d 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xbd 0xbe>;
		pinctrl-1 = <0xbf>;
		gpios = <0x81 0x9 0x1 0x81 0xa 0x1>;
		clocks = <0x90 0xd>;
		rockchip,check-idle = <0x1>;
		status = "okay";
	};

	i2c@ff150000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff150000 0x1000>;
		interrupts = <0x0 0x3f 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xc0 0xc1>;
		pinctrl-1 = <0xc2>;
		gpios = <0x96 0x11 0x1 0x96 0x10 0x1>;
		clocks = <0x90 0xe>;
		rockchip,check-idle = <0x1>;
		status = "okay";
	};

	i2c@ff160000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff160000 0x1000>;
		interrupts = <0x0 0x40 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xc3 0xc4>;
		pinctrl-1 = <0xc5>;
		gpios = <0x4 0x11 0x1 0x4 0x12 0x1>;
		clocks = <0x90 0xf>;
		rockchip,check-idle = <0x1>;
		status = "okay";

		rk1000_control@40 {
			compatible = "rockchip,rk1000_control";
			reg = <0x40>;
			gpio-reset = <0x4 0x15 0x1>;
			clocks = <0x20 0x63>;
			clock-names = "i2s_clk", "i2s_mclk";
		};

		rk1000_tve@42 {
			compatible = "rockchip,rk1000_tve";
			reg = <0x42>;
			rockchip,source = <0x0>;
			rockchip,prop = <0x1>;
		};

		rk1000_codec@60 {
			compatible = "rockchip,rk1000_codec";
			reg = <0x60>;
			spk_ctl_io = <0x4 0x5 0x1>;
			boot_depop = <0x1>;
			pa_enable_time = <0x1388>;
			linux,phandle = <0x119>;
			phandle = <0x119>;
		};
	};

	i2c@ff170000 {
		compatible = "rockchip,rk30-i2c";
		reg = <0xff170000 0x1000>;
		interrupts = <0x0 0x41 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xc6 0xc7>;
		pinctrl-1 = <0xc8>;
		gpios = <0x4 0x13 0x1 0x4 0x14 0x1>;
		clocks = <0x7a 0x0>;
		rockchip,check-idle = <0x1>;
		status = "disabled";
	};

	fb {
		compatible = "rockchip,rk-fb";
		rockchip,disp-mode = <0x2>;
	};

	rk_screen {
		compatible = "rockchip,screen";
		display-timings = <0xc9>;
	};

	mipi@ff960000 {
		compatible = "rockchip,rk32-dsi";
		rockchip,prop = <0x0>;
		reg = <0xff960000 0x4000>;
		interrupts = <0x0 0x13 0x4>;
		clocks = <0x79 0xf 0xb 0x4 0xca>;
		clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
		status = "disabled";
	};

	mipi@ff964000 {
		compatible = "rockchip,rk32-dsi";
		rockchip,prop = <0x1>;
		reg = <0xff964000 0x4000>;
		interrupts = <0x0 0x14 0x4>;
		clocks = <0x79 0xf 0xb 0x5 0xca>;
		clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
		status = "disabled";
	};

	lvds@ff96c000 {
		compatible = "rockchip,rk32-lvds";
		reg = <0xff96c000 0x4000>;
		clocks = <0xb 0x7>;
		clock-names = "pclk_lvds";
	};

	edp@ff970000 {
		compatible = "rockchip,rk32-edp";
		reg = <0xff970000 0x4000>;
		interrupts = <0x0 0x62 0x4>;
		clocks = <0x45 0x62 0xb 0x8>;
		clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
	};

	hdmi@ff980000 {
		compatible = "rockchip,rk3288-hdmi";
		reg = <0xff980000 0x20000>;
		interrupts = <0x0 0x67 0x4>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xc6 0xc7 0xcb>;
		pinctrl-1 = <0xc8>;
		clocks = <0xb 0x9 0x79 0xc 0x79 0xb>;
		clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
		status = "okay";
		rockchips,hdmi_audio_source = <0x0>;
		hdmi_cec = <0x1>;
		hdcp_enable = <0x0>;
	};

	lcdc@ff930000 {
		compatible = "rockchip,rk3288-lcdc";
		rockchip,prop = <0x1>;
		rockchip,pwr18 = <0x0>;
		rockchip,iommu-enabled = <0x1>;
		reg = <0xff930000 0x10000>;
		interrupts = <0x0 0xf 0x4>;
		status = "okay";
		clocks = <0xb5 0x5 0x44 0xb5 0x6 0xcc>;
		clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
	};

	lcdc@ff940000 {
		compatible = "rockchip,rk3288-lcdc";
		rockchip,prop = <0x2>;
		rochchip,pwr18 = <0x0>;
		rockchip,iommu-enabled = <0x1>;
		reg = <0xff940000 0x10000>;
		interrupts = <0x0 0x10 0x4>;
		pinctrl-names = "default", "gpio";
		pinctrl-0 = <0xcd>;
		pinctrl-1 = <0xce>;
		status = "disabled";
		clocks = <0xb5 0x7 0x4b 0xb5 0x8 0xcf>;
		clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
	};

	adc@ff100000 {
		compatible = "rockchip,saradc";
		reg = <0xff100000 0x100>;
		interrupts = <0x0 0x24 0x4>;
		#io-channel-cells = <0x1>;
		io-channel-ranges;
		rockchip,adc-vref = <0x708>;
		clock-frequency = <0xf4240>;
		clocks = <0x61 0x7a 0x1>;
		clock-names = "saradc", "pclk_saradc";
		status = "okay";
		linux,phandle = <0xd0>;
		phandle = <0xd0>;

		key {
			compatible = "rockchip,key";
			io-channels = <0xd0 0x1>;

			power-key {
				gpios = <0x95 0x5 0x1>;
				linux,code = <0x74>;
				label = "power";
				gpio-key,wakeup;
			};
		};
	};

	rga@ff920000 {
		compatible = "rockchip,rga";
		reg = <0xff920000 0x1000>;
		interrupts = <0x0 0x12 0x4>;
		clocks = <0xb5 0x1 0x4c 0x4d>;
		clock-names = "hclk_rga", "aclk_rga", "clk_rga";
	};

	rockchip-i2s@0xff890000 {
		compatible = "rockchip-i2s";
		reg = <0xff890000 0x10000>;
		i2s-id = <0x0>;
		clocks = <0x20 0x63 0xb4 0x8>;
		clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
		interrupts = <0x0 0x35 0x4>;
		dmas = <0xa7 0x0 0xa7 0x1>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
		pinctrl-1 = <0xda>;
		linux,phandle = <0x116>;
		phandle = <0x116>;
	};

	rockchip-spdif@0xff8b0000 {
		compatible = "rockchip-spdif";
		reg = <0xff8b0000 0x10000>;
		clocks = <0x64 0x65 0xb4 0xb>;
		clock-names = "spdif_mclk", "spdif_8ch_mclk", "spdif_hclk";
		interrupts = <0x0 0x56 0x4>;
		dmas = <0xa7 0x3>;
		dma-names = "tx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <0xdb>;
		pinctrl-1 = <0xdc>;
		linux,phandle = <0x118>;
		phandle = <0x118>;
	};

	pwm@ff9401a0 {
		compatible = "rockchip,vop-pwm";
		reg = <0xff9401a0 0x10>;
		#pwm-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xdd>;
		clocks = <0x9 0xb>;
		clock-names = "pclk_pwm";
		status = "disabled";
	};

	pwm@ff9301a0 {
		compatible = "rockchip,vop-pwm";
		ir-led-gpio = <0x3 0x3 0x1>;
		reg = <0xff9301a0 0x10>;
		#pwm-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xde>;
		clocks = <0x9 0xa>;
		clock-names = "pclk_pwm";
		status = "disabled";
	};

	pwm@ff680000 {
		compatible = "rockchip,rk-pwm0";
		reg = <0xff680000 0x10>;
		#pwm-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xdf>;
		clocks = <0xa6 0xb>;
		clock-names = "pclk_pwm";
		status = "okay";
		ir-emission-gpio = <0x95 0xa 0x1>;
		interrupts = <0x0 0x4e 0x4>;
	};

	pwm@ff680010 {
		compatible = "rockchip,rk-pwm";
		reg = <0xff680010 0x10>;
		#pwm-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xe0>;
		clocks = <0xa6 0xb>;
		clock-names = "pclk_pwm";
		status = "disabled";
		linux,phandle = <0x114>;
		phandle = <0x114>;
	};

	pwm@ff680020 {
		compatible = "rockchip,rk-pwm";
		reg = <0xff680020 0x10>;
		#pwm-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xe1>;
		clocks = <0xa6 0xb>;
		clock-names = "pclk_pwm";
		status = "disabled";
	};

	pwm@ff680030 {
		compatible = "rockchip,rk-pwm";
		reg = <0xff680030 0x10>;
		#pwm-cells = <0x2>;
		pinctrl-names = "default";
		pinctrl-0 = <0xe2>;
		clocks = <0xa6 0xb>;
		clock-names = "pclk_pwm";
		status = "disabled";
	};

	dvfs {

		vd_arm {
			regulator_name = "vdd_arm";
			suspend_volt = <0x3e8>;

			pd_core {

				clk_core {
					operating-points = <0x4c2c0 0x10c8e0 0x7b0c0 0x10c8e0 0xc7380 0x10c8e0 0xf6180 0x10c8e0>;
					channel = <0x0>;
					temp-limit-enable = <0x1>;
					target-temp = <0x5f>;
					normal-temp-limit = <0x3 0x17700 0x6 0x23280 0x9 0x2ee00 0xf 0x5dc00>;
					performance-temp-limit = <0x64 0xc7380>;
					status = "okay";
					support-pvtm = <0x0>;
					pvtm-operating-points = <0x1ec30 0xdbba0 0x61a8 0x34bc0 0xdbba0 0x61a8 0x4c2c0 0xdbba0 0x61a8 0x639c0 0xdbba0 0x61a8 0x927c0 0xe7ef0 0xc350 0xa9ec0 0xe7ef0 0xc350 0xc7380 0xf4240 0xc350 0xf6180 0x100590 0x124f8 0x124f80 0x10c8e0 0x124f8 0x159b40 0x124f80 0x124f8 0x171240 0x13d620 0x124f8 0x188940 0x149970 0x124f8 0x1a0040 0x149970 0x124f8 0x1b7740 0x149970 0x124f8>;
				};
			};
		};

		vd_logic {
			regulator_name = "vdd_logic";
			suspend_volt = <0x3e8>;

			pd_ddr {

				clk_ddr {
					operating-points = <0x30d40 0x106738 0xc15c0 0x149970>;
					channel = <0x2>;
					status = "okay";
					freq-table = <0x1 0xc15c0 0x2 0x30d40 0x10 0xc15c0 0x2000 0xc15c0>;
					auto-freq-table = <0x3a980 0x4f1a0 0x6f540 0x80e80>;
					auto-freq = <0x0>;
				};
			};

			pd_vio {

				aclk_vio1 {
					operating-points = <0x186a0 0x10c8e0 0x7a120 0x10c8e0>;
					status = "okay";
				};
			};
		};

		vd_gpu {
			regulator_name = "vdd_gpu";
			suspend_volt = <0x3e8>;

			pd_gpu {

				clk_gpu {
					operating-points = <0x30d40 0xdbba0 0x493e0 0xe7ef0 0x668a0 0x10c8e0 0x7a120 0x118c30 0x927c0 0x1312d0>;
					channel = <0x1>;
					status = "okay";
				};
			};
		};
	};

	ion {
		compatible = "rockchip,ion";
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		rockchip,ion-heap@3 {
			rockchip,ion_heap = <0x3>;
		};
	};

	vpu_service@ff9a0000 {
		compatible = "vpu_service";
		iommu_enabled = <0x1>;
		reg = <0xff9a0000 0x800>;
		interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
		interrupt-names = "irq_enc", "irq_dec";
		clocks = <0xd 0xe3>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
	};

	hevc_service@ff9c0000 {
		compatible = "rockchip,hevc_service";
		iommu_enabled = <0x1>;
		reg = <0xff9c0000 0x800>;
		interrupts = <0x0 0xc 0x4>;
		interrupt-names = "irq_dec";
		clocks = <0x57 0xb1 0x5b 0x5a>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
	};

	iep@ff900000 {
		compatible = "rockchip,iep";
		iommu_enabled = <0x1>;
		reg = <0xff900000 0x800>;
		interrupts = <0x0 0x11 0x4>;
		clocks = <0xb5 0x2 0xb5 0x3>;
		clock-names = "aclk_iep", "hclk_iep";
		status = "okay";
	};

	dwc-control-usb@ff770284 {
		compatible = "rockchip,rk3288-dwc-control-usb";
		reg = <0xff770284 0x4 0xff770288 0x4 0xff7702cc 0x4 0xff7702d4 0x4 0xff770320 0x14 0xff770334 0x14 0xff770348 0x10 0xff770358 0x8 0xff770360 0x8>;
		reg-names = "GRF_SOC_STATUS1", "GRF_SOC_STATUS2", "GRF_SOC_STATUS19", "GRF_SOC_STATUS21", "GRF_UOC0_BASE", "GRF_UOC1_BASE", "GRF_UOC2_BASE", "GRF_UOC3_BASE", "GRF_UOC4_BASE";
		interrupts = <0x0 0x5d 0x4 0x0 0x5e 0x4 0x0 0x5f 0x4 0x0 0x60 0x4 0x0 0x61 0x4>;
		interrupt-names = "otg_id", "otg_bvalid", "otg_linestate", "host0_linestate", "host1_linestate";
		clocks = <0x7a 0x9 0x31 0x2e 0x2f>;
		clock-names = "hclk_usb_peri", "usbphy_480m", "usbphy1_480m", "usbphy2_480m";

		usb_bc {
			compatible = "synopsys,phy";
			rk_usb,bvalid = <0x288 0xe 0x1>;
			rk_usb,iddig = <0x288 0x11 0x1>;
			rk_usb,dcdenb = <0x328 0xe 0x1>;
			rk_usb,vdatsrcenb = <0x328 0x7 0x1>;
			rk_usb,vdatdetenb = <0x328 0x6 0x1>;
			rk_usb,chrgsel = <0x328 0x5 0x1>;
			rk_usb,chgdet = <0x2cc 0x17 0x1>;
			rk_usb,fsvminus = <0x2cc 0x19 0x1>;
			rk_usb,fsvplus = <0x2cc 0x18 0x1>;
		};
	};

	usb@ff580000 {
		compatible = "rockchip,rk3288_usb20_otg";
		reg = <0xff580000 0x40000>;
		interrupts = <0x0 0x17 0x4>;
		clocks = <0x9 0x4 0x7a 0x4>;
		clock-names = "clk_usbphy0", "hclk_usb0";
		resets = <0xe4 0x84 0xe4 0x85 0xe4 0x86>;
		reset-names = "otg_ahb", "otg_phy", "otg_controller";
		rockchip,usb-mode = <0x1>;
	};

	usb@ff540000 {
		compatible = "rockchip,rk3288_usb20_host";
		reg = <0xff540000 0x40000>;
		interrupts = <0x0 0x19 0x4>;
		clocks = <0x9 0x6 0x7a 0x7 0x31>;
		clock-names = "clk_usbphy1", "hclk_usb1", "usbphy_480m";
		resets = <0xe4 0x8a 0xe4 0x8b 0xe4 0x8c>;
		reset-names = "host1_ahb", "host1_phy", "host1_controller";
	};

	usb@ff500000 {
		compatible = "rockchip,rk3288_rk_ehci_host";
		reg = <0xff500000 0x20000>;
		interrupts = <0x0 0x18 0x4>;
		clocks = <0x9 0x5 0x7a 0x6>;
		clock-names = "clk_usbphy2", "hclk_usb2";
		resets = <0xe4 0x87 0xe4 0x88 0xe4 0x89 0xe4 0x48>;
		reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
	};

	usb@ff520000 {
		compatible = "rockchip,rk3288_rk_ohci_host";
		reg = <0xff520000 0x20000>;
		interrupts = <0x0 0x29 0x4>;
		clocks = <0x9 0x5 0x7a 0x6>;
		clock-names = "clk_usbphy3", "hclk_usb3";
	};

	hsic@ff5c0000 {
		compatible = "rockchip,rk3288_rk_hsic_host";
		reg = <0xff5c0000 0x40000>;
		interrupts = <0x0 0x1a 0x4>;
		clocks = <0x29 0x7a 0x8 0xe5 0x31 0x2e 0x2f>;
		clock-names = "hsicphy_480m", "hclk_hsic", "hsicphy_12m", "usbphy_480m", "hsic_usbphy1", "hsic_usbphy2";
		resets = <0xe4 0x49 0xe4 0x4a 0xe4 0x4b>;
		reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
	};

	eth@ff290000 {
		compatible = "rockchip,rk3288-gmac";
		reg = <0xff290000 0x10000>;
		interrupts = <0x0 0x1b 0x4>;
		interrupt-names = "macirq";
		clocks = <0x67 0x79 0x0 0x79 0x1 0x79 0x2 0x79 0x3 0x7b 0x0 0x7b 0x1>;
		clock-names = "clk_mac", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac";
		phy-mode = "rgmii";
		pinctrl-names = "default";
		pinctrl-0 = <0xe6 0xe7 0xe8 0xe9>;
		reset-gpio = <0x5 0x8 0x1>;
		clock_in_out = "input";
		tx_delay = <0x30>;
		rx_delay = <0x20>;
	};

	rockchip-tsp@0xff420000 {
		compatible = "rockchip-tsp";
		reg = <0xff420000 0x10000>;
		i2s-id = <0x0>;
		clocks = <0x20 0x63>;
		clock-names = "i2s_clk", "i2s_mclk";
		interrupts = <0x0 0x55 0x4>;
		dmas = <0xa7 0x0 0xa7 0x1>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
		pinctrl-1 = <0xda>;
	};

	gpu {
		compatible = "arm,malit764", "arm,malit76x", "arm,malit7xx", "arm,mali-midgard";
		reg = <0xffa30000 0x10000>;
		interrupts = <0x0 0x6 0x4 0x0 0x7 0x4 0x0 0x8 0x4>;
		interrupt-names = "JOB", "MMU", "GPU";
	};

	iep_mmu {
		dbgname = "iep";
		compatible = "rockchip,iep_mmu";
		reg = <0xff900800 0x100>;
		interrupts = <0x0 0x11 0x4>;
		interrupt-names = "iep_mmu";
	};

	vip_mmu {
		dbgname = "vip";
		compatible = "rockchip,vip_mmu";
		reg = <0xff950800 0x100>;
		interrupts = <0x0 0xd 0x4>;
		interrupt-names = "vip_mmu";
	};

	vopb_mmu {
		dbgname = "vopb";
		compatible = "rockchip,vopb_mmu";
		reg = <0xff930300 0x100>;
		interrupts = <0x0 0xf 0x4>;
		interrupt-names = "vopb_mmu";
	};

	vopl_mmu {
		dbgname = "vopl";
		compatible = "rockchip,vopl_mmu";
		reg = <0xff940300 0x100>;
		interrupts = <0x0 0x10 0x4>;
		interrupt-names = "vopl_mmu";
	};

	hevc_mmu {
		dbgname = "hevc";
		compatible = "rockchip,hevc_mmu";
		reg = <0xff9c0440 0x40 0xff9c0480 0x40>;
		interrupts = <0x0 0x6f 0x4>;
		interrupt-names = "hevc_mmu";
	};

	vpu_mmu {
		dbgname = "vpu";
		compatible = "rockchip,vpu_mmu";
		reg = <0xff9a0800 0x100>;
		interrupts = <0x0 0xb 0x4>;
		interrupt-names = "vpu_mmu";
	};

	isp_mmu {
		dbgname = "isp_mmu";
		compatible = "rockchip,isp_mmu";
		reg = <0xff914000 0x100 0xff915000 0x100>;
		interrupts = <0x0 0xe 0x4>;
		interrupt-names = "isp_mmu";
	};

	rockchip_suspend {
		rockchip,ctrbits = <0x40017>;
		rockchip,pmic-gpios = <0x4000a00 0x1000a10>;
		rockchip,pmic-suspend_gpios = <0x1007c30 0x1007c40>;
		rockchip,pmic-resume_gpios = <0x2007c32 0x2007c42>;
	};

	isp@ff910000 {
		compatible = "rockchip,isp";
		reg = <0xff910000 0x10000>;
		interrupts = <0x0 0xe 0x4>;
		clocks = <0xb 0x2 0xb 0x1 0x24 0x26 0xea 0x41 0x79 0xf 0x42 0xeb 0xb 0x6>;
		clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
		pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl";
		pinctrl-0 = <0xec>;
		pinctrl-1 = <0xec 0xed>;
		pinctrl-2 = <0xec 0xed 0xee>;
		pinctrl-3 = <0xec 0xed 0xee 0xef>;
		pinctrl-4 = <0xec 0xf0>;
		pinctrl-5 = <0xec 0xf1>;
		pinctrl-6 = <0xec 0xf1 0xf2>;
		rockchip,isp,mipiphy = <0x2>;
		rockchip,isp,cifphy = <0x1>;
		rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
		rockchip,gpios = <0x4 0xd 0x0>;
		rockchip,isp,iommu_enable = <0x1>;
		status = "okay";
	};

	tsadc@ff280000 {
		compatible = "rockchip,tsadc";
		reg = <0xff280000 0x100>;
		interrupts = <0x0 0x25 0x4>;
		#io-channel-cells = <0x1>;
		io-channel-ranges;
		clock-frequency = <0xc350>;
		clocks = <0x60 0x7a 0x2>;
		clock-names = "tsadc", "pclk_tsadc";
		status = "okay";
	};

	lcdc-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0xf3>;
		pinctrl-1 = <0xf4>;
		pinctrl-2 = <0xf5>;
		regulator-name = "vcc30_lcd";
	};

	dpio-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0xf6>;
		pinctrl-1 = <0xf7>;
		pinctrl-2 = <0xf8>;
		regulator-name = "vcc18_cif";
	};

	flash0-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0xf9>;
		pinctrl-1 = <0xfa>;
		pinctrl-2 = <0xfb>;
		regulator-name = "vcc_flash";
	};

	flash1-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0xfc>;
		pinctrl-1 = <0xfd>;
		pinctrl-2 = <0xfe>;
		regulator-name = "vcc_flash";
	};

	apio3-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0xff>;
		pinctrl-1 = <0x100>;
		pinctrl-2 = <0x101>;
		regulator-name = "vccio_wl";
	};

	apio5-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0x102>;
		pinctrl-1 = <0x103>;
		pinctrl-2 = <0x104>;
		regulator-name = "vccio";
	};

	apio4-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0x105>;
		pinctrl-1 = <0x106>;
		pinctrl-2 = <0x107>;
		regulator-name = "vccio";
	};

	apio0-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0x108>;
		pinctrl-1 = <0x109>;
		pinctrl-2 = <0x10a>;
		regulator-name = "vccio";
	};

	apio2-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0x10b>;
		pinctrl-1 = <0x10c>;
		pinctrl-2 = <0x10d>;
		regulator-name = "vccio";
	};

	sdmmc0-vdd-domain {
		compatible = "rockchip,io_vol_domain";
		pinctrl-names = "default", "1.8V", "3.3V";
		pinctrl-0 = <0x10e>;
		pinctrl-1 = <0x10f>;
		pinctrl-2 = <0x110>;
		regulator-name = "vcc_sd";
	};

	power_ctr {
	};

	display-timings {
		native-mode = <0x111>;
		linux,phandle = <0xc9>;
		phandle = <0xc9>;

		timing0 {
			screen-type = <0x1>;
			out-face = <0x0>;
			clock-frequency = <0x46cf710>;
			hactive = <0x500>;
			vactive = <0x2d0>;
			hback-porch = <0xdc>;
			hfront-porch = <0x6e>;
			vback-porch = <0x14>;
			vfront-porch = <0x5>;
			hsync-len = <0x28>;
			vsync-len = <0x5>;
			hsync-active = <0x1>;
			vsync-active = <0x1>;
			de-active = <0x0>;
			pixelclk-active = <0x0>;
			swap-rb = <0x0>;
			swap-rg = <0x0>;
			swap-gb = <0x0>;
		};

		timing1 {
			screen-type = <0x1>;
			out-face = <0x0>;
			clock-frequency = <0x8d9ee20>;
			hactive = <0x780>;
			vactive = <0x438>;
			hback-porch = <0x94>;
			hfront-porch = <0x58>;
			vback-porch = <0x24>;
			vfront-porch = <0x4>;
			hsync-len = <0x2c>;
			vsync-len = <0x5>;
			hsync-active = <0x1>;
			vsync-active = <0x1>;
			de-active = <0x0>;
			pixelclk-active = <0x0>;
			swap-rb = <0x0>;
			swap-rg = <0x0>;
			swap-gb = <0x0>;
			linux,phandle = <0x111>;
			phandle = <0x111>;
		};

		timing2 {
			screen-type = <0x1>;
			out-face = <0x0>;
			clock-frequency = <0x11b3dc40>;
			hactive = <0xf00>;
			vactive = <0x870>;
			hback-porch = <0x128>;
			hfront-porch = <0xb0>;
			vback-porch = <0x48>;
			vfront-porch = <0x8>;
			hsync-len = <0x58>;
			vsync-len = <0xa>;
			hsync-active = <0x1>;
			vsync-active = <0x1>;
			de-active = <0x0>;
			pixelclk-active = <0x0>;
			swap-rb = <0x0>;
			swap-rg = <0x0>;
			swap-gb = <0x0>;
		};
	};

	wireless-wlan {
		compatible = "wlan-platdata";
		wifi_chip_type = "bcmwifi";
		sdio_vref = <0x708>;
		power_pmu_regulator = "act_ldo3";
		power_pmu_enable_level = <0x1>;
		vref_pmu_regulator = "act_ldo3";
		vref_pmu_enable_level = <0x1>;
		WIFI,poweren_gpio = <0x5 0x1c 0x0>;
		WIFI,host_wake_irq = <0x5 0x1e 0x0>;
		status = "okay";
	};

	wireless-bluetooth {
		compatible = "bluetooth-platdata";
		uart_rts_gpios = <0x5 0x13 0x1>;
		pinctrl-names = "default", "rts_gpio";
		pinctrl-0 = <0x112>;
		pinctrl-1 = <0x113>;
		BT,power_gpio = <0x5 0x1b 0x0>;
		BT,reset_gpio = <0x5 0x1d 0x0>;
		BT,wake_gpio = <0x5 0x1a 0x0>;
		BT,wake_host_irq = <0x5 0x1f 0x0>;
		status = "okay";
	};

	pwm_regulator {
		compatible = "rockchip_pwm_regulator";
		pwms = <0x114 0x0 0x7d0>;
		rockchip,pwm_id = <0x1>;
		rockchip,pwm_voltage_map = <0xe1d48 0xe7ef0 0xee098 0xf4240 0xfa3e8 0x100590 0x106738 0x10c8e0 0x112a88 0x118c30 0x11edd8 0x124f80 0x12b128 0x1312d0 0x137478 0x13d620 0x1437c8 0x149970 0x14fb18 0x155cc0>;
		rockchip,pwm_voltage = <0x10c8e0>;
		rockchip,pwm_min_voltage = <0xe1d48>;
		rockchip,pwm_max_voltage = <0x155cc0>;
		rockchip,pwm_suspend_voltage = <0xe7ef0>;
		rockchip,pwm_coefficient = <0x1db>;

		regulators {
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			regulator@0 {
				regulator-compatible = "pwm_dcdc1";
				regulator-name = "vdd_logic";
				regulator-min-microvolt = <0xe1d48>;
				regulator-max-microvolt = <0x155cc0>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	codec-hdmi-i2s {
		compatible = "hdmi-i2s";
		linux,phandle = <0x115>;
		phandle = <0x115>;
	};

	codec-hdmi-spdif {
		compatible = "hdmi-spdif";
		linux,phandle = <0x117>;
		phandle = <0x117>;
	};

	rockchip-hdmi-i2s {
		compatible = "rockchip-hdmi-i2s";

		dais {

			dai0 {
				audio-codec = <0x115>;
				i2s-controller = <0x116>;
				format = "i2s";
			};
		};
	};

	rockchip-hdmi-spdif {
		compatible = "rockchip-hdmi-spdif";

		dais {

			dai0 {
				audio-codec = <0x117>;
				i2s-controller = <0x118>;
			};
		};
	};

	rockchip-rk1000 {
		compatible = "rockchip-rk1000";

		dais {

			dai0 {
				audio-codec = <0x119>;
				i2s-controller = <0x116>;
				format = "i2s";
			};
		};
	};

	rkxx-remotectl {
		compatible = "rockchip,remotectl";
		module-gpios = <0x4 0x0 0x1>;
		status = "okay";
	};

	usb_control {
		compatible = "rockchip,rk3288-usb-control";
		host_drv_gpio = <0x95 0xe 0x1>;
		otg_drv_gpio = <0x95 0xc 0x1>;
		rockchip,remote_wakeup;
		rockchip,usb_irq_wakeup;
	};

	leds@fff16100 {
		reg = <0xfff16100 0x10>;
		compatible = "gpio-leds";

		power {
			label = "blue:power";
			linux,default-trigger = "ir-click";
			default-state = "on";
			gpios = <0x3 0x3 0x1>;
		};
	};

	ug_fan@fff16000 {
		reg = <0xfff16000 0x10>;
		compatible = "ug_fan";
		fan-gpio = <0x3 0x9 0x0>;
		fan-mode = <0x2>;
		fan-on-temp = <0x46>;
		fan-off-temp = <0x41>;
	};
};