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  1. /dts-v1/;
  2.  
  3. /memreserve/ 0x0000000000000000 0x0000000000001000;
  4. / {
  5. #address-cells = <0x1>;
  6. #size-cells = <0x1>;
  7. model = "Terasic DE-0(Atlas)";
  8. compatible = "altr,socfpga-cyclone5", "altr,socfpga";
  9.  
  10. chosen {
  11. bootargs = "earlyprintk";
  12. stdout-path = "serial0:115200n8";
  13. };
  14.  
  15. aliases {
  16. ethernet0 = "/soc/ethernet@ff702000";
  17. ethernet1 = "/soc/ethernet@ff702000";
  18. serial0 = "/soc/serial0@ffc02000";
  19. serial1 = "/soc/serial1@ffc03000";
  20. timer0 = "/soc/timer0@ffc08000";
  21. timer1 = "/soc/timer1@ffc09000";
  22. timer2 = "/soc/timer2@ffd00000";
  23. timer3 = "/soc/timer3@ffd01000";
  24. };
  25.  
  26. memory {
  27. device_type = "memory";
  28. reg = <0x0 0x40000000>;
  29. };
  30.  
  31. cpus {
  32. #address-cells = <0x1>;
  33. #size-cells = <0x0>;
  34. enable-method = "altr,socfpga-smp";
  35.  
  36. cpu@0 {
  37. compatible = "arm,cortex-a9";
  38. device_type = "cpu";
  39. reg = <0x0>;
  40. next-level-cache = <0x1>;
  41. };
  42.  
  43. cpu@1 {
  44. compatible = "arm,cortex-a9";
  45. device_type = "cpu";
  46. reg = <0x1>;
  47. next-level-cache = <0x1>;
  48. };
  49. };
  50.  
  51. intc@fffed000 {
  52. compatible = "arm,cortex-a9-gic";
  53. #interrupt-cells = <0x3>;
  54. interrupt-controller;
  55. reg = <0xfffed000 0x1000 0xfffec100 0x100>;
  56. linux,phandle = <0x2>;
  57. phandle = <0x2>;
  58. };
  59.  
  60. soc {
  61. #address-cells = <0x1>;
  62. #size-cells = <0x1>;
  63. compatible = "simple-bus";
  64. device_type = "soc";
  65. interrupt-parent = <0x2>;
  66. ranges;
  67.  
  68. amba {
  69. compatible = "simple-bus";
  70. #address-cells = <0x1>;
  71. #size-cells = <0x1>;
  72. ranges;
  73.  
  74. pdma@ffe01000 {
  75. compatible = "arm,pl330", "arm,primecell";
  76. reg = <0xffe01000 0x1000>;
  77. interrupts = <0x0 0x68 0x4 0x0 0x69 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4>;
  78. #dma-cells = <0x1>;
  79. #dma-channels = <0x8>;
  80. #dma-requests = <0x20>;
  81. clocks = <0x3>;
  82. clock-names = "apb_pclk";
  83. linux,phandle = <0x2b>;
  84. phandle = <0x2b>;
  85. };
  86. };
  87.  
  88. can@ffc00000 {
  89. compatible = "bosch,d_can";
  90. reg = <0xffc00000 0x1000>;
  91. interrupts = <0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4>;
  92. clocks = <0x4>;
  93. status = "disabled";
  94. };
  95.  
  96. can@ffc01000 {
  97. compatible = "bosch,d_can";
  98. reg = <0xffc01000 0x1000>;
  99. interrupts = <0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4>;
  100. clocks = <0x5>;
  101. status = "disabled";
  102. };
  103.  
  104. clkmgr@ffd04000 {
  105. compatible = "altr,clk-mgr";
  106. reg = <0xffd04000 0x1000>;
  107.  
  108. clocks {
  109. #address-cells = <0x1>;
  110. #size-cells = <0x0>;
  111.  
  112. osc1 {
  113. #clock-cells = <0x0>;
  114. compatible = "fixed-clock";
  115. clock-frequency = <0x17d7840>;
  116. linux,phandle = <0x6>;
  117. phandle = <0x6>;
  118. };
  119.  
  120. osc2 {
  121. #clock-cells = <0x0>;
  122. compatible = "fixed-clock";
  123. linux,phandle = <0x8>;
  124. phandle = <0x8>;
  125. };
  126.  
  127. f2s_periph_ref_clk {
  128. #clock-cells = <0x0>;
  129. compatible = "fixed-clock";
  130. linux,phandle = <0x9>;
  131. phandle = <0x9>;
  132. };
  133.  
  134. f2s_sdram_ref_clk {
  135. #clock-cells = <0x0>;
  136. compatible = "fixed-clock";
  137. linux,phandle = <0xb>;
  138. phandle = <0xb>;
  139. };
  140.  
  141. main_pll {
  142. #address-cells = <0x1>;
  143. #size-cells = <0x0>;
  144. #clock-cells = <0x0>;
  145. compatible = "altr,socfpga-pll-clock";
  146. clocks = <0x6>;
  147. reg = <0x40>;
  148. linux,phandle = <0x7>;
  149. phandle = <0x7>;
  150.  
  151. mpuclk {
  152. #clock-cells = <0x0>;
  153. compatible = "altr,socfpga-perip-clk";
  154. clocks = <0x7>;
  155. div-reg = <0xe0 0x0 0x9>;
  156. reg = <0x48>;
  157. linux,phandle = <0xd>;
  158. phandle = <0xd>;
  159. };
  160.  
  161. mainclk {
  162. #clock-cells = <0x0>;
  163. compatible = "altr,socfpga-perip-clk";
  164. clocks = <0x7>;
  165. div-reg = <0xe4 0x0 0x9>;
  166. reg = <0x4c>;
  167. linux,phandle = <0xe>;
  168. phandle = <0xe>;
  169. };
  170.  
  171. dbg_base_clk {
  172. #clock-cells = <0x0>;
  173. compatible = "altr,socfpga-perip-clk";
  174. clocks = <0x7 0x6>;
  175. div-reg = <0xe8 0x0 0x9>;
  176. reg = <0x50>;
  177. linux,phandle = <0x11>;
  178. phandle = <0x11>;
  179. };
  180.  
  181. main_qspi_clk {
  182. #clock-cells = <0x0>;
  183. compatible = "altr,socfpga-perip-clk";
  184. clocks = <0x7>;
  185. reg = <0x54>;
  186. linux,phandle = <0x1a>;
  187. phandle = <0x1a>;
  188. };
  189.  
  190. main_nand_sdmmc_clk {
  191. #clock-cells = <0x0>;
  192. compatible = "altr,socfpga-perip-clk";
  193. clocks = <0x7>;
  194. reg = <0x58>;
  195. linux,phandle = <0x17>;
  196. phandle = <0x17>;
  197. };
  198.  
  199. cfg_h2f_usr0_clk {
  200. #clock-cells = <0x0>;
  201. compatible = "altr,socfpga-perip-clk";
  202. clocks = <0x7>;
  203. reg = <0x5c>;
  204. linux,phandle = <0x13>;
  205. phandle = <0x13>;
  206. };
  207. };
  208.  
  209. periph_pll {
  210. #address-cells = <0x1>;
  211. #size-cells = <0x0>;
  212. #clock-cells = <0x0>;
  213. compatible = "altr,socfpga-pll-clock";
  214. clocks = <0x6 0x8 0x9>;
  215. reg = <0x80>;
  216. linux,phandle = <0xa>;
  217. phandle = <0xa>;
  218.  
  219. emac0_clk {
  220. #clock-cells = <0x0>;
  221. compatible = "altr,socfpga-perip-clk";
  222. clocks = <0xa>;
  223. reg = <0x88>;
  224. linux,phandle = <0x14>;
  225. phandle = <0x14>;
  226. };
  227.  
  228. emac1_clk {
  229. #clock-cells = <0x0>;
  230. compatible = "altr,socfpga-perip-clk";
  231. clocks = <0xa>;
  232. reg = <0x8c>;
  233. linux,phandle = <0x15>;
  234. phandle = <0x15>;
  235. };
  236.  
  237. per_qsi_clk {
  238. #clock-cells = <0x0>;
  239. compatible = "altr,socfpga-perip-clk";
  240. clocks = <0xa>;
  241. reg = <0x90>;
  242. linux,phandle = <0x1b>;
  243. phandle = <0x1b>;
  244. };
  245.  
  246. per_nand_mmc_clk {
  247. #clock-cells = <0x0>;
  248. compatible = "altr,socfpga-perip-clk";
  249. clocks = <0xa>;
  250. reg = <0x94>;
  251. linux,phandle = <0x18>;
  252. phandle = <0x18>;
  253. };
  254.  
  255. per_base_clk {
  256. #clock-cells = <0x0>;
  257. compatible = "altr,socfpga-perip-clk";
  258. clocks = <0xa>;
  259. reg = <0x98>;
  260. linux,phandle = <0x10>;
  261. phandle = <0x10>;
  262. };
  263.  
  264. h2f_usr1_clk {
  265. #clock-cells = <0x0>;
  266. compatible = "altr,socfpga-perip-clk";
  267. clocks = <0xa>;
  268. reg = <0x9c>;
  269. linux,phandle = <0x16>;
  270. phandle = <0x16>;
  271. };
  272. };
  273.  
  274. sdram_pll {
  275. #address-cells = <0x1>;
  276. #size-cells = <0x0>;
  277. #clock-cells = <0x0>;
  278. compatible = "altr,socfpga-pll-clock";
  279. clocks = <0x6 0x8 0xb>;
  280. reg = <0xc0>;
  281. linux,phandle = <0xc>;
  282. phandle = <0xc>;
  283.  
  284. ddr_dqs_clk {
  285. #clock-cells = <0x0>;
  286. compatible = "altr,socfpga-perip-clk";
  287. clocks = <0xc>;
  288. reg = <0xc8>;
  289. linux,phandle = <0x1c>;
  290. phandle = <0x1c>;
  291. };
  292.  
  293. ddr_2x_dqs_clk {
  294. #clock-cells = <0x0>;
  295. compatible = "altr,socfpga-perip-clk";
  296. clocks = <0xc>;
  297. reg = <0xcc>;
  298. linux,phandle = <0x1d>;
  299. phandle = <0x1d>;
  300. };
  301.  
  302. ddr_dq_clk {
  303. #clock-cells = <0x0>;
  304. compatible = "altr,socfpga-perip-clk";
  305. clocks = <0xc>;
  306. reg = <0xd0>;
  307. linux,phandle = <0x1e>;
  308. phandle = <0x1e>;
  309. };
  310.  
  311. h2f_usr2_clk {
  312. #clock-cells = <0x0>;
  313. compatible = "altr,socfpga-perip-clk";
  314. clocks = <0xc>;
  315. reg = <0xd4>;
  316. linux,phandle = <0x1f>;
  317. phandle = <0x1f>;
  318. };
  319. };
  320.  
  321. mpu_periph_clk {
  322. #clock-cells = <0x0>;
  323. compatible = "altr,socfpga-perip-clk";
  324. clocks = <0xd>;
  325. fixed-divider = <0x4>;
  326. linux,phandle = <0x2a>;
  327. phandle = <0x2a>;
  328. };
  329.  
  330. mpu_l2_ram_clk {
  331. #clock-cells = <0x0>;
  332. compatible = "altr,socfpga-perip-clk";
  333. clocks = <0xd>;
  334. fixed-divider = <0x2>;
  335. };
  336.  
  337. l4_main_clk {
  338. #clock-cells = <0x0>;
  339. compatible = "altr,socfpga-gate-clk";
  340. clocks = <0xe>;
  341. clk-gate = <0x60 0x0>;
  342. linux,phandle = <0x3>;
  343. phandle = <0x3>;
  344. };
  345.  
  346. l3_main_clk {
  347. #clock-cells = <0x0>;
  348. compatible = "altr,socfpga-perip-clk";
  349. clocks = <0xe>;
  350. fixed-divider = <0x1>;
  351. };
  352.  
  353. l3_mp_clk {
  354. #clock-cells = <0x0>;
  355. compatible = "altr,socfpga-gate-clk";
  356. clocks = <0xe>;
  357. div-reg = <0x64 0x0 0x2>;
  358. clk-gate = <0x60 0x1>;
  359. linux,phandle = <0xf>;
  360. phandle = <0xf>;
  361. };
  362.  
  363. l3_sp_clk {
  364. #clock-cells = <0x0>;
  365. compatible = "altr,socfpga-gate-clk";
  366. clocks = <0xf>;
  367. div-reg = <0x64 0x2 0x2>;
  368. };
  369.  
  370. l4_mp_clk {
  371. #clock-cells = <0x0>;
  372. compatible = "altr,socfpga-gate-clk";
  373. clocks = <0xe 0x10>;
  374. div-reg = <0x64 0x4 0x3>;
  375. clk-gate = <0x60 0x2>;
  376. linux,phandle = <0x22>;
  377. phandle = <0x22>;
  378. };
  379.  
  380. l4_sp_clk {
  381. #clock-cells = <0x0>;
  382. compatible = "altr,socfpga-gate-clk";
  383. clocks = <0xe 0x10>;
  384. div-reg = <0x64 0x7 0x3>;
  385. clk-gate = <0x60 0x3>;
  386. linux,phandle = <0x23>;
  387. phandle = <0x23>;
  388. };
  389.  
  390. dbg_at_clk {
  391. #clock-cells = <0x0>;
  392. compatible = "altr,socfpga-gate-clk";
  393. clocks = <0x11>;
  394. div-reg = <0x68 0x0 0x2>;
  395. clk-gate = <0x60 0x4>;
  396. linux,phandle = <0x12>;
  397. phandle = <0x12>;
  398. };
  399.  
  400. dbg_clk {
  401. #clock-cells = <0x0>;
  402. compatible = "altr,socfpga-gate-clk";
  403. clocks = <0x12>;
  404. div-reg = <0x68 0x2 0x2>;
  405. clk-gate = <0x60 0x5>;
  406. };
  407.  
  408. dbg_trace_clk {
  409. #clock-cells = <0x0>;
  410. compatible = "altr,socfpga-gate-clk";
  411. clocks = <0x11>;
  412. div-reg = <0x6c 0x0 0x3>;
  413. clk-gate = <0x60 0x6>;
  414. };
  415.  
  416. dbg_timer_clk {
  417. #clock-cells = <0x0>;
  418. compatible = "altr,socfpga-gate-clk";
  419. clocks = <0x11>;
  420. clk-gate = <0x60 0x7>;
  421. };
  422.  
  423. cfg_clk {
  424. #clock-cells = <0x0>;
  425. compatible = "altr,socfpga-gate-clk";
  426. clocks = <0x13>;
  427. clk-gate = <0x60 0x8>;
  428. };
  429.  
  430. h2f_user0_clk {
  431. #clock-cells = <0x0>;
  432. compatible = "altr,socfpga-gate-clk";
  433. clocks = <0x13>;
  434. clk-gate = <0x60 0x9>;
  435. };
  436.  
  437. emac_0_clk {
  438. #clock-cells = <0x0>;
  439. compatible = "altr,socfpga-gate-clk";
  440. clocks = <0x14>;
  441. clk-gate = <0xa0 0x0>;
  442. };
  443.  
  444. emac_1_clk {
  445. #clock-cells = <0x0>;
  446. compatible = "altr,socfpga-gate-clk";
  447. clocks = <0x15>;
  448. clk-gate = <0xa0 0x1>;
  449. };
  450.  
  451. usb_mp_clk {
  452. #clock-cells = <0x0>;
  453. compatible = "altr,socfpga-gate-clk";
  454. clocks = <0x10>;
  455. clk-gate = <0xa0 0x2>;
  456. div-reg = <0xa4 0x0 0x3>;
  457. linux,phandle = <0x2c>;
  458. phandle = <0x2c>;
  459. };
  460.  
  461. spi_m_clk {
  462. #clock-cells = <0x0>;
  463. compatible = "altr,socfpga-gate-clk";
  464. clocks = <0x10>;
  465. clk-gate = <0xa0 0x3>;
  466. div-reg = <0xa4 0x3 0x3>;
  467. linux,phandle = <0x29>;
  468. phandle = <0x29>;
  469. };
  470.  
  471. can0_clk {
  472. #clock-cells = <0x0>;
  473. compatible = "altr,socfpga-gate-clk";
  474. clocks = <0x10>;
  475. clk-gate = <0xa0 0x4>;
  476. div-reg = <0xa4 0x6 0x3>;
  477. linux,phandle = <0x4>;
  478. phandle = <0x4>;
  479. };
  480.  
  481. can1_clk {
  482. #clock-cells = <0x0>;
  483. compatible = "altr,socfpga-gate-clk";
  484. clocks = <0x10>;
  485. clk-gate = <0xa0 0x5>;
  486. div-reg = <0xa4 0x9 0x3>;
  487. linux,phandle = <0x5>;
  488. phandle = <0x5>;
  489. };
  490.  
  491. gpio_db_clk {
  492. #clock-cells = <0x0>;
  493. compatible = "altr,socfpga-gate-clk";
  494. clocks = <0x10>;
  495. clk-gate = <0xa0 0x6>;
  496. div-reg = <0xa8 0x0 0x18>;
  497. };
  498.  
  499. h2f_user1_clk {
  500. #clock-cells = <0x0>;
  501. compatible = "altr,socfpga-gate-clk";
  502. clocks = <0x16>;
  503. clk-gate = <0xa0 0x7>;
  504. };
  505.  
  506. sdmmc_clk {
  507. #clock-cells = <0x0>;
  508. compatible = "altr,socfpga-gate-clk";
  509. clocks = <0x9 0x17 0x18>;
  510. clk-gate = <0xa0 0x8>;
  511. clk-phase = <0x0 0x87>;
  512. linux,phandle = <0x19>;
  513. phandle = <0x19>;
  514. };
  515.  
  516. sdmmc_clk_divided {
  517. #clock-cells = <0x0>;
  518. compatible = "altr,socfpga-gate-clk";
  519. clocks = <0x19>;
  520. clk-gate = <0xa0 0x8>;
  521. fixed-divider = <0x4>;
  522. linux,phandle = <0x26>;
  523. phandle = <0x26>;
  524. };
  525.  
  526. nand_x_clk {
  527. #clock-cells = <0x0>;
  528. compatible = "altr,socfpga-gate-clk";
  529. clocks = <0x9 0x17 0x18>;
  530. clk-gate = <0xa0 0x9>;
  531. };
  532.  
  533. nand_clk {
  534. #clock-cells = <0x0>;
  535. compatible = "altr,socfpga-gate-clk";
  536. clocks = <0x9 0x17 0x18>;
  537. clk-gate = <0xa0 0xa>;
  538. fixed-divider = <0x4>;
  539. };
  540.  
  541. qspi_clk {
  542. #clock-cells = <0x0>;
  543. compatible = "altr,socfpga-gate-clk";
  544. clocks = <0x9 0x1a 0x1b>;
  545. clk-gate = <0xa0 0xb>;
  546. };
  547.  
  548. ddr_dqs_clk_gate {
  549. #clock-cells = <0x0>;
  550. compatible = "altr,socfpga-gate-clk";
  551. clocks = <0x1c>;
  552. clk-gate = <0xd8 0x0>;
  553. };
  554.  
  555. ddr_2x_dqs_clk_gate {
  556. #clock-cells = <0x0>;
  557. compatible = "altr,socfpga-gate-clk";
  558. clocks = <0x1d>;
  559. clk-gate = <0xd8 0x1>;
  560. };
  561.  
  562. ddr_dq_clk_gate {
  563. #clock-cells = <0x0>;
  564. compatible = "altr,socfpga-gate-clk";
  565. clocks = <0x1e>;
  566. clk-gate = <0xd8 0x2>;
  567. };
  568.  
  569. h2f_user2_clk {
  570. #clock-cells = <0x0>;
  571. compatible = "altr,socfpga-gate-clk";
  572. clocks = <0x1f>;
  573. clk-gate = <0xd8 0x3>;
  574. };
  575. };
  576. };
  577.  
  578. fpgamgr@ff706000 {
  579. compatible = "altr,socfpga-fpga-mgr";
  580. reg = <0xff706000 0x1000 0xffb90000 0x1000>;
  581. interrupts = <0x0 0xaf 0x4>;
  582. };
  583.  
  584. ethernet@ff700000 {
  585. compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
  586. altr,sysmgr-syscon = <0x20 0x60 0x0>;
  587. reg = <0xff700000 0x2000>;
  588. interrupts = <0x0 0x73 0x4>;
  589. interrupt-names = "macirq";
  590. mac-address = [00 00 00 00 00 00];
  591. clocks = <0x14>;
  592. clock-names = "stmmaceth";
  593. resets = <0x21 0x20>;
  594. reset-names = "stmmaceth";
  595. snps,multicast-filter-bins = <0x100>;
  596. snps,perfect-filter-entries = <0x80>;
  597. tx-fifo-depth = <0x1000>;
  598. rx-fifo-depth = <0x1000>;
  599. status = "disabled";
  600. };
  601.  
  602. ethernet@ff702000 {
  603. compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
  604. altr,sysmgr-syscon = <0x20 0x60 0x2>;
  605. reg = <0xff702000 0x2000>;
  606. interrupts = <0x0 0x78 0x4>;
  607. interrupt-names = "macirq";
  608. mac-address = [00 00 00 00 00 00];
  609. clocks = <0x15>;
  610. clock-names = "stmmaceth";
  611. resets = <0x21 0x21>;
  612. reset-names = "stmmaceth";
  613. snps,multicast-filter-bins = <0x100>;
  614. snps,perfect-filter-entries = <0x80>;
  615. tx-fifo-depth = <0x1000>;
  616. rx-fifo-depth = <0x1000>;
  617. status = "okay";
  618. phy-mode = "rgmii";
  619. txd0-skew-ps = <0x0>;
  620. txd1-skew-ps = <0x0>;
  621. txd2-skew-ps = <0x0>;
  622. txd3-skew-ps = <0x0>;
  623. rxd0-skew-ps = <0x1a4>;
  624. rxd1-skew-ps = <0x1a4>;
  625. rxd2-skew-ps = <0x1a4>;
  626. rxd3-skew-ps = <0x1a4>;
  627. txen-skew-ps = <0x0>;
  628. txc-skew-ps = <0x744>;
  629. rxdv-skew-ps = <0x1a4>;
  630. rxc-skew-ps = <0x690>;
  631. max-frame-size = <0xed8>;
  632. };
  633.  
  634. gpio@ff708000 {
  635. #address-cells = <0x1>;
  636. #size-cells = <0x0>;
  637. compatible = "snps,dw-apb-gpio";
  638. reg = <0xff708000 0x1000>;
  639. clocks = <0x22>;
  640. status = "okay";
  641.  
  642. gpio-controller@0 {
  643. compatible = "snps,dw-apb-gpio-port";
  644. gpio-controller;
  645. #gpio-cells = <0x2>;
  646. snps,nr-gpios = <0x1d>;
  647. reg = <0x0>;
  648. interrupt-controller;
  649. #interrupt-cells = <0x2>;
  650. interrupts = <0x0 0xa4 0x4>;
  651. };
  652. };
  653.  
  654. gpio@ff709000 {
  655. #address-cells = <0x1>;
  656. #size-cells = <0x0>;
  657. compatible = "snps,dw-apb-gpio";
  658. reg = <0xff709000 0x1000>;
  659. clocks = <0x22>;
  660. status = "okay";
  661.  
  662. gpio-controller@0 {
  663. compatible = "snps,dw-apb-gpio-port";
  664. gpio-controller;
  665. #gpio-cells = <0x2>;
  666. snps,nr-gpios = <0x1d>;
  667. reg = <0x0>;
  668. interrupt-controller;
  669. #interrupt-cells = <0x2>;
  670. interrupts = <0x0 0xa5 0x4>;
  671. linux,phandle = <0x2e>;
  672. phandle = <0x2e>;
  673. };
  674. };
  675.  
  676. gpio@ff70a000 {
  677. #address-cells = <0x1>;
  678. #size-cells = <0x0>;
  679. compatible = "snps,dw-apb-gpio";
  680. reg = <0xff70a000 0x1000>;
  681. clocks = <0x22>;
  682. status = "okay";
  683.  
  684. gpio-controller@0 {
  685. compatible = "snps,dw-apb-gpio-port";
  686. gpio-controller;
  687. #gpio-cells = <0x2>;
  688. snps,nr-gpios = <0x1b>;
  689. reg = <0x0>;
  690. interrupt-controller;
  691. #interrupt-cells = <0x2>;
  692. interrupts = <0x0 0xa6 0x4>;
  693. linux,phandle = <0x24>;
  694. phandle = <0x24>;
  695. };
  696. };
  697.  
  698. i2c@ffc04000 {
  699. #address-cells = <0x1>;
  700. #size-cells = <0x0>;
  701. compatible = "snps,designware-i2c";
  702. reg = <0xffc04000 0x1000>;
  703. clocks = <0x23>;
  704. interrupts = <0x0 0x9e 0x4>;
  705. status = "okay";
  706. speed-mode = <0x0>;
  707.  
  708. adxl345@0 {
  709. compatible = "adi,adxl345";
  710. reg = <0x53>;
  711. interrupt-parent = <0x24>;
  712. interrupts = <0x3 0x2>;
  713. };
  714. };
  715.  
  716. i2c@ffc05000 {
  717. #address-cells = <0x1>;
  718. #size-cells = <0x0>;
  719. compatible = "snps,designware-i2c";
  720. reg = <0xffc05000 0x1000>;
  721. clocks = <0x23>;
  722. interrupts = <0x0 0x9f 0x4>;
  723. status = "okay";
  724. speed-mode = <0x0>;
  725. };
  726.  
  727. i2c@ffc06000 {
  728. #address-cells = <0x1>;
  729. #size-cells = <0x0>;
  730. compatible = "snps,designware-i2c";
  731. reg = <0xffc06000 0x1000>;
  732. clocks = <0x23>;
  733. interrupts = <0x0 0xa0 0x4>;
  734. status = "disabled";
  735. };
  736.  
  737. i2c@ffc07000 {
  738. #address-cells = <0x1>;
  739. #size-cells = <0x0>;
  740. compatible = "snps,designware-i2c";
  741. reg = <0xffc07000 0x1000>;
  742. clocks = <0x23>;
  743. interrupts = <0x0 0xa1 0x4>;
  744. status = "disabled";
  745. };
  746.  
  747. eccmgr@ffd08140 {
  748. compatible = "altr,socfpga-ecc-manager";
  749. #address-cells = <0x1>;
  750. #size-cells = <0x1>;
  751. ranges;
  752.  
  753. l2-ecc@ffd08140 {
  754. compatible = "altr,socfpga-l2-ecc";
  755. reg = <0xffd08140 0x4>;
  756. interrupts = <0x0 0x24 0x1 0x0 0x25 0x1>;
  757. };
  758.  
  759. ocram-ecc@ffd08144 {
  760. compatible = "altr,socfpga-ocram-ecc";
  761. reg = <0xffd08144 0x4>;
  762. iram = <0x25>;
  763. interrupts = <0x0 0xb2 0x1 0x0 0xb3 0x1>;
  764. };
  765. };
  766.  
  767. l2-cache@fffef000 {
  768. compatible = "arm,pl310-cache";
  769. reg = <0xfffef000 0x1000>;
  770. interrupts = <0x0 0x26 0x4>;
  771. cache-unified;
  772. cache-level = <0x2>;
  773. arm,tag-latency = <0x1 0x1 0x1>;
  774. arm,data-latency = <0x2 0x1 0x1>;
  775. prefetch-data = <0x1>;
  776. prefetch-instr = <0x1>;
  777. linux,phandle = <0x1>;
  778. phandle = <0x1>;
  779. };
  780.  
  781. dwmmc0@ff704000 {
  782. compatible = "altr,socfpga-dw-mshc";
  783. reg = <0xff704000 0x1000>;
  784. interrupts = <0x0 0x8b 0x4>;
  785. fifo-depth = <0x400>;
  786. #address-cells = <0x1>;
  787. #size-cells = <0x0>;
  788. clocks = <0x22 0x26>;
  789. clock-names = "biu", "ciu";
  790. status = "okay";
  791. num-slots = <0x1>;
  792. broken-cd;
  793. bus-width = <0x4>;
  794. cap-mmc-highspeed;
  795. cap-sd-highspeed;
  796. vmmc-supply = <0x27>;
  797. vqmmc-supply = <0x27>;
  798. };
  799.  
  800. sram@ffff0000 {
  801. compatible = "mmio-sram";
  802. reg = <0xffff0000 0x10000>;
  803. linux,phandle = <0x25>;
  804. phandle = <0x25>;
  805. };
  806.  
  807. rstmgr@ffd05000 {
  808. #reset-cells = <0x1>;
  809. compatible = "altr,rst-mgr";
  810. reg = <0xffd05000 0x1000>;
  811. altr,modrst-offset = <0x10>;
  812. linux,phandle = <0x21>;
  813. phandle = <0x21>;
  814. };
  815.  
  816. snoop-control-unit@fffec000 {
  817. compatible = "arm,cortex-a9-scu";
  818. reg = <0xfffec000 0x100>;
  819. };
  820.  
  821. sdr@ffc25000 {
  822. compatible = "syscon";
  823. reg = <0xffc25000 0x1000>;
  824. linux,phandle = <0x28>;
  825. phandle = <0x28>;
  826. };
  827.  
  828. sdramedac {
  829. compatible = "altr,sdram-edac";
  830. altr,sdr-syscon = <0x28>;
  831. interrupts = <0x0 0x27 0x4>;
  832. };
  833.  
  834. spi@fff00000 {
  835. compatible = "snps,dw-apb-ssi";
  836. #address-cells = <0x1>;
  837. #size-cells = <0x0>;
  838. reg = <0xfff00000 0x1000>;
  839. interrupts = <0x0 0x9a 0x4>;
  840. num-cs = <0x4>;
  841. clocks = <0x29>;
  842. status = "disabled";
  843. };
  844.  
  845. spi@fff01000 {
  846. compatible = "snps,dw-apb-ssi";
  847. #address-cells = <0x1>;
  848. #size-cells = <0x0>;
  849. reg = <0xfff01000 0x1000>;
  850. interrupts = <0x0 0x9b 0x4>;
  851. num-cs = <0x4>;
  852. clocks = <0x29>;
  853. status = "disabled";
  854. };
  855.  
  856. sysmgr@ffd08000 {
  857. compatible = "altr,sys-mgr", "syscon";
  858. reg = <0xffd08000 0x4000>;
  859. cpu1-start-addr = <0xffd080c4>;
  860. linux,phandle = <0x20>;
  861. phandle = <0x20>;
  862. };
  863.  
  864. timer@fffec600 {
  865. compatible = "arm,cortex-a9-twd-timer";
  866. reg = <0xfffec600 0x100>;
  867. interrupts = <0x1 0xd 0xf01>;
  868. clocks = <0x2a>;
  869. };
  870.  
  871. timer0@ffc08000 {
  872. compatible = "snps,dw-apb-timer";
  873. interrupts = <0x0 0xa7 0x4>;
  874. reg = <0xffc08000 0x1000>;
  875. clocks = <0x23>;
  876. clock-names = "timer";
  877. };
  878.  
  879. timer1@ffc09000 {
  880. compatible = "snps,dw-apb-timer";
  881. interrupts = <0x0 0xa8 0x4>;
  882. reg = <0xffc09000 0x1000>;
  883. clocks = <0x23>;
  884. clock-names = "timer";
  885. };
  886.  
  887. timer2@ffd00000 {
  888. compatible = "snps,dw-apb-timer";
  889. interrupts = <0x0 0xa9 0x4>;
  890. reg = <0xffd00000 0x1000>;
  891. clocks = <0x6>;
  892. clock-names = "timer";
  893. };
  894.  
  895. timer3@ffd01000 {
  896. compatible = "snps,dw-apb-timer";
  897. interrupts = <0x0 0xaa 0x4>;
  898. reg = <0xffd01000 0x1000>;
  899. clocks = <0x6>;
  900. clock-names = "timer";
  901. };
  902.  
  903. serial0@ffc02000 {
  904. compatible = "snps,dw-apb-uart";
  905. reg = <0xffc02000 0x1000>;
  906. interrupts = <0x0 0xa2 0x4>;
  907. reg-shift = <0x2>;
  908. reg-io-width = <0x4>;
  909. clocks = <0x23>;
  910. dmas = <0x2b 0x1c 0x2b 0x1d>;
  911. dma-names = "tx", "rx";
  912. status = "okay";
  913. };
  914.  
  915. serial1@ffc03000 {
  916. compatible = "snps,dw-apb-uart";
  917. reg = <0xffc03000 0x1000>;
  918. interrupts = <0x0 0xa3 0x4>;
  919. reg-shift = <0x2>;
  920. reg-io-width = <0x4>;
  921. clocks = <0x23>;
  922. dmas = <0x2b 0x1e 0x2b 0x1f>;
  923. dma-names = "tx", "rx";
  924. };
  925.  
  926. usbphy@0 {
  927. #phy-cells = <0x0>;
  928. compatible = "usb-nop-xceiv";
  929. status = "okay";
  930. linux,phandle = <0x2d>;
  931. phandle = <0x2d>;
  932. };
  933.  
  934. usb@ffb00000 {
  935. compatible = "snps,dwc2";
  936. reg = <0xffb00000 0xffff>;
  937. interrupts = <0x0 0x7d 0x4>;
  938. clocks = <0x2c>;
  939. clock-names = "otg";
  940. resets = <0x21 0x22>;
  941. reset-names = "dwc2";
  942. phys = <0x2d>;
  943. phy-names = "usb2-phy";
  944. status = "okay";
  945. };
  946.  
  947. usb@ffb40000 {
  948. compatible = "snps,dwc2";
  949. reg = <0xffb40000 0xffff>;
  950. interrupts = <0x0 0x80 0x4>;
  951. clocks = <0x2c>;
  952. clock-names = "otg";
  953. resets = <0x21 0x23>;
  954. reset-names = "dwc2";
  955. status = "okay";
  956. dr_mode = "host";
  957. };
  958.  
  959. watchdog@ffd02000 {
  960. compatible = "snps,dw-wdt";
  961. reg = <0xffd02000 0x1000>;
  962. interrupts = <0x0 0xab 0x4>;
  963. clocks = <0x6>;
  964. status = "okay";
  965. };
  966.  
  967. watchdog@ffd03000 {
  968. compatible = "snps,dw-wdt";
  969. reg = <0xffd03000 0x1000>;
  970. interrupts = <0x0 0xac 0x4>;
  971. clocks = <0x6>;
  972. status = "disabled";
  973. };
  974. };
  975.  
  976. 3-3-v-regulator {
  977. compatible = "regulator-fixed";
  978. regulator-name = "3.3V";
  979. regulator-min-microvolt = <0x325aa0>;
  980. regulator-max-microvolt = <0x325aa0>;
  981. linux,phandle = <0x27>;
  982. phandle = <0x27>;
  983. };
  984.  
  985. leds {
  986. compatible = "gpio-leds";
  987.  
  988. hps0 {
  989. label = "hps_led0";
  990. gpios = <0x2e 0x18 0x0>;
  991. linux,default-trigger = "heartbeat";
  992. };
  993. };
  994. };
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