module video_ram (
  input wire vram_clk,          // Input: Clock for vram read latch.
  input wire [14:0] vram_addr,  // Input: Address for vram port.
  output wire [3:0] vram_out     // Output: Vram port.
);
  //memory declaration.
  reg [7:0] ram[0:9600];
  initial $readmemh("possum.hex", ram);

  reg [7:0] vram_out_i;

  //Reading from the RAM in 4-bit chunks
  always @(posedge vram_clk)
    vram_out_i <= ram[vram_addr[14:1]];

  always @(posedge vram_clk)
    lsb <= vram_addr[0];

  assign vram_out = lsb ? vram_out_i[7:4] : vram_out_i[3:0];

endmodule