module Verilog1(Out, A, B, Sel1, Sel0);
 	output reg [7: 0]Out;
 	input [7: 0]A;
	input [7: 0]B;
	input Sel1, Sel0;

 	always @(Sel1 or Sel0 or A or B)
 	 	begin
 	 	 	case({Sel1, Sel0})
			2'b00: Out = 0;
			2'b01: Out = A+B;
				2'b10: Out = A-B;
				2'b11: Out = A*B;
 	 	 	 	default: Out = 1'bx;
				endcase
 	 	end
		endmodule