alpha_lights

//////////////////////////////////////////////////////////////////////////////////
//
// Link:https://imgur.com/a/g6oK4vi
//
// Create Date: 18.06.2019 08:35:02
// Design Name:
// Module Name: Alpha_lights
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Alpha_lights(alpha, beta, gamma, alpha_cond, beta_cond, clk, rst);
parameter   A=3'b001,
            AB=3'b011,
            B=3'b010,
            BC=3'b110,
            C=3'b100,
            CA=3'b101;

input  clk, rst;
output reg[2:0] alpha ,beta , gamma;
output reg alpha_cond , beta_cond;

reg[7:0] cnt=0;
reg cnt10s=0, cnt3s=0, cnt_en=0;

reg[2:0] state, next_state;


always @(posedge clk or negedge rst) //  rst
begin

    if(~rst) state <= A;
    else if(cnt_en == 1) state <= next_state;

end
always @(posedge clk) // clk
begin

   if(cnt_en == 0)
   begin
   cnt <= cnt + 1;
    if (cnt3s&&(cnt == 3))
        begin
        cnt_en = 1;
        cnt <= 0;
        //state  <= next_state;
        end
    if(cnt10s&&(cnt==15))
        begin
        cnt_en = 1;
        cnt <= 0;
        //state  <= next_state;
        end
   end
   else
   begin
    cnt_en = 0;
    cnt <= cnt + 1;
   end
 end

always @(posedge clk)
begin
    case(state)
    A:
    begin
    alpha = 3'b001;
    beta = 3'b100;
    gamma = 3'b100;
    alpha_cond = 0;
    beta_cond = 1;

    cnt10s = 1;
    cnt3s = 0;
    if(cnt_en)
    begin
    next_state = AB;

    end
    else  next_state = A;
    end
    AB:
    begin
       alpha = 3'b010;
       beta =  3'b100;
       gamma = 3'b100;
       alpha_cond = 0;
       beta_cond = 0;

       cnt10s = 0;
       cnt3s = 1;

       next_state = B;
    end
    B:
    begin
       alpha = 3'b100;
       beta =  3'b001;
       gamma = 3'b100;
       alpha_cond = 1;
       beta_cond = 0;

        cnt10s = 1;
        cnt3s = 0;
        next_state = BC;

    end
    BC:
     begin
        alpha = 3'b100;
        beta =  3'b010;
        gamma = 3'b100;
        alpha_cond = 0;
        beta_cond = 0;

       cnt10s = 0;
       cnt3s = 1;
       next_state = C;
     end
    C:
     begin
        alpha = 3'b100;
        beta =  3'b100;
        gamma = 3'b001;
        alpha_cond = 0;
        beta_cond = 1;

        cnt10s = 1;
        cnt3s = 0;
        next_state = CA;
     end
    CA:
     begin
        alpha = 3'b100;
        beta =  3'b100;
        gamma = 3'b010;
        alpha_cond = 0;
        beta_cond = 0;

       cnt10s = 0;
       cnt3s = 1;
       next_state = A;
     end
    default: next_state = A;
    endcase
end
endmodule