module testbench();

timeunit 10ns;

timeprecision 1ns;

logic clk=0;
logic Reset, ClearA_LoadB, Run;
//inputs
logic [7:0] S;
logic [7:0] B;
//outputs
logic [7:0] A;
logic X;

always begin : CLOCK_GENERATION
#1 Clk = ~Clk;
end

initial begin: CLOCK_INITIALIZATION
    Clk = 0;
end

// Testing begins here
// The initial block is not synthesizable
// Everything happens sequentially inside an initial block
// as in a software program
initial begin: TEST_VECTORS
Reset = 1;
S = 8'b00000111;
ClearA_LoadB = 0;
B = 8'b11000101;
Execute = 0;

end
endmodule