module rng(start, r_out);
input start /* synthesis keep */;
reg rout /* synthesis keep */;
output r_out;
wire n0 /* synthesis keep */;
wire n1 /* synthesis keep */;
wire n2 /* synthesis keep */;
wire n3 /* synthesis keep */;
wire n4 /* synthesis keep */;
wire n5 /* synthesis keep */;
mynot(n0,(r_out&start));
mynot(n1,n0);
mynot(n2,n1);
mynot(n3,n2);
mynot(n4,n3);
mynot(n5,n4);
mynot(r_out,n5);
endmodule

module mynot(
    input x,
    output wire y
    );
    not(y,x);
endmodule