module runner;
    reg [3:0] a, b;
    reg [3:0] func;
    wire [7:0] alu_out;
    wire [6:0] hex1_out, hex2_out;

    integer _a, _b;
    ALU my_alu(a, b, 0, alu_out);
    hex_display hex1(alu_out[3:0], hex1_out);
    hex_display hex2(alu_out[7:4], hex2_out);
    initial
    begin
        #1 $monitor("a=%b b=%b out=%b hex2=%b, hex1=%b", a, b, alu_out, hex2_out, hex1_out);
        for (_a = 0; _a < 16; _a = _a + 1)
        begin
            for (_b = 0; _b < 16; _b = _b + 1)
            begin
                a = _a; b = _b;
                #1;
            end
        end
    end
endmodule

module ALU(a, b, f, out);
    input [3:0] a, b, f;
    output [7:0] out;
    reg out;

    wire [7:0] result0, result1, result2, result3, result4, result5;
    reg [7:0] has_1, all_1;

    Adder5Bit my_adder(a, b, 1'b0, result0);
    assign result1 = a + b;
    assign result2 = {a | b,  a ^ b};
    assign result3 = | {a, b};
    assign result4 = & {a, b};
    assign result5 = {a, b};

    always @ (*)
    begin
        case(f)
            'd0: out = result0;
            'd1: out = result1;
            'd2: out = result2;
            'd3: out = result3;
            'd4: out = result4;
            'd5: out = result5;
            default: out = 'b0;
        endcase
    end

endmodule


module Adder5Bit(a, b, cin, out);
    input [3:0] a, b;
    input cin;
    output [4:0] out;
    wire cout;

    wire _carry1, _carry2, _carry3, _carry4;

    FullAdder bit1(a[0], b[0], cin, out[0], _carry1);
    FullAdder bit2(a[1], b[1], _carry1, out[1], _carry2);
    FullAdder bit3(a[2], b[2], _carry2, out[2], _carry3);
    FullAdder bit4(a[3], b[3], _carry3, out[3], _carry4);
    FullAdder bit5('b0, 'b0, _carry4, out[4], cout);
endmodule

module FullAdder(a, b, cin, out, cout);
    input a, b, cin;
    output out, cout;

    assign out = a ^ b ^ cin;
    assign cout = a & b | b & cin | a & cin;

endmodule

module hex_display(IN, OUT);
    input [3:0] IN;
     output reg [7:0] OUT;

     always @(*)
     begin
        case(IN[3:0])
            4'b0000: OUT = 7'b1000000;
            4'b0001: OUT = 7'b1111001;
            4'b0010: OUT = 7'b0100100;
            4'b0011: OUT = 7'b0110000;
            4'b0100: OUT = 7'b0011001;
            4'b0101: OUT = 7'b0010010;
            4'b0110: OUT = 7'b0000010;
            4'b0111: OUT = 7'b1111000;
            4'b1000: OUT = 7'b0000000;
            4'b1001: OUT = 7'b0011000;
            4'b1010: OUT = 7'b0001000;
            4'b1011: OUT = 7'b0000011;
            4'b1100: OUT = 7'b1000110;
            4'b1101: OUT = 7'b0100001;
            4'b1110: OUT = 7'b0000110;
            4'b1111: OUT = 7'b0001110;

            default: OUT = 7'b0111111;
        endcase

    end
endmodule