demo.v

module maggas_2_Bit_Counter(clk,clr_,in,out);
//Declare our inputs
input clk,clr_;
//if in == 1 then up counter
//if in == 0 then down counter
input in;
//Declare our outputs
output[1:0] out;
//Internal Variables
//These are used for the states
(* fsm_encoding="auto" *) reg[1:0] S;
reg[1:0] S_; //S = Present, S_ = Next
reg[1:0] tmp_out;
//Some Local Parameters for us
//This is just for readable code
localparam  S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//Obfuscation states S0-S4
//Normnal mode states S5-S12
//Enabling Key = 10101

//Combinational Logic that Defines the next states
//Transition function δ:IxS------> S
always @ (in,S) begin
  //Here a case statement starts to deftermine the states
  case(S)
    //////////////////////////////
    S0: if(in == 0)
          S_ = S1;
    //////////////////////////////
    S1: if(in == 1)
          S_ = S2;
    //////////////////////////////
    S2: if(in == 0)
          S_ = S3;
    //////////////////////////////
    S3: if(in == 1)
          S_ = S0;
    //////////////////////////////
    default: S_ = 2'bxx; //this is so that verilog knows oti sto vilo m
  endcase
end

//Define State Update
always @ (negedge clr_, posedge clk) begin
  //An to clr en 0 tote kame reset to FSM, aka parto sto proto state aka to
  //obfuscation mode sto state 0
  if(!clr_)
    S <= S0;
  //Else an to clr en 1 tote men kamis reset to FSM je vale to current state na pai
  //sto calculated next state (pou ivres me to combinational logic pio pano)
  else
    S <= S_;
end
//Define Output combinational logic
//This is the output functuion
// λ: S--->O (Moore)
// λ: SXI--->O (Mealy)
always @ (*) begin
    //So that output is the state
    tmp_out <= S; //normal mode as a 3bit counter
end

//I have no idea what this
//I think this is an assign block
assign out = tmp_out;

endmodule //End of module Obfuscated_3_Bit_Counter