// inputs to set
        // eInst ?? (not rly, used intermediately)
        // e2w
        // dataE
        // dstE
        // dCache.req  ...
        // e/dstall????
        // annul
        // redirectPC

        // outputs to read
        // d2e



        if (isValid(d2e)) begin
            let d2e_v = fromMaybe(?, d2e);
            let eInst = execute(d2e_v.dInst, d2e_v.rVal1, d2e_v.rVal2, d2e_v.pc);
            let is_load = eInst.iType == LOAD;
            let is_store = eInst.iType == STORE;
            let req_enabled = dCache.reqEnabled;
            let e_to_writeback = E2W{pc: d2e_v.pc, iType: eInst.iType, dst: eInst.dst, data: eInst.data};
            let need_to_annul = (eInst.nextPc != d2e_v.pc + 4)
            let data = is_load ? ? : eInst.data;
            let memrequest = Valid(MemReq{addr: eInst.addr, op: Ld, data: data}
            dCache.req = dStall ? Invalid : (is_load ? (req_enabled ? memrequest) : Invalid) : (is_store ? (req_enabled ? memrequest) : Invalid) : Invalid));
            eStall = dstall? True : (is_load ? (req_enabled ? False : True) : (is_store ? (req_enabled ? False : True) : False));
            //eStall =
            e2w <= dStall ? e2w : Valid(e_to_writeback);
            dstE = dStall ? Invalid : Valid(fromMaybe(?, eInst.dst));
            annul = dStall ? False : (need_to_annul ? True: False)
            redirectPC = dStall ? eInst.nextPc : (need_to_annul ? eInst.nextPc : eInst.nextPc ); // arbitrary setting it everywhere to same thing

        end else begin
            e2w <= Invalid;
        end