module alu1_test;
    // exhaustively test your 1-bit ALU implementation by adapting mux4_tb.v
    // cycle through all combinations of A and B every 16 time units
    reg A = 0;
    always #1 A = !A;
    reg B = 0;
    always #2 B = !B;

    reg [3:0] control = `ALU_ADD;
    reg cin = 0;
    initial begin
        $dumpfile("alu1.vcd");
        $dumpvars(0, alu1_test);

        // control is initially ALU_ADD
        # 16 control = `ALU_SUB; // wait 16 time units and then set it to subtract
        # 16 control = `ALU_AND; // wait 16 time units and then set it to and
        # 16 control = `ALU_OR;  // wait 16 time units and then set it to or
        # 16 control = `ALU_NOR; // wait 16 time units and then set it to nor
        # 16 control = `ALU_XOR; // wait 16 time units and then set it to xor
        # 16 $finish; // wait 16 time units and then end the simulation
    end

    wire out, cout;
    alu1 a1(out, cout, A, B, cin, control);
endmodule   //alu1_test