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linux-rockchip-v4l2-5.5-work-in-progress-v5.5_v5.5.patch

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Feb 16th, 2020
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  1. diff -uNr '--exclude=.git' linux-5.5/Documentation/media/uapi/v4l/ext-ctrls-codec.rst linux-rockchip-v4l2-5.5-work-in-progress-v5.5/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
  2. --- linux-5.5/Documentation/media/uapi/v4l/ext-ctrls-codec.rst 2020-01-26 16:23:03.000000000 -0800
  3. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/Documentation/media/uapi/v4l/ext-ctrls-codec.rst 2020-02-14 22:59:03.205507039 -0800
  4. @@ -2028,6 +2028,18 @@
  5. * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
  6. - 0x00000004
  7. - The DPB entry is a long term reference frame
  8. + * - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE``
  9. + - 0x00000008
  10. + - The DPB entry is a field picture
  11. + * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_TOP``
  12. + - 0x00000010
  13. + - The DPB entry is a top field reference
  14. + * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM``
  15. + - 0x00000020
  16. + - The DPB entry is a bottom field reference
  17. + * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME``
  18. + - 0x00000030
  19. + - The DPB entry is a reference frame
  20.  
  21. ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)``
  22. Specifies the decoding mode to use. Currently exposes slice-based and
  23. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_drv.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_drv.c
  24. --- linux-5.5/drivers/staging/media/hantro/hantro_drv.c 2020-01-26 16:23:03.000000000 -0800
  25. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_drv.c 2020-02-14 22:59:08.117542364 -0800
  26. @@ -53,7 +53,7 @@
  27. if (index < 0)
  28. return 0;
  29. buf = vb2_get_buffer(q, index);
  30. - return vb2_dma_contig_plane_dma_addr(buf, 0);
  31. + return hantro_get_dec_buf_addr(ctx, buf);
  32. }
  33.  
  34. static int
  35. @@ -152,16 +152,21 @@
  36. }
  37. }
  38.  
  39. -void hantro_prepare_run(struct hantro_ctx *ctx)
  40. +void hantro_start_prepare_run(struct hantro_ctx *ctx)
  41. {
  42. struct vb2_v4l2_buffer *src_buf;
  43.  
  44. src_buf = hantro_get_src_buf(ctx);
  45. v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
  46. &ctx->ctrl_handler);
  47. +
  48. + if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
  49. + hantro_postproc_enable(ctx);
  50. + else
  51. + hantro_postproc_disable(ctx);
  52. }
  53.  
  54. -void hantro_finish_run(struct hantro_ctx *ctx)
  55. +void hantro_end_prepare_run(struct hantro_ctx *ctx)
  56. {
  57. struct vb2_v4l2_buffer *src_buf;
  58.  
  59. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_g1_h264_dec.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_h264_dec.c
  60. --- linux-5.5/drivers/staging/media/hantro/hantro_g1_h264_dec.c 2020-01-26 16:23:03.000000000 -0800
  61. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_h264_dec.c 2020-02-14 22:59:08.117542364 -0800
  62. @@ -1,6 +1,6 @@
  63. // SPDX-License-Identifier: GPL-2.0
  64. /*
  65. - * Rockchip RK3288 VPU codec driver
  66. + * Hantro VPU codec driver
  67. *
  68. * Copyright (c) 2014 Rockchip Electronics Co., Ltd.
  69. * Hertz Wong <hertz.wong@rock-chips.com>
  70. @@ -15,248 +15,430 @@
  71.  
  72. #include <media/v4l2-mem2mem.h>
  73.  
  74. -#include "hantro_g1_regs.h"
  75. #include "hantro_hw.h"
  76. #include "hantro_v4l2.h"
  77.  
  78. -static void set_params(struct hantro_ctx *ctx)
  79. -{
  80. - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
  81. - const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
  82. - const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
  83. - const struct v4l2_ctrl_h264_sps *sps = ctrls->sps;
  84. - const struct v4l2_ctrl_h264_pps *pps = ctrls->pps;
  85. - struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx);
  86. - struct hantro_dev *vpu = ctx->dev;
  87. - u32 reg;
  88. +#define G1_SWREG(nr) ((nr) * 4)
  89.  
  90. - /* Decoder control register 0. */
  91. - reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0);
  92. - if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)
  93. - reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E;
  94. - if (sps->profile_idc > 66) {
  95. - reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E;
  96. - if (dec_param->nal_ref_idc)
  97. - reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E;
  98. - }
  99. +#define G1_REG_RLC_VLC_BASE G1_SWREG(12)
  100. +#define G1_REG_DEC_OUT_BASE G1_SWREG(13)
  101. +#define G1_REG_REFER0_BASE G1_SWREG(14)
  102. +#define G1_REG_REFER1_BASE G1_SWREG(15)
  103. +#define G1_REG_REFER2_BASE G1_SWREG(16)
  104. +#define G1_REG_REFER3_BASE G1_SWREG(17)
  105. +#define G1_REG_REFER4_BASE G1_SWREG(18)
  106. +#define G1_REG_REFER5_BASE G1_SWREG(19)
  107. +#define G1_REG_REFER6_BASE G1_SWREG(20)
  108. +#define G1_REG_REFER7_BASE G1_SWREG(21)
  109. +#define G1_REG_REFER8_BASE G1_SWREG(22)
  110. +#define G1_REG_REFER9_BASE G1_SWREG(23)
  111. +#define G1_REG_REFER10_BASE G1_SWREG(24)
  112. +#define G1_REG_REFER11_BASE G1_SWREG(25)
  113. +#define G1_REG_REFER12_BASE G1_SWREG(26)
  114. +#define G1_REG_REFER13_BASE G1_SWREG(27)
  115. +#define G1_REG_REFER14_BASE G1_SWREG(28)
  116. +#define G1_REG_REFER15_BASE G1_SWREG(29)
  117. +#define G1_REG_QTABLE_BASE G1_SWREG(40)
  118. +#define G1_REG_DIR_MV_BASE G1_SWREG(41)
  119. +#define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0)
  120. +
  121. +#define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
  122. +#define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0)
  123. +#define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0)
  124. +#define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0)
  125. +#define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0)
  126. +#define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0)
  127. +#define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0)
  128. +#define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11))
  129. +#define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0)
  130. +#define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0)
  131. +#define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0)
  132. +#define G1_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(6) : 0)
  133. +#define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0)
  134. +#define G1_REG_DEC_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
  135. +
  136. +#define G1_REG_DEC_MODE(v) (((v) << 28) & GENMASK(31, 28))
  137. +#define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0)
  138. +#define G1_REG_PIC_INTERLACE_E(v) ((v) ? BIT(23) : 0)
  139. +#define G1_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(22) : 0)
  140. +#define G1_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(19) : 0)
  141. +#define G1_REG_FILTERING_DIS(v) ((v) ? BIT(14) : 0)
  142. +#define G1_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(13) : 0)
  143. +#define G1_REG_WRITE_MVS_E(v) ((v) ? BIT(12) : 0)
  144. +#define G1_REG_SEQ_MBAFF_E(v) ((v) ? BIT(10) : 0)
  145. +#define G1_REG_PICORD_COUNT_E(v) ((v) ? BIT(9) : 0)
  146. +#define G1_REG_DEC_AXI_WR_ID(v) (((v) << 0) & GENMASK(7, 0))
  147. +
  148. +#define G1_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
  149. +#define G1_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
  150. +#define G1_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0))
  151. +
  152. +#define G1_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
  153. +#define G1_REG_TYPE1_QUANT_E(v) ((v) ? BIT(24) : 0)
  154. +#define G1_REG_CH_QP_OFFSET(v) (((v) << 19) & GENMASK(23, 19))
  155. +#define G1_REG_CH_QP_OFFSET2(v) (((v) << 14) & GENMASK(18, 14))
  156. +#define G1_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0)
  157. +
  158. +#define G1_REG_START_CODE_E(v) ((v) ? BIT(31) : 0)
  159. +#define G1_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
  160. +#define G1_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(24) : 0)
  161. +#define G1_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
  162. +
  163. +#define G1_REG_CABAC_E(v) ((v) ? BIT(31) : 0)
  164. +#define G1_REG_BLACKWHITE_E(v) ((v) ? BIT(30) : 0)
  165. +#define G1_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(29) : 0)
  166. +#define G1_REG_WEIGHT_PRED_E(v) ((v) ? BIT(28) : 0)
  167. +#define G1_REG_WEIGHT_BIPR_IDC(v) (((v) << 26) & GENMASK(27, 26))
  168. +#define G1_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16))
  169. +#define G1_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0))
  170. +
  171. +#define G1_REG_CONST_INTRA_E(v) ((v) ? BIT(31) : 0)
  172. +#define G1_REG_FILT_CTRL_PRES(v) ((v) ? BIT(30) : 0)
  173. +#define G1_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(29) : 0)
  174. +#define G1_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(28) : 0)
  175. +#define G1_REG_REFPIC_MK_LEN(v) (((v) << 17) & GENMASK(27, 17))
  176. +#define G1_REG_IDR_PIC_E(v) ((v) ? BIT(16) : 0)
  177. +#define G1_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0))
  178. +
  179. +#define G1_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24))
  180. +#define G1_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19))
  181. +#define G1_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14))
  182. +#define G1_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0))
  183. +
  184. +#define G1_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25))
  185. +#define G1_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20))
  186. +#define G1_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15))
  187. +#define G1_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10))
  188. +#define G1_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5))
  189. +#define G1_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0))
  190. +
  191. +#define G1_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25))
  192. +#define G1_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20))
  193. +#define G1_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15))
  194. +#define G1_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10))
  195. +#define G1_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5))
  196. +#define G1_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0))
  197. +
  198. +#define G1_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16))
  199. +#define G1_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0))
  200. +
  201. +#define G1_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16))
  202. +#define G1_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0))
  203. +
  204. +#define G1_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16))
  205. +#define G1_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0))
  206. +
  207. +#define G1_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16))
  208. +#define G1_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0))
  209. +
  210. +#define G1_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16))
  211. +#define G1_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0))
  212. +
  213. +#define G1_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16))
  214. +#define G1_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0))
  215. +
  216. +#define G1_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16))
  217. +#define G1_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0))
  218. +
  219. +#define G1_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16))
  220. +#define G1_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0))
  221. +
  222. +#define G1_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0))
  223. +
  224. +#define G1_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0))
  225. +
  226. +#define G1_REG_BINIT_RLIST_B2(v) (((v) << 25) & GENMASK(29, 25))
  227. +#define G1_REG_BINIT_RLIST_F2(v) (((v) << 20) & GENMASK(24, 20))
  228. +#define G1_REG_BINIT_RLIST_B1(v) (((v) << 15) & GENMASK(19, 15))
  229. +#define G1_REG_BINIT_RLIST_F1(v) (((v) << 10) & GENMASK(14, 10))
  230. +#define G1_REG_BINIT_RLIST_B0(v) (((v) << 5) & GENMASK(9, 5))
  231. +#define G1_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))
  232. +
  233. +#define G1_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25))
  234. +#define G1_REG_BINIT_RLIST_F5(v) (((v) << 20) & GENMASK(24, 20))
  235. +#define G1_REG_BINIT_RLIST_B4(v) (((v) << 15) & GENMASK(19, 15))
  236. +#define G1_REG_BINIT_RLIST_F4(v) (((v) << 10) & GENMASK(14, 10))
  237. +#define G1_REG_BINIT_RLIST_B3(v) (((v) << 5) & GENMASK(9, 5))
  238. +#define G1_REG_BINIT_RLIST_F3(v) (((v) << 0) & GENMASK(4, 0))
  239. +
  240. +#define G1_REG_BINIT_RLIST_B8(v) (((v) << 25) & GENMASK(29, 25))
  241. +#define G1_REG_BINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20))
  242. +#define G1_REG_BINIT_RLIST_B7(v) (((v) << 15) & GENMASK(19, 15))
  243. +#define G1_REG_BINIT_RLIST_F7(v) (((v) << 10) & GENMASK(14, 10))
  244. +#define G1_REG_BINIT_RLIST_B6(v) (((v) << 5) & GENMASK(9, 5))
  245. +#define G1_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0))
  246. +
  247. +#define G1_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25))
  248. +#define G1_REG_BINIT_RLIST_F11(v) (((v) << 20) & GENMASK(24, 20))
  249. +#define G1_REG_BINIT_RLIST_B10(v) (((v) << 15) & GENMASK(19, 15))
  250. +#define G1_REG_BINIT_RLIST_F10(v) (((v) << 10) & GENMASK(14, 10))
  251. +#define G1_REG_BINIT_RLIST_B9(v) (((v) << 5) & GENMASK(9, 5))
  252. +#define G1_REG_BINIT_RLIST_F9(v) (((v) << 0) & GENMASK(4, 0))
  253. +
  254. +#define G1_REG_BINIT_RLIST_B14(v) (((v) << 25) & GENMASK(29, 25))
  255. +#define G1_REG_BINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20))
  256. +#define G1_REG_BINIT_RLIST_B13(v) (((v) << 15) & GENMASK(19, 15))
  257. +#define G1_REG_BINIT_RLIST_F13(v) (((v) << 10) & GENMASK(14, 10))
  258. +#define G1_REG_BINIT_RLIST_B12(v) (((v) << 5) & GENMASK(9, 5))
  259. +#define G1_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0))
  260. +
  261. +#define G1_REG_PINIT_RLIST_F3(v) (((v) << 25) & GENMASK(29, 25))
  262. +#define G1_REG_PINIT_RLIST_F2(v) (((v) << 20) & GENMASK(24, 20))
  263. +#define G1_REG_PINIT_RLIST_F1(v) (((v) << 15) & GENMASK(19, 15))
  264. +#define G1_REG_PINIT_RLIST_F0(v) (((v) << 10) & GENMASK(14, 10))
  265. +#define G1_REG_BINIT_RLIST_B15(v) (((v) << 5) & GENMASK(9, 5))
  266. +#define G1_REG_BINIT_RLIST_F15(v) (((v) << 0) & GENMASK(4, 0))
  267. +
  268. +#define G1_REG_STARTMB_X(v) (((v) << 23) & GENMASK(31, 23))
  269. +#define G1_REG_STARTMB_Y(v) (((v) << 15) & GENMASK(22, 15))
  270. +
  271. +#define G1_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22))
  272. +#define G1_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12))
  273. +#define G1_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2))
  274.  
  275. - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) &&
  276. - (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD ||
  277. - slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
  278. - reg |= G1_REG_DEC_CTRL0_PIC_INTERLACE_E;
  279. - if (slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)
  280. - reg |= G1_REG_DEC_CTRL0_PIC_FIELDMODE_E;
  281. - if (!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD))
  282. - reg |= G1_REG_DEC_CTRL0_PIC_TOPFIELD_E;
  283. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0);
  284. -
  285. - /* Decoder control register 1. */
  286. - reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)) |
  287. - G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |
  288. - G1_REG_DEC_CTRL1_REF_FRAMES(sps->max_num_ref_frames);
  289. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1);
  290. -
  291. - /* Decoder control register 2. */
  292. - reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) |
  293. - G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset);
  294. -
  295. - /* always use the matrix sent from userspace */
  296. - reg |= G1_REG_DEC_CTRL2_TYPE1_QUANT_E;
  297. -
  298. - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
  299. - reg |= G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E;
  300. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2);
  301. -
  302. - /* Decoder control register 3. */
  303. - reg = G1_REG_DEC_CTRL3_START_CODE_E |
  304. - G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) |
  305. - G1_REG_DEC_CTRL3_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
  306. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3);
  307. -
  308. - /* Decoder control register 4. */
  309. - reg = G1_REG_DEC_CTRL4_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) |
  310. - G1_REG_DEC_CTRL4_FRAMENUM(slices[0].frame_num) |
  311. - G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc);
  312. - if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE)
  313. - reg |= G1_REG_DEC_CTRL4_CABAC_E;
  314. - if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE)
  315. - reg |= G1_REG_DEC_CTRL4_DIR_8X8_INFER_E;
  316. - if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0)
  317. - reg |= G1_REG_DEC_CTRL4_BLACKWHITE_E;
  318. - if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED)
  319. - reg |= G1_REG_DEC_CTRL4_WEIGHT_PRED_E;
  320. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4);
  321. -
  322. - /* Decoder control register 5. */
  323. - reg = G1_REG_DEC_CTRL5_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) |
  324. - G1_REG_DEC_CTRL5_IDR_PIC_ID(slices[0].idr_pic_id);
  325. - if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED)
  326. - reg |= G1_REG_DEC_CTRL5_CONST_INTRA_E;
  327. - if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT)
  328. - reg |= G1_REG_DEC_CTRL5_FILT_CTRL_PRES;
  329. - if (pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT)
  330. - reg |= G1_REG_DEC_CTRL5_RDPIC_CNT_PRES;
  331. - if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE)
  332. - reg |= G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E;
  333. - if (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC)
  334. - reg |= G1_REG_DEC_CTRL5_IDR_PIC_E;
  335. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5);
  336. -
  337. - /* Decoder control register 6. */
  338. - reg = G1_REG_DEC_CTRL6_PPS_ID(slices[0].pic_parameter_set_id) |
  339. - G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |
  340. - G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |
  341. - G1_REG_DEC_CTRL6_POC_LENGTH(slices[0].pic_order_cnt_bit_size);
  342. - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6);
  343. -
  344. - /* Error concealment register. */
  345. - vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC);
  346. -
  347. - /* Prediction filter tap register. */
  348. - vdpu_write_relaxed(vpu,
  349. - G1_REG_PRED_FLT_PRED_BC_TAP_0_0(1) |
  350. - G1_REG_PRED_FLT_PRED_BC_TAP_0_1(-5 & 0x3ff) |
  351. - G1_REG_PRED_FLT_PRED_BC_TAP_0_2(20),
  352. - G1_REG_PRED_FLT);
  353. -
  354. - /* Reference picture buffer control register. */
  355. - vdpu_write_relaxed(vpu, 0, G1_REG_REF_BUF_CTRL);
  356. -
  357. - /* Reference picture buffer control register 2. */
  358. - vdpu_write_relaxed(vpu, G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(8),
  359. - G1_REG_REF_BUF_CTRL2);
  360. -}
  361. +#define G1_REG_REFBU_E(v) ((v) ? BIT(31) : 0)
  362. +
  363. +#define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0))
  364.  
  365. -static void set_ref(struct hantro_ctx *ctx)
  366. +void hantro_g1_h264_dec_run(struct hantro_ctx *ctx)
  367. {
  368. - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
  369. - const u8 *b0_reflist, *b1_reflist, *p_reflist;
  370. struct hantro_dev *vpu = ctx->dev;
  371. - u32 dpb_longterm = 0;
  372. - u32 dpb_valid = 0;
  373. - int reg_num;
  374. + struct vb2_v4l2_buffer *src_buf, *dst_buf;
  375. + const struct hantro_h264_dec_ctrls *ctrls;
  376. + const struct v4l2_ctrl_h264_decode_params *decode;
  377. + const struct v4l2_ctrl_h264_slice_params *slices;
  378. + const struct v4l2_ctrl_h264_sps *sps;
  379. + const struct v4l2_ctrl_h264_pps *pps;
  380. + const u8 *b0_reflist, *b1_reflist, *p_reflist;
  381. + dma_addr_t addr;
  382. + size_t offset = 0;
  383. u32 reg;
  384. - int i;
  385.  
  386. - /*
  387. - * Set up bit maps of valid and long term DPBs.
  388. - * NOTE: The bits are reversed, i.e. MSb is DPB 0.
  389. - */
  390. - for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
  391. - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
  392. - dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
  393. -
  394. - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
  395. - dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
  396. - }
  397. - vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
  398. - vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
  399. + /* Prepare the H264 decoder context. */
  400. + if (hantro_h264_dec_prepare_run(ctx))
  401. + return;
  402.  
  403. - /*
  404. - * Set up reference frame picture numbers.
  405. - *
  406. - * Each G1_REG_REF_PIC(x) register contains numbers of two
  407. - * subsequential reference pictures.
  408. - */
  409. - for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) {
  410. - reg = 0;
  411. - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
  412. - reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num);
  413. - else
  414. - reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num);
  415. -
  416. - if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
  417. - reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num);
  418. - else
  419. - reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num);
  420. + src_buf = hantro_get_src_buf(ctx);
  421. + dst_buf = hantro_get_dst_buf(ctx);
  422.  
  423. - vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2));
  424. - }
  425. + ctrls = &ctx->h264_dec.ctrls;
  426. + decode = ctrls->decode;
  427. + slices = ctrls->slices;
  428. + sps = ctrls->sps;
  429. + pps = ctrls->pps;
  430.  
  431. b0_reflist = ctx->h264_dec.reflists.b0;
  432. b1_reflist = ctx->h264_dec.reflists.b1;
  433. p_reflist = ctx->h264_dec.reflists.p;
  434.  
  435. - /*
  436. - * Each G1_REG_BD_REF_PIC(x) register contains three entries
  437. - * of each forward and backward picture list.
  438. - */
  439. - reg_num = 0;
  440. - for (i = 0; i < 15; i += 3) {
  441. - reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i]) |
  442. - G1_REG_BD_REF_PIC_BINIT_RLIST_F1(b0_reflist[i + 1]) |
  443. - G1_REG_BD_REF_PIC_BINIT_RLIST_F2(b0_reflist[i + 2]) |
  444. - G1_REG_BD_REF_PIC_BINIT_RLIST_B0(b1_reflist[i]) |
  445. - G1_REG_BD_REF_PIC_BINIT_RLIST_B1(b1_reflist[i + 1]) |
  446. - G1_REG_BD_REF_PIC_BINIT_RLIST_B2(b1_reflist[i + 2]);
  447. - vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++));
  448. - }
  449. + reg = G1_REG_DEC_AXI_RD_ID(0xff) |
  450. + G1_REG_DEC_TIMEOUT_E(1) |
  451. + G1_REG_DEC_STRSWAP32_E(1) |
  452. + G1_REG_DEC_STRENDIAN_E(1) |
  453. + G1_REG_DEC_INSWAP32_E(1) |
  454. + G1_REG_DEC_OUTSWAP32_E(1) |
  455. + G1_REG_DEC_DATA_DISC_E(0) |
  456. + G1_REG_DEC_LATENCY(0) |
  457. + G1_REG_DEC_CLK_GATE_E(1) |
  458. + G1_REG_DEC_IN_ENDIAN(0) |
  459. + G1_REG_DEC_OUT_ENDIAN(1) |
  460. + G1_REG_DEC_ADV_PRE_DIS(0) |
  461. + G1_REG_DEC_SCMD_DIS(0) |
  462. + G1_REG_DEC_MAX_BURST(16);
  463. + vdpu_write_relaxed(vpu, reg, G1_SWREG(2));
  464. +
  465. + reg = G1_REG_DEC_MODE(0) |
  466. + G1_REG_RLC_MODE_E(0) |
  467. + G1_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) |
  468. + G1_REG_PIC_FIELDMODE_E(slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) |
  469. + G1_REG_PIC_TOPFIELD_E(!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)) |
  470. + G1_REG_FILTERING_DIS(0) |
  471. + G1_REG_PIC_FIXED_QUANT(0) |
  472. + G1_REG_WRITE_MVS_E(sps->profile_idc > 66 && decode->nal_ref_idc) |
  473. + G1_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) |
  474. + G1_REG_PICORD_COUNT_E(sps->profile_idc > 66) |
  475. + G1_REG_DEC_AXI_WR_ID(0);
  476. + vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
  477. +
  478. + reg = G1_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)) |
  479. + G1_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |
  480. + G1_REG_REF_FRAMES(sps->max_num_ref_frames);
  481. + vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
  482. +
  483. + reg = G1_REG_STRM_START_BIT(0) |
  484. + G1_REG_TYPE1_QUANT_E(1) |
  485. + G1_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) |
  486. + G1_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) |
  487. + G1_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY));
  488. + vdpu_write_relaxed(vpu, reg, G1_SWREG(5));
  489. +
  490. + reg = G1_REG_START_CODE_E(1) |
  491. + G1_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) |
  492. + G1_REG_CH_8PIX_ILEAV_E(0) |
  493. + G1_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
  494. + vdpu_write_relaxed(vpu, reg, G1_SWREG(6));
  495. +
  496. + reg = G1_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) |
  497. + G1_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) |
  498. + G1_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) |
  499. + G1_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) |
  500. + G1_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) |
  501. + G1_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) |
  502. + G1_REG_FRAMENUM(slices[0].frame_num);
  503. + vdpu_write_relaxed(vpu, reg, G1_SWREG(7));
  504. +
  505. + reg = G1_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) |
  506. + G1_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) |
  507. + G1_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) |
  508. + G1_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) |
  509. + G1_REG_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) |
  510. + G1_REG_IDR_PIC_E(decode->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) |
  511. + G1_REG_IDR_PIC_ID(slices[0].idr_pic_id);
  512. + vdpu_write_relaxed(vpu, reg, G1_SWREG(8));
  513. +
  514. + reg = G1_REG_PPS_ID(slices[0].pic_parameter_set_id) |
  515. + G1_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |
  516. + G1_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |
  517. + G1_REG_POC_LENGTH(slices[0].pic_order_cnt_bit_size);
  518. + vdpu_write_relaxed(vpu, reg, G1_SWREG(9));
  519. +
  520. + reg = G1_REG_PINIT_RLIST_F9(p_reflist[9]) |
  521. + G1_REG_PINIT_RLIST_F8(p_reflist[8]) |
  522. + G1_REG_PINIT_RLIST_F7(p_reflist[7]) |
  523. + G1_REG_PINIT_RLIST_F6(p_reflist[6]) |
  524. + G1_REG_PINIT_RLIST_F5(p_reflist[5]) |
  525. + G1_REG_PINIT_RLIST_F4(p_reflist[4]);
  526. + vdpu_write_relaxed(vpu, reg, G1_SWREG(10));
  527. +
  528. + reg = G1_REG_PINIT_RLIST_F15(p_reflist[15]) |
  529. + G1_REG_PINIT_RLIST_F14(p_reflist[14]) |
  530. + G1_REG_PINIT_RLIST_F13(p_reflist[13]) |
  531. + G1_REG_PINIT_RLIST_F12(p_reflist[12]) |
  532. + G1_REG_PINIT_RLIST_F11(p_reflist[11]) |
  533. + G1_REG_PINIT_RLIST_F10(p_reflist[10]);
  534. + vdpu_write_relaxed(vpu, reg, G1_SWREG(11));
  535. +
  536. + reg = G1_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) |
  537. + G1_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0));
  538. + vdpu_write_relaxed(vpu, reg, G1_SWREG(30));
  539. +
  540. + reg = G1_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) |
  541. + G1_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2));
  542. + vdpu_write_relaxed(vpu, reg, G1_SWREG(31));
  543. +
  544. + reg = G1_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) |
  545. + G1_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4));
  546. + vdpu_write_relaxed(vpu, reg, G1_SWREG(32));
  547. +
  548. + reg = G1_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) |
  549. + G1_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6));
  550. + vdpu_write_relaxed(vpu, reg, G1_SWREG(33));
  551. +
  552. + reg = G1_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) |
  553. + G1_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8));
  554. + vdpu_write_relaxed(vpu, reg, G1_SWREG(34));
  555. +
  556. + reg = G1_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) |
  557. + G1_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10));
  558. + vdpu_write_relaxed(vpu, reg, G1_SWREG(35));
  559. +
  560. + reg = G1_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) |
  561. + G1_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12));
  562. + vdpu_write_relaxed(vpu, reg, G1_SWREG(36));
  563. +
  564. + reg = G1_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) |
  565. + G1_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14));
  566. + vdpu_write_relaxed(vpu, reg, G1_SWREG(37));
  567. +
  568. + reg = G1_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm);
  569. + vdpu_write_relaxed(vpu, reg, G1_SWREG(38));
  570. +
  571. + reg = G1_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid);
  572. + vdpu_write_relaxed(vpu, reg, G1_SWREG(39));
  573. +
  574. + reg = G1_REG_BINIT_RLIST_B2(b1_reflist[2]) |
  575. + G1_REG_BINIT_RLIST_F2(b0_reflist[2]) |
  576. + G1_REG_BINIT_RLIST_B1(b1_reflist[1]) |
  577. + G1_REG_BINIT_RLIST_F1(b0_reflist[1]) |
  578. + G1_REG_BINIT_RLIST_B0(b1_reflist[0]) |
  579. + G1_REG_BINIT_RLIST_F0(b0_reflist[0]);
  580. + vdpu_write_relaxed(vpu, reg, G1_SWREG(42));
  581. +
  582. + reg = G1_REG_BINIT_RLIST_B5(b1_reflist[5]) |
  583. + G1_REG_BINIT_RLIST_F5(b0_reflist[5]) |
  584. + G1_REG_BINIT_RLIST_B4(b1_reflist[4]) |
  585. + G1_REG_BINIT_RLIST_F4(b0_reflist[4]) |
  586. + G1_REG_BINIT_RLIST_B3(b1_reflist[3]) |
  587. + G1_REG_BINIT_RLIST_F3(b0_reflist[3]);
  588. + vdpu_write_relaxed(vpu, reg, G1_SWREG(43));
  589. +
  590. + reg = G1_REG_BINIT_RLIST_B8(b1_reflist[8]) |
  591. + G1_REG_BINIT_RLIST_F8(b0_reflist[8]) |
  592. + G1_REG_BINIT_RLIST_B7(b1_reflist[7]) |
  593. + G1_REG_BINIT_RLIST_F7(b0_reflist[7]) |
  594. + G1_REG_BINIT_RLIST_B6(b1_reflist[6]) |
  595. + G1_REG_BINIT_RLIST_F6(b0_reflist[6]);
  596. + vdpu_write_relaxed(vpu, reg, G1_SWREG(44));
  597. +
  598. + reg = G1_REG_BINIT_RLIST_B11(b1_reflist[11]) |
  599. + G1_REG_BINIT_RLIST_F11(b0_reflist[11]) |
  600. + G1_REG_BINIT_RLIST_B10(b1_reflist[10]) |
  601. + G1_REG_BINIT_RLIST_F10(b0_reflist[10]) |
  602. + G1_REG_BINIT_RLIST_B9(b1_reflist[9]) |
  603. + G1_REG_BINIT_RLIST_F9(b0_reflist[9]);
  604. + vdpu_write_relaxed(vpu, reg, G1_SWREG(45));
  605. +
  606. + reg = G1_REG_BINIT_RLIST_B14(b1_reflist[14]) |
  607. + G1_REG_BINIT_RLIST_F14(b0_reflist[14]) |
  608. + G1_REG_BINIT_RLIST_B13(b1_reflist[13]) |
  609. + G1_REG_BINIT_RLIST_F13(b0_reflist[13]) |
  610. + G1_REG_BINIT_RLIST_B12(b1_reflist[12]) |
  611. + G1_REG_BINIT_RLIST_F12(b0_reflist[12]);
  612. + vdpu_write_relaxed(vpu, reg, G1_SWREG(46));
  613. +
  614. + reg = G1_REG_PINIT_RLIST_F3(p_reflist[3]) |
  615. + G1_REG_PINIT_RLIST_F2(p_reflist[2]) |
  616. + G1_REG_PINIT_RLIST_F1(p_reflist[1]) |
  617. + G1_REG_PINIT_RLIST_F0(p_reflist[0]) |
  618. + G1_REG_BINIT_RLIST_B15(b1_reflist[15]) |
  619. + G1_REG_BINIT_RLIST_F15(b0_reflist[15]);
  620. + vdpu_write_relaxed(vpu, reg, G1_SWREG(47));
  621. +
  622. + reg = G1_REG_STARTMB_X(0) |
  623. + G1_REG_STARTMB_Y(0);
  624. + vdpu_write_relaxed(vpu, reg, G1_SWREG(48));
  625. +
  626. + reg = G1_REG_PRED_BC_TAP_0_0(1) |
  627. + G1_REG_PRED_BC_TAP_0_1((u32)-5) |
  628. + G1_REG_PRED_BC_TAP_0_2(20);
  629. + vdpu_write_relaxed(vpu, reg, G1_SWREG(49));
  630.  
  631. - /*
  632. - * G1_REG_BD_P_REF_PIC register contains last entries (index 15)
  633. - * of forward and backward reference picture lists and first 4 entries
  634. - * of P forward picture list.
  635. - */
  636. - reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15]) |
  637. - G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15(b1_reflist[15]) |
  638. - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0(p_reflist[0]) |
  639. - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1(p_reflist[1]) |
  640. - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2(p_reflist[2]) |
  641. - G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3(p_reflist[3]);
  642. - vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC);
  643. -
  644. - /*
  645. - * Each G1_REG_FWD_PIC(x) register contains six consecutive
  646. - * entries of P forward picture list, starting from index 4.
  647. - */
  648. - reg_num = 0;
  649. - for (i = 4; i < HANTRO_H264_DPB_SIZE; i += 6) {
  650. - reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i]) |
  651. - G1_REG_FWD_PIC_PINIT_RLIST_F1(p_reflist[i + 1]) |
  652. - G1_REG_FWD_PIC_PINIT_RLIST_F2(p_reflist[i + 2]) |
  653. - G1_REG_FWD_PIC_PINIT_RLIST_F3(p_reflist[i + 3]) |
  654. - G1_REG_FWD_PIC_PINIT_RLIST_F4(p_reflist[i + 4]) |
  655. - G1_REG_FWD_PIC_PINIT_RLIST_F5(p_reflist[i + 5]);
  656. - vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++));
  657. - }
  658. + reg = G1_REG_REFBU_E(0);
  659. + vdpu_write_relaxed(vpu, reg, G1_SWREG(51));
  660.  
  661. - /* Set up addresses of DPB buffers. */
  662. - for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) {
  663. - dma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i);
  664. + reg = G1_REG_APF_THRESHOLD(8);
  665. + vdpu_write_relaxed(vpu, reg, G1_SWREG(55));
  666.  
  667. - vdpu_write_relaxed(vpu, dma_addr, G1_REG_ADDR_REF(i));
  668. - }
  669. -}
  670. -
  671. -static void set_buffers(struct hantro_ctx *ctx)
  672. -{
  673. - const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
  674. - struct vb2_v4l2_buffer *src_buf, *dst_buf;
  675. - struct hantro_dev *vpu = ctx->dev;
  676. - dma_addr_t src_dma, dst_dma;
  677. - size_t offset = 0;
  678. -
  679. - src_buf = hantro_get_src_buf(ctx);
  680. - dst_buf = hantro_get_dst_buf(ctx);
  681. + /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */
  682. + vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_QTABLE_BASE);
  683.  
  684. /* Source (stream) buffer. */
  685. - src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
  686. - vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR);
  687. + addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
  688. + vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
  689.  
  690. /* Destination (decoded frame) buffer. */
  691. - dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
  692. + addr = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf);
  693. /* Adjust dma addr to start at second line for bottom field */
  694. - if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
  695. + if (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
  696. offset = ALIGN(ctx->src_fmt.width, MB_DIM);
  697. - vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DST);
  698. + vdpu_write_relaxed(vpu, addr + offset, G1_REG_DEC_OUT_BASE);
  699.  
  700. /* Higher profiles require DMV buffer appended to reference frames. */
  701. - if (ctrls->sps->profile_idc > 66 && ctrls->decode->nal_ref_idc) {
  702. + if (sps->profile_idc > 66 && decode->nal_ref_idc) {
  703. unsigned int bytes_per_mb = 384;
  704.  
  705. /* DMV buffer for monochrome start directly after Y-plane */
  706. - if (ctrls->sps->profile_idc >= 100 &&
  707. - ctrls->sps->chroma_format_idc == 0)
  708. + if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0)
  709. bytes_per_mb = 256;
  710. offset = bytes_per_mb * MB_WIDTH(ctx->src_fmt.width) *
  711. MB_HEIGHT(ctx->src_fmt.height);
  712. @@ -265,42 +447,32 @@
  713. * DMV buffer is split in two for field encoded frames,
  714. * adjust offset for bottom field
  715. */
  716. - if (ctrls->slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
  717. + if (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
  718. offset += 32 * MB_WIDTH(ctx->src_fmt.width) *
  719. MB_HEIGHT(ctx->src_fmt.height);
  720. - vdpu_write_relaxed(vpu, dst_dma + offset, G1_REG_ADDR_DIR_MV);
  721. + vdpu_write_relaxed(vpu, addr + offset, G1_REG_DIR_MV_BASE);
  722. }
  723.  
  724. - /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */
  725. - vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);
  726. -}
  727. -
  728. -void hantro_g1_h264_dec_run(struct hantro_ctx *ctx)
  729. -{
  730. - struct hantro_dev *vpu = ctx->dev;
  731. -
  732. - /* Prepare the H264 decoder context. */
  733. - if (hantro_h264_dec_prepare_run(ctx))
  734. - return;
  735. -
  736. - /* Configure hardware registers. */
  737. - set_params(ctx);
  738. - set_ref(ctx);
  739. - set_buffers(ctx);
  740. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 0), G1_REG_REFER0_BASE);
  741. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 1), G1_REG_REFER1_BASE);
  742. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 2), G1_REG_REFER2_BASE);
  743. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 3), G1_REG_REFER3_BASE);
  744. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 4), G1_REG_REFER4_BASE);
  745. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 5), G1_REG_REFER5_BASE);
  746. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 6), G1_REG_REFER6_BASE);
  747. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 7), G1_REG_REFER7_BASE);
  748. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 8), G1_REG_REFER8_BASE);
  749. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 9), G1_REG_REFER9_BASE);
  750. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 10), G1_REG_REFER10_BASE);
  751. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 11), G1_REG_REFER11_BASE);
  752. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 12), G1_REG_REFER12_BASE);
  753. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 13), G1_REG_REFER13_BASE);
  754. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 14), G1_REG_REFER14_BASE);
  755. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 15), G1_REG_REFER15_BASE);
  756.  
  757. - hantro_finish_run(ctx);
  758. + hantro_end_prepare_run(ctx);
  759.  
  760. /* Start decoding! */
  761. - vdpu_write_relaxed(vpu,
  762. - G1_REG_CONFIG_DEC_AXI_RD_ID(0xffu) |
  763. - G1_REG_CONFIG_DEC_TIMEOUT_E |
  764. - G1_REG_CONFIG_DEC_OUT_ENDIAN |
  765. - G1_REG_CONFIG_DEC_STRENDIAN_E |
  766. - G1_REG_CONFIG_DEC_MAX_BURST(16) |
  767. - G1_REG_CONFIG_DEC_OUTSWAP32_E |
  768. - G1_REG_CONFIG_DEC_INSWAP32_E |
  769. - G1_REG_CONFIG_DEC_STRSWAP32_E |
  770. - G1_REG_CONFIG_DEC_CLK_GATE_E,
  771. - G1_REG_CONFIG);
  772. - vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
  773. + reg = G1_REG_DEC_E(1);
  774. + vdpu_write(vpu, reg, G1_SWREG(1));
  775. }
  776. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c
  777. --- linux-5.5/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c 2020-01-26 16:23:03.000000000 -0800
  778. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c 2020-02-14 22:59:08.117542364 -0800
  779. @@ -121,11 +121,11 @@
  780. vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
  781.  
  782. /* Destination frame buffer */
  783. - addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  784. + addr = hantro_get_dec_buf_addr(ctx, dst_buf);
  785. current_addr = addr;
  786.  
  787. if (picture->picture_structure == PICT_BOTTOM_FIELD)
  788. - addr += ALIGN(ctx->dst_fmt.width, 16);
  789. + addr += ALIGN(ctx->src_fmt.width, MB_DIM);
  790. vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);
  791.  
  792. if (!forward_addr)
  793. @@ -168,7 +168,7 @@
  794. dst_buf = hantro_get_dst_buf(ctx);
  795.  
  796. /* Apply request controls if any */
  797. - hantro_prepare_run(ctx);
  798. + hantro_start_prepare_run(ctx);
  799.  
  800. slice_params = hantro_get_ctrl(ctx,
  801. V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
  802. @@ -204,8 +204,8 @@
  803. G1_REG_DEC_AXI_WR_ID(0);
  804. vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
  805.  
  806. - reg = G1_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) |
  807. - G1_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) |
  808. + reg = G1_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)) |
  809. + G1_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |
  810. G1_REG_ALT_SCAN_E(picture->alternate_scan) |
  811. G1_REG_TOPFIELDFIRST_E(picture->top_field_first);
  812. vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
  813. @@ -244,7 +244,7 @@
  814. &dst_buf->vb2_buf,
  815. sequence, picture, slice_params);
  816.  
  817. - hantro_finish_run(ctx);
  818. + hantro_end_prepare_run(ctx);
  819.  
  820. reg = G1_REG_DEC_E(1);
  821. vdpu_write(vpu, reg, G1_SWREG(1));
  822. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_g1_regs.h linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_regs.h
  823. --- linux-5.5/drivers/staging/media/hantro/hantro_g1_regs.h 2020-01-26 16:23:03.000000000 -0800
  824. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_regs.h 2020-02-14 22:59:08.117542364 -0800
  825. @@ -9,6 +9,8 @@
  826. #ifndef HANTRO_G1_REGS_H_
  827. #define HANTRO_G1_REGS_H_
  828.  
  829. +#define G1_SWREG(nr) ((nr) * 4)
  830. +
  831. /* Decoder registers. */
  832. #define G1_REG_INTERRUPT 0x004
  833. #define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24)
  834. @@ -298,4 +300,55 @@
  835. #define G1_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 0)
  836. #define G1_REG_SOFT_RESET 0x194
  837.  
  838. +/* Post-processor registers. */
  839. +#define G1_REG_PP_INTERRUPT G1_SWREG(60)
  840. +#define G1_REG_PP_READY_IRQ BIT(12)
  841. +#define G1_REG_PP_IRQ BIT(8)
  842. +#define G1_REG_PP_IRQ_DIS BIT(4)
  843. +#define G1_REG_PP_PIPELINE_EN BIT(1)
  844. +#define G1_REG_PP_EXTERNAL_TRIGGER BIT(0)
  845. +#define G1_REG_PP_DEV_CONFIG G1_SWREG(61)
  846. +#define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
  847. +#define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16))
  848. +#define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0)
  849. +#define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0)
  850. +#define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0)
  851. +#define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0)
  852. +#define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0)
  853. +#define G1_REG_PP_OUTSWAP32_E(v) ((v) ? BIT(5) : 0)
  854. +#define G1_REG_PP_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
  855. +#define G1_REG_PP_IN_LUMA_BASE G1_SWREG(63)
  856. +#define G1_REG_PP_IN_CB_BASE G1_SWREG(64)
  857. +#define G1_REG_PP_IN_CR_BASE G1_SWREG(65)
  858. +#define G1_REG_PP_OUT_LUMA_BASE G1_SWREG(66)
  859. +#define G1_REG_PP_OUT_CHROMA_BASE G1_SWREG(67)
  860. +#define G1_REG_PP_CONTRAST_ADJUST G1_SWREG(68)
  861. +#define G1_REG_PP_COLOR_CONVERSION G1_SWREG(69)
  862. +#define G1_REG_PP_COLOR_CONVERSION0 G1_SWREG(70)
  863. +#define G1_REG_PP_COLOR_CONVERSION1 G1_SWREG(71)
  864. +#define G1_REG_PP_INPUT_SIZE G1_SWREG(72)
  865. +#define G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9))
  866. +#define G1_REG_PP_INPUT_SIZE_WIDTH(v) (((v) << 0) & GENMASK(8, 0))
  867. +#define G1_REG_PP_SCALING0 G1_SWREG(79)
  868. +#define G1_REG_PP_PADD_R(v) (((v) << 23) & GENMASK(27, 23))
  869. +#define G1_REG_PP_PADD_G(v) (((v) << 18) & GENMASK(22, 18))
  870. +#define G1_REG_PP_RANGEMAP_Y(v) ((v) ? BIT(31) : 0)
  871. +#define G1_REG_PP_RANGEMAP_C(v) ((v) ? BIT(30) : 0)
  872. +#define G1_REG_PP_YCBCR_RANGE(v) ((v) ? BIT(29) : 0)
  873. +#define G1_REG_PP_RGB_16(v) ((v) ? BIT(28) : 0)
  874. +#define G1_REG_PP_SCALING1 G1_SWREG(80)
  875. +#define G1_REG_PP_PADD_B(v) (((v) << 18) & GENMASK(22, 18))
  876. +#define G1_REG_PP_MASK_R G1_SWREG(82)
  877. +#define G1_REG_PP_MASK_G G1_SWREG(83)
  878. +#define G1_REG_PP_MASK_B G1_SWREG(84)
  879. +#define G1_REG_PP_CONTROL G1_SWREG(85)
  880. +#define G1_REG_PP_CONTROL_IN_FMT(v) (((v) << 29) & GENMASK(31, 29))
  881. +#define G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26))
  882. +#define G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15))
  883. +#define G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))
  884. +#define G1_REG_PP_MASK1_ORIG_WIDTH G1_SWREG(88)
  885. +#define G1_REG_PP_ORIG_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
  886. +#define G1_REG_PP_DISPLAY_WIDTH G1_SWREG(92)
  887. +#define G1_REG_PP_FUSE G1_SWREG(99)
  888. +
  889. #endif /* HANTRO_G1_REGS_H_ */
  890. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_g1_vp8_dec.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_vp8_dec.c
  891. --- linux-5.5/drivers/staging/media/hantro/hantro_g1_vp8_dec.c 2020-01-26 16:23:03.000000000 -0800
  892. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_g1_vp8_dec.c 2020-02-14 22:59:08.117542364 -0800
  893. @@ -422,7 +422,7 @@
  894. }
  895. vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0));
  896.  
  897. - dst_dma = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
  898. + dst_dma = hantro_get_dec_buf_addr(ctx, &vb2_dst->vb2_buf);
  899. vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST);
  900. }
  901.  
  902. @@ -430,12 +430,12 @@
  903. {
  904. const struct v4l2_ctrl_vp8_frame_header *hdr;
  905. struct hantro_dev *vpu = ctx->dev;
  906. - size_t height = ctx->dst_fmt.height;
  907. - size_t width = ctx->dst_fmt.width;
  908. + size_t height = ctx->src_fmt.height;
  909. + size_t width = ctx->src_fmt.width;
  910. u32 mb_width, mb_height;
  911. u32 reg;
  912.  
  913. - hantro_prepare_run(ctx);
  914. + hantro_start_prepare_run(ctx);
  915.  
  916. hdr = hantro_get_ctrl(ctx, V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER);
  917. if (WARN_ON(!hdr))
  918. @@ -496,7 +496,7 @@
  919. cfg_ref(ctx, hdr);
  920. cfg_buffers(ctx, hdr);
  921.  
  922. - hantro_finish_run(ctx);
  923. + hantro_end_prepare_run(ctx);
  924.  
  925. vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
  926. }
  927. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro.h linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro.h
  928. --- linux-5.5/drivers/staging/media/hantro/hantro.h 2020-01-26 16:23:03.000000000 -0800
  929. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro.h 2020-02-14 22:59:08.117542364 -0800
  930. @@ -60,6 +60,8 @@
  931. * @num_enc_fmts: Number of encoder formats.
  932. * @dec_fmts: Decoder formats.
  933. * @num_dec_fmts: Number of decoder formats.
  934. + * @postproc_fmts: Post-processor formats.
  935. + * @num_postproc_fmts: Number of post-processor formats.
  936. * @codec: Supported codecs
  937. * @codec_ops: Codec ops.
  938. * @init: Initialize hardware.
  939. @@ -70,6 +72,7 @@
  940. * @num_clocks: number of clocks in the array
  941. * @reg_names: array of register range names
  942. * @num_regs: number of register range names in the array
  943. + * @postproc_regs: &struct hantro_postproc_regs pointer
  944. */
  945. struct hantro_variant {
  946. unsigned int enc_offset;
  947. @@ -78,6 +81,8 @@
  948. unsigned int num_enc_fmts;
  949. const struct hantro_fmt *dec_fmts;
  950. unsigned int num_dec_fmts;
  951. + const struct hantro_fmt *postproc_fmts;
  952. + unsigned int num_postproc_fmts;
  953. unsigned int codec;
  954. const struct hantro_codec_ops *codec_ops;
  955. int (*init)(struct hantro_dev *vpu);
  956. @@ -88,6 +93,7 @@
  957. int num_clocks;
  958. const char * const *reg_names;
  959. int num_regs;
  960. + const struct hantro_postproc_regs *postproc_regs;
  961. };
  962.  
  963. /**
  964. @@ -213,6 +219,7 @@
  965. * context, and it's called right before
  966. * calling v4l2_m2m_job_finish.
  967. * @codec_ops: Set of operations related to codec mode.
  968. + * @postproc: Post-processing context.
  969. * @jpeg_enc: JPEG-encoding context.
  970. * @mpeg2_dec: MPEG-2-decoding context.
  971. * @vp8_dec: VP8-decoding context.
  972. @@ -237,6 +244,7 @@
  973. unsigned int bytesused);
  974.  
  975. const struct hantro_codec_ops *codec_ops;
  976. + struct hantro_postproc_ctx postproc;
  977.  
  978. /* Specific for particular codec modes. */
  979. union {
  980. @@ -274,6 +282,23 @@
  981. u32 mask;
  982. };
  983.  
  984. +struct hantro_postproc_regs {
  985. + struct hantro_reg pipeline_en;
  986. + struct hantro_reg max_burst;
  987. + struct hantro_reg clk_gate;
  988. + struct hantro_reg out_swap32;
  989. + struct hantro_reg out_endian;
  990. + struct hantro_reg out_luma_base;
  991. + struct hantro_reg input_width;
  992. + struct hantro_reg input_height;
  993. + struct hantro_reg output_width;
  994. + struct hantro_reg output_height;
  995. + struct hantro_reg input_fmt;
  996. + struct hantro_reg output_fmt;
  997. + struct hantro_reg orig_width;
  998. + struct hantro_reg display_width;
  999. +};
  1000. +
  1001. /* Logging helpers */
  1002.  
  1003. /**
  1004. @@ -352,16 +377,30 @@
  1005. return val;
  1006. }
  1007.  
  1008. -static inline void hantro_reg_write(struct hantro_dev *vpu,
  1009. - const struct hantro_reg *reg,
  1010. - u32 val)
  1011. +static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
  1012. + const struct hantro_reg *reg,
  1013. + u32 val)
  1014. {
  1015. u32 v;
  1016.  
  1017. v = vdpu_read(vpu, reg->base);
  1018. v &= ~(reg->mask << reg->shift);
  1019. v |= ((val & reg->mask) << reg->shift);
  1020. - vdpu_write_relaxed(vpu, v, reg->base);
  1021. + return v;
  1022. +}
  1023. +
  1024. +static inline void hantro_reg_write(struct hantro_dev *vpu,
  1025. + const struct hantro_reg *reg,
  1026. + u32 val)
  1027. +{
  1028. + vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
  1029. +}
  1030. +
  1031. +static inline void hantro_reg_write_s(struct hantro_dev *vpu,
  1032. + const struct hantro_reg *reg,
  1033. + u32 val)
  1034. +{
  1035. + vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
  1036. }
  1037.  
  1038. bool hantro_is_encoder_ctx(const struct hantro_ctx *ctx);
  1039. @@ -381,4 +420,23 @@
  1040. return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1041. }
  1042.  
  1043. +static inline bool
  1044. +hantro_needs_postproc(struct hantro_ctx *ctx, const struct hantro_fmt *fmt)
  1045. +{
  1046. + return !hantro_is_encoder_ctx(ctx) && fmt->fourcc != V4L2_PIX_FMT_NV12;
  1047. +}
  1048. +
  1049. +static inline dma_addr_t
  1050. +hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
  1051. +{
  1052. + if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
  1053. + return ctx->postproc.dec_q[vb->index].dma;
  1054. + return vb2_dma_contig_plane_dma_addr(vb, 0);
  1055. +}
  1056. +
  1057. +void hantro_postproc_disable(struct hantro_ctx *ctx);
  1058. +void hantro_postproc_enable(struct hantro_ctx *ctx);
  1059. +void hantro_postproc_free(struct hantro_ctx *ctx);
  1060. +int hantro_postproc_alloc(struct hantro_ctx *ctx);
  1061. +
  1062. #endif /* HANTRO_H_ */
  1063. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_h1_jpeg_enc.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_h1_jpeg_enc.c
  1064. --- linux-5.5/drivers/staging/media/hantro/hantro_h1_jpeg_enc.c 2020-01-26 16:23:03.000000000 -0800
  1065. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_h1_jpeg_enc.c 2020-02-14 22:59:08.117542364 -0800
  1066. @@ -87,7 +87,7 @@
  1067. src_buf = hantro_get_src_buf(ctx);
  1068. dst_buf = hantro_get_dst_buf(ctx);
  1069.  
  1070. - hantro_prepare_run(ctx);
  1071. + hantro_start_prepare_run(ctx);
  1072.  
  1073. memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
  1074. jpeg_ctx.buffer = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
  1075. @@ -122,7 +122,7 @@
  1076. | H1_REG_ENC_PIC_INTRA
  1077. | H1_REG_ENC_CTRL_EN_BIT;
  1078.  
  1079. - hantro_finish_run(ctx);
  1080. + hantro_end_prepare_run(ctx);
  1081.  
  1082. vepu_write(vpu, reg, H1_REG_ENC_CTRL);
  1083. }
  1084. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_h264.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_h264.c
  1085. --- linux-5.5/drivers/staging/media/hantro/hantro_h264.c 2020-01-26 16:23:03.000000000 -0800
  1086. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_h264.c 2020-02-14 22:59:08.117542364 -0800
  1087. @@ -225,17 +225,65 @@
  1088. {
  1089. const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
  1090. const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
  1091. + const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
  1092. struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
  1093. const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
  1094. + u32 dpb_longterm = 0;
  1095. + u32 dpb_valid = 0;
  1096. int i;
  1097.  
  1098. + /*
  1099. + * Set up bit maps of valid and long term DPBs.
  1100. + * NOTE: The bits are reversed, i.e. MSb is DPB 0.
  1101. + */
  1102. + if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || (slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
  1103. + for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
  1104. + // check for correct reference use
  1105. + u32 flag = (i & 0x1) ? V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM : V4L2_H264_DPB_ENTRY_FLAG_REF_TOP;
  1106. + if (dpb[i / 2].flags & flag)
  1107. + dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
  1108. +
  1109. + if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
  1110. + dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
  1111. + }
  1112. +
  1113. + ctx->h264_dec.dpb_valid = dpb_valid;
  1114. + ctx->h264_dec.dpb_longterm = dpb_longterm;
  1115. + } else {
  1116. + for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
  1117. + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
  1118. + dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
  1119. +
  1120. + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
  1121. + dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
  1122. + }
  1123. +
  1124. + ctx->h264_dec.dpb_valid = dpb_valid << 16;
  1125. + ctx->h264_dec.dpb_longterm = dpb_longterm << 16;
  1126. + }
  1127. +
  1128. for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
  1129. - tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
  1130. - tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
  1131. + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
  1132. + tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
  1133. + tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
  1134. + } else {
  1135. + tbl->poc[i * 2] = 0;
  1136. + tbl->poc[i * 2 + 1] = 0;
  1137. + }
  1138. }
  1139.  
  1140. - tbl->poc[32] = dec_param->top_field_order_cnt;
  1141. - tbl->poc[33] = dec_param->bottom_field_order_cnt;
  1142. + if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || !(slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
  1143. + if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
  1144. + tbl->poc[32] = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
  1145. + dec_param->bottom_field_order_cnt :
  1146. + dec_param->top_field_order_cnt;
  1147. + else
  1148. + tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt);
  1149. + tbl->poc[33] = 0;
  1150. + } else {
  1151. + tbl->poc[32] = dec_param->top_field_order_cnt;
  1152. + tbl->poc[33] = dec_param->bottom_field_order_cnt;
  1153. + }
  1154.  
  1155. reorder_scaling_list(ctx);
  1156. }
  1157. @@ -249,21 +297,6 @@
  1158. u8 num_valid;
  1159. };
  1160.  
  1161. -static s32 get_poc(enum v4l2_field field, s32 top_field_order_cnt,
  1162. - s32 bottom_field_order_cnt)
  1163. -{
  1164. - switch (field) {
  1165. - case V4L2_FIELD_TOP:
  1166. - return top_field_order_cnt;
  1167. - case V4L2_FIELD_BOTTOM:
  1168. - return bottom_field_order_cnt;
  1169. - default:
  1170. - break;
  1171. - }
  1172. -
  1173. - return min(top_field_order_cnt, bottom_field_order_cnt);
  1174. -}
  1175. -
  1176. static void
  1177. init_reflist_builder(struct hantro_ctx *ctx,
  1178. struct hantro_h264_reflist_builder *b)
  1179. @@ -271,9 +304,7 @@
  1180. const struct v4l2_ctrl_h264_slice_params *slice_params;
  1181. const struct v4l2_ctrl_h264_decode_params *dec_param;
  1182. const struct v4l2_ctrl_h264_sps *sps;
  1183. - struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx);
  1184. const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
  1185. - struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
  1186. int cur_frame_num, max_frame_num;
  1187. unsigned int i;
  1188.  
  1189. @@ -285,21 +316,15 @@
  1190.  
  1191. memset(b, 0, sizeof(*b));
  1192. b->dpb = dpb;
  1193. - b->curpoc = get_poc(buf->field, dec_param->top_field_order_cnt,
  1194. - dec_param->bottom_field_order_cnt);
  1195. + b->curpoc = (slice_params->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
  1196. + dec_param->bottom_field_order_cnt :
  1197. + dec_param->top_field_order_cnt;
  1198.  
  1199. for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) {
  1200. - int buf_idx;
  1201. -
  1202. - if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
  1203. + u32 ref_flag = dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME;
  1204. + if (!ref_flag)
  1205. continue;
  1206.  
  1207. - buf_idx = vb2_find_timestamp(cap_q, dpb[i].reference_ts, 0);
  1208. - if (buf_idx < 0)
  1209. - continue;
  1210. -
  1211. - buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx));
  1212. -
  1213. /*
  1214. * Handle frame_num wraparound as described in section
  1215. * '8.2.4.1 Decoding process for picture numbers' of the spec.
  1216. @@ -311,8 +336,13 @@
  1217. else
  1218. b->frame_nums[i] = dpb[i].frame_num;
  1219.  
  1220. - b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt,
  1221. - dpb[i].bottom_field_order_cnt);
  1222. + if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME)
  1223. + b->pocs[i] = min(dpb[i].bottom_field_order_cnt, dpb[i].top_field_order_cnt);
  1224. + else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM)
  1225. + b->pocs[i] = dpb[i].bottom_field_order_cnt;
  1226. + else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_TOP)
  1227. + b->pocs[i] = dpb[i].top_field_order_cnt;
  1228. +
  1229. b->unordered_reflist[b->num_valid] = i;
  1230. b->num_valid++;
  1231. }
  1232. @@ -466,8 +496,7 @@
  1233. static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a,
  1234. const struct v4l2_h264_dpb_entry *b)
  1235. {
  1236. - return a->top_field_order_cnt == b->top_field_order_cnt &&
  1237. - a->bottom_field_order_cnt == b->bottom_field_order_cnt;
  1238. + return a->reference_ts == b->reference_ts;
  1239. }
  1240.  
  1241. static void update_dpb(struct hantro_ctx *ctx)
  1242. @@ -481,13 +510,13 @@
  1243.  
  1244. /* Disable all entries by default. */
  1245. for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++)
  1246. - ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE;
  1247. + ctx->h264_dec.dpb[i].flags = 0;
  1248.  
  1249. /* Try to match new DPB entries with existing ones by their POCs. */
  1250. for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) {
  1251. const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i];
  1252.  
  1253. - if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
  1254. + if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))
  1255. continue;
  1256.  
  1257. /*
  1258. @@ -498,8 +527,7 @@
  1259. struct v4l2_h264_dpb_entry *cdpb;
  1260.  
  1261. cdpb = &ctx->h264_dec.dpb[j];
  1262. - if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ||
  1263. - !dpb_entry_match(cdpb, ndpb))
  1264. + if (!dpb_entry_match(cdpb, ndpb))
  1265. continue;
  1266.  
  1267. *cdpb = *ndpb;
  1268. @@ -535,7 +563,11 @@
  1269. unsigned int dpb_idx)
  1270. {
  1271. struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
  1272. + const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode;
  1273. + const struct v4l2_ctrl_h264_slice_params *slices = ctx->h264_dec.ctrls.slices;
  1274. dma_addr_t dma_addr = 0;
  1275. + s32 cur_poc;
  1276. + u32 flags;
  1277.  
  1278. if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
  1279. dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts);
  1280. @@ -553,7 +585,29 @@
  1281. dma_addr = vb2_dma_contig_plane_dma_addr(buf, 0);
  1282. }
  1283.  
  1284. - return dma_addr;
  1285. + cur_poc = slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD ?
  1286. + dec_param->bottom_field_order_cnt :
  1287. + dec_param->top_field_order_cnt;
  1288. + flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE ? 0x2 : 0;
  1289. + flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) <
  1290. + abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ?
  1291. + 0x1 : 0;
  1292. +
  1293. + return dma_addr | flags;
  1294. +}
  1295. +
  1296. +u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx,
  1297. + unsigned int dpb_idx)
  1298. +{
  1299. + const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx];
  1300. +
  1301. + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
  1302. + return 0;
  1303. +
  1304. + if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
  1305. + return dpb->pic_num;
  1306. +
  1307. + return dpb->frame_num;
  1308. }
  1309.  
  1310. int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx)
  1311. @@ -562,7 +616,7 @@
  1312. struct hantro_h264_dec_ctrls *ctrls = &h264_ctx->ctrls;
  1313. struct hantro_h264_reflist_builder reflist_builder;
  1314.  
  1315. - hantro_prepare_run(ctx);
  1316. + hantro_start_prepare_run(ctx);
  1317.  
  1318. ctrls->scaling =
  1319. hantro_get_ctrl(ctx, V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX);
  1320. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_hw.h linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_hw.h
  1321. --- linux-5.5/drivers/staging/media/hantro/hantro_hw.h 2020-01-26 16:23:03.000000000 -0800
  1322. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_hw.h 2020-02-14 22:59:08.117542364 -0800
  1323. @@ -28,11 +28,13 @@
  1324. * @cpu: CPU pointer to the buffer.
  1325. * @dma: DMA address of the buffer.
  1326. * @size: Size of the buffer.
  1327. + * @attrs: Attributes of the DMA mapping.
  1328. */
  1329. struct hantro_aux_buf {
  1330. void *cpu;
  1331. dma_addr_t dma;
  1332. size_t size;
  1333. + unsigned long attrs;
  1334. };
  1335.  
  1336. /**
  1337. @@ -86,6 +88,8 @@
  1338. struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
  1339. struct hantro_h264_dec_reflists reflists;
  1340. struct hantro_h264_dec_ctrls ctrls;
  1341. + u32 dpb_longterm;
  1342. + u32 dpb_valid;
  1343. };
  1344.  
  1345. /**
  1346. @@ -107,6 +111,15 @@
  1347. };
  1348.  
  1349. /**
  1350. + * struct hantro_postproc_ctx
  1351. + *
  1352. + * @dec_q: References buffers, in decoder format.
  1353. + */
  1354. +struct hantro_postproc_ctx {
  1355. + struct hantro_aux_buf dec_q[VB2_MAX_FRAME];
  1356. +};
  1357. +
  1358. +/**
  1359. * struct hantro_codec_ops - codec mode specific operations
  1360. *
  1361. * @init: If needed, can be used for initialization.
  1362. @@ -141,14 +154,16 @@
  1363. extern const struct hantro_variant rk3328_vpu_variant;
  1364. extern const struct hantro_variant rk3288_vpu_variant;
  1365.  
  1366. +extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
  1367. +
  1368. extern const u32 hantro_vp8_dec_mc_filter[8][6];
  1369.  
  1370. void hantro_watchdog(struct work_struct *work);
  1371. void hantro_run(struct hantro_ctx *ctx);
  1372. void hantro_irq_done(struct hantro_dev *vpu, unsigned int bytesused,
  1373. enum vb2_buffer_state result);
  1374. -void hantro_prepare_run(struct hantro_ctx *ctx);
  1375. -void hantro_finish_run(struct hantro_ctx *ctx);
  1376. +void hantro_start_prepare_run(struct hantro_ctx *ctx);
  1377. +void hantro_end_prepare_run(struct hantro_ctx *ctx);
  1378.  
  1379. void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
  1380. void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx);
  1381. @@ -157,8 +172,11 @@
  1382.  
  1383. dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
  1384. unsigned int dpb_idx);
  1385. +u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx,
  1386. + unsigned int dpb_idx);
  1387. int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx);
  1388. void hantro_g1_h264_dec_run(struct hantro_ctx *ctx);
  1389. +void rk3399_vpu_h264_dec_run(struct hantro_ctx *ctx);
  1390. int hantro_h264_dec_init(struct hantro_ctx *ctx);
  1391. void hantro_h264_dec_exit(struct hantro_ctx *ctx);
  1392.  
  1393. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_postproc.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_postproc.c
  1394. --- linux-5.5/drivers/staging/media/hantro/hantro_postproc.c 1969-12-31 16:00:00.000000000 -0800
  1395. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_postproc.c 2020-02-14 22:59:08.117542364 -0800
  1396. @@ -0,0 +1,148 @@
  1397. +// SPDX-License-Identifier: GPL-2.0
  1398. +/*
  1399. + * Hantro G1 post-processor support
  1400. + *
  1401. + * Copyright (C) 2019 Collabora, Ltd.
  1402. + */
  1403. +
  1404. +#include <linux/dma-mapping.h>
  1405. +#include <linux/types.h>
  1406. +
  1407. +#include "hantro.h"
  1408. +#include "hantro_hw.h"
  1409. +#include "hantro_g1_regs.h"
  1410. +
  1411. +#define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
  1412. +{ \
  1413. + hantro_reg_write((vpu), \
  1414. + &((vpu)->variant->postproc_regs->reg_name), \
  1415. + (val)); \
  1416. +}
  1417. +
  1418. +#define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \
  1419. +{ \
  1420. + hantro_reg_write_s((vpu), \
  1421. + &((vpu)->variant->postproc_regs->reg_name), \
  1422. + (val)); \
  1423. +}
  1424. +
  1425. +#define VPU_PP_IN_YUYV 0x0
  1426. +#define VPU_PP_IN_NV12 0x1
  1427. +#define VPU_PP_IN_YUV420 0x2
  1428. +#define VPU_PP_IN_YUV240_TILED 0x5
  1429. +#define VPU_PP_OUT_RGB 0x0
  1430. +#define VPU_PP_OUT_YUYV 0x3
  1431. +
  1432. +const struct hantro_postproc_regs hantro_g1_postproc_regs = {
  1433. + .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
  1434. + .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
  1435. + .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
  1436. + .out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1},
  1437. + .out_endian = {G1_REG_PP_DEV_CONFIG, 6, 0x1},
  1438. + .out_luma_base = {G1_REG_PP_OUT_LUMA_BASE, 0, 0xffffffff},
  1439. + .input_width = {G1_REG_PP_INPUT_SIZE, 0, 0x1ff},
  1440. + .input_height = {G1_REG_PP_INPUT_SIZE, 9, 0x1ff},
  1441. + .output_width = {G1_REG_PP_CONTROL, 4, 0x7ff},
  1442. + .output_height = {G1_REG_PP_CONTROL, 15, 0x7ff},
  1443. + .input_fmt = {G1_REG_PP_CONTROL, 29, 0x7},
  1444. + .output_fmt = {G1_REG_PP_CONTROL, 26, 0x7},
  1445. + .orig_width = {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff},
  1446. + .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff},
  1447. +};
  1448. +
  1449. +void hantro_postproc_enable(struct hantro_ctx *ctx)
  1450. +{
  1451. + struct hantro_dev *vpu = ctx->dev;
  1452. + struct vb2_v4l2_buffer *dst_buf;
  1453. + u32 src_pp_fmt, dst_pp_fmt;
  1454. + dma_addr_t dst_dma;
  1455. +
  1456. + if (!vpu->variant->postproc_regs)
  1457. + return;
  1458. +
  1459. + /* Turn on pipeline mode. Must be done first. */
  1460. + HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
  1461. +
  1462. + src_pp_fmt = VPU_PP_IN_NV12;
  1463. +
  1464. + switch (ctx->vpu_dst_fmt->fourcc) {
  1465. + case V4L2_PIX_FMT_YUYV:
  1466. + dst_pp_fmt = VPU_PP_OUT_YUYV;
  1467. + break;
  1468. + default:
  1469. + WARN(1, "output format %d not supported by the post-processor, this wasn't expected.",
  1470. + ctx->vpu_dst_fmt->fourcc);
  1471. + dst_pp_fmt = 0;
  1472. + break;
  1473. + }
  1474. +
  1475. + dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1476. + dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
  1477. +
  1478. + HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);
  1479. + HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);
  1480. + HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);
  1481. + HANTRO_PP_REG_WRITE(vpu, max_burst, 16);
  1482. + HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma);
  1483. + HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width));
  1484. + HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height));
  1485. + HANTRO_PP_REG_WRITE(vpu, input_fmt, src_pp_fmt);
  1486. + HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt);
  1487. + HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width);
  1488. + HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);
  1489. + HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));
  1490. + HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
  1491. +}
  1492. +
  1493. +void hantro_postproc_free(struct hantro_ctx *ctx)
  1494. +{
  1495. + struct hantro_dev *vpu = ctx->dev;
  1496. + unsigned int i;
  1497. +
  1498. + for (i = 0; i < VB2_MAX_FRAME; ++i) {
  1499. + struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
  1500. +
  1501. + if (priv->cpu) {
  1502. + dma_free_attrs(vpu->dev, priv->size, priv->cpu,
  1503. + priv->dma, priv->attrs);
  1504. + priv->cpu = NULL;
  1505. + }
  1506. + }
  1507. +}
  1508. +
  1509. +int hantro_postproc_alloc(struct hantro_ctx *ctx)
  1510. +{
  1511. + struct hantro_dev *vpu = ctx->dev;
  1512. + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
  1513. + struct vb2_queue *cap_queue = &m2m_ctx->cap_q_ctx.q;
  1514. + unsigned int num_buffers = cap_queue->num_buffers;
  1515. + unsigned int i, buf_size;
  1516. +
  1517. + buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage;
  1518. +
  1519. + for (i = 0; i < num_buffers; ++i) {
  1520. + struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
  1521. +
  1522. + /*
  1523. + * The buffers on this queue are meant as intermediate
  1524. + * buffers for the decoder, so no mapping is needed.
  1525. + */
  1526. + priv->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
  1527. + priv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &priv->dma,
  1528. + GFP_KERNEL, priv->attrs);
  1529. + if (!priv->cpu)
  1530. + return -ENOMEM;
  1531. + priv->size = buf_size;
  1532. + }
  1533. + return 0;
  1534. +}
  1535. +
  1536. +void hantro_postproc_disable(struct hantro_ctx *ctx)
  1537. +{
  1538. + struct hantro_dev *vpu = ctx->dev;
  1539. +
  1540. + if (!vpu->variant->postproc_regs)
  1541. + return;
  1542. +
  1543. + HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
  1544. +}
  1545. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_v4l2.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_v4l2.c
  1546. --- linux-5.5/drivers/staging/media/hantro/hantro_v4l2.c 2020-01-26 16:23:03.000000000 -0800
  1547. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_v4l2.c 2020-02-14 22:59:08.117542364 -0800
  1548. @@ -47,11 +47,30 @@
  1549. }
  1550.  
  1551. static const struct hantro_fmt *
  1552. -hantro_find_format(const struct hantro_fmt *formats, unsigned int num_fmts,
  1553. - u32 fourcc)
  1554. +hantro_get_postproc_formats(const struct hantro_ctx *ctx,
  1555. + unsigned int *num_fmts)
  1556. {
  1557. - unsigned int i;
  1558. + if (hantro_is_encoder_ctx(ctx)) {
  1559. + *num_fmts = 0;
  1560. + return NULL;
  1561. + }
  1562. +
  1563. + *num_fmts = ctx->dev->variant->num_postproc_fmts;
  1564. + return ctx->dev->variant->postproc_fmts;
  1565. +}
  1566. +
  1567. +static const struct hantro_fmt *
  1568. +hantro_find_format(const struct hantro_ctx *ctx, u32 fourcc)
  1569. +{
  1570. + const struct hantro_fmt *formats;
  1571. + unsigned int i, num_fmts;
  1572. +
  1573. + formats = hantro_get_formats(ctx, &num_fmts);
  1574. + for (i = 0; i < num_fmts; i++)
  1575. + if (formats[i].fourcc == fourcc)
  1576. + return &formats[i];
  1577.  
  1578. + formats = hantro_get_postproc_formats(ctx, &num_fmts);
  1579. for (i = 0; i < num_fmts; i++)
  1580. if (formats[i].fourcc == fourcc)
  1581. return &formats[i];
  1582. @@ -59,11 +78,12 @@
  1583. }
  1584.  
  1585. static const struct hantro_fmt *
  1586. -hantro_get_default_fmt(const struct hantro_fmt *formats, unsigned int num_fmts,
  1587. - bool bitstream)
  1588. +hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream)
  1589. {
  1590. - unsigned int i;
  1591. + const struct hantro_fmt *formats;
  1592. + unsigned int i, num_fmts;
  1593.  
  1594. + formats = hantro_get_formats(ctx, &num_fmts);
  1595. for (i = 0; i < num_fmts; i++) {
  1596. if (bitstream == (formats[i].codec_mode !=
  1597. HANTRO_MODE_NONE))
  1598. @@ -89,8 +109,7 @@
  1599. struct v4l2_frmsizeenum *fsize)
  1600. {
  1601. struct hantro_ctx *ctx = fh_to_ctx(priv);
  1602. - const struct hantro_fmt *formats, *fmt;
  1603. - unsigned int num_fmts;
  1604. + const struct hantro_fmt *fmt;
  1605.  
  1606. if (fsize->index != 0) {
  1607. vpu_debug(0, "invalid frame size index (expected 0, got %d)\n",
  1608. @@ -98,8 +117,7 @@
  1609. return -EINVAL;
  1610. }
  1611.  
  1612. - formats = hantro_get_formats(ctx, &num_fmts);
  1613. - fmt = hantro_find_format(formats, num_fmts, fsize->pixel_format);
  1614. + fmt = hantro_find_format(ctx, fsize->pixel_format);
  1615. if (!fmt) {
  1616. vpu_debug(0, "unsupported bitstream format (%08x)\n",
  1617. fsize->pixel_format);
  1618. @@ -150,6 +168,24 @@
  1619. }
  1620. ++j;
  1621. }
  1622. +
  1623. + /*
  1624. + * Enumerate post-processed formats. As per the specification,
  1625. + * we enumerated these formats after natively decoded formats
  1626. + * as a hint for applications on what's the preferred fomat.
  1627. + */
  1628. + if (!capture)
  1629. + return -EINVAL;
  1630. + formats = hantro_get_postproc_formats(ctx, &num_fmts);
  1631. + for (i = 0; i < num_fmts; i++) {
  1632. + if (j == f->index) {
  1633. + fmt = &formats[i];
  1634. + f->pixelformat = fmt->fourcc;
  1635. + return 0;
  1636. + }
  1637. + ++j;
  1638. + }
  1639. +
  1640. return -EINVAL;
  1641. }
  1642.  
  1643. @@ -196,8 +232,7 @@
  1644. {
  1645. struct hantro_ctx *ctx = fh_to_ctx(priv);
  1646. struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
  1647. - const struct hantro_fmt *formats, *fmt, *vpu_fmt;
  1648. - unsigned int num_fmts;
  1649. + const struct hantro_fmt *fmt, *vpu_fmt;
  1650. bool coded;
  1651.  
  1652. coded = capture == hantro_is_encoder_ctx(ctx);
  1653. @@ -208,10 +243,9 @@
  1654. (pix_mp->pixelformat >> 16) & 0x7f,
  1655. (pix_mp->pixelformat >> 24) & 0x7f);
  1656.  
  1657. - formats = hantro_get_formats(ctx, &num_fmts);
  1658. - fmt = hantro_find_format(formats, num_fmts, pix_mp->pixelformat);
  1659. + fmt = hantro_find_format(ctx, pix_mp->pixelformat);
  1660. if (!fmt) {
  1661. - fmt = hantro_get_default_fmt(formats, num_fmts, coded);
  1662. + fmt = hantro_get_default_fmt(ctx, coded);
  1663. f->fmt.pix_mp.pixelformat = fmt->fourcc;
  1664. }
  1665.  
  1666. @@ -246,7 +280,7 @@
  1667. *
  1668. * The H264 decoder needs extra space on the output buffers
  1669. * to store motion vectors. This is needed for reference
  1670. - * frames.
  1671. + * frames and only if the format is non-post-processed NV12.
  1672. *
  1673. * Memory layout is as follow:
  1674. *
  1675. @@ -260,7 +294,8 @@
  1676. * | MC sync 32 bytes |
  1677. * +---------------------------+
  1678. */
  1679. - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
  1680. + if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE &&
  1681. + !hantro_needs_postproc(ctx, fmt))
  1682. pix_mp->plane_fmt[0].sizeimage +=
  1683. 64 * MB_WIDTH(pix_mp->width) *
  1684. MB_WIDTH(pix_mp->height) + 32;
  1685. @@ -306,12 +341,10 @@
  1686. static void
  1687. hantro_reset_encoded_fmt(struct hantro_ctx *ctx)
  1688. {
  1689. - const struct hantro_fmt *vpu_fmt, *formats;
  1690. + const struct hantro_fmt *vpu_fmt;
  1691. struct v4l2_pix_format_mplane *fmt;
  1692. - unsigned int num_fmts;
  1693.  
  1694. - formats = hantro_get_formats(ctx, &num_fmts);
  1695. - vpu_fmt = hantro_get_default_fmt(formats, num_fmts, true);
  1696. + vpu_fmt = hantro_get_default_fmt(ctx, true);
  1697.  
  1698. if (hantro_is_encoder_ctx(ctx)) {
  1699. ctx->vpu_dst_fmt = vpu_fmt;
  1700. @@ -332,12 +365,10 @@
  1701. static void
  1702. hantro_reset_raw_fmt(struct hantro_ctx *ctx)
  1703. {
  1704. - const struct hantro_fmt *raw_vpu_fmt, *formats;
  1705. + const struct hantro_fmt *raw_vpu_fmt;
  1706. struct v4l2_pix_format_mplane *raw_fmt, *encoded_fmt;
  1707. - unsigned int num_fmts;
  1708.  
  1709. - formats = hantro_get_formats(ctx, &num_fmts);
  1710. - raw_vpu_fmt = hantro_get_default_fmt(formats, num_fmts, false);
  1711. + raw_vpu_fmt = hantro_get_default_fmt(ctx, false);
  1712.  
  1713. if (hantro_is_encoder_ctx(ctx)) {
  1714. ctx->vpu_src_fmt = raw_vpu_fmt;
  1715. @@ -384,8 +415,6 @@
  1716. struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
  1717. struct hantro_ctx *ctx = fh_to_ctx(priv);
  1718. struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
  1719. - const struct hantro_fmt *formats;
  1720. - unsigned int num_fmts;
  1721. int ret;
  1722.  
  1723. ret = vidioc_try_fmt_out_mplane(file, priv, f);
  1724. @@ -421,9 +450,7 @@
  1725. return -EBUSY;
  1726. }
  1727.  
  1728. - formats = hantro_get_formats(ctx, &num_fmts);
  1729. - ctx->vpu_src_fmt = hantro_find_format(formats, num_fmts,
  1730. - pix_mp->pixelformat);
  1731. + ctx->vpu_src_fmt = hantro_find_format(ctx, pix_mp->pixelformat);
  1732. ctx->src_fmt = *pix_mp;
  1733.  
  1734. /*
  1735. @@ -457,9 +484,7 @@
  1736. {
  1737. struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
  1738. struct hantro_ctx *ctx = fh_to_ctx(priv);
  1739. - const struct hantro_fmt *formats;
  1740. struct vb2_queue *vq;
  1741. - unsigned int num_fmts;
  1742. int ret;
  1743.  
  1744. /* Change not allowed if queue is busy. */
  1745. @@ -488,9 +513,7 @@
  1746. if (ret)
  1747. return ret;
  1748.  
  1749. - formats = hantro_get_formats(ctx, &num_fmts);
  1750. - ctx->vpu_dst_fmt = hantro_find_format(formats, num_fmts,
  1751. - pix_mp->pixelformat);
  1752. + ctx->vpu_dst_fmt = hantro_find_format(ctx, pix_mp->pixelformat);
  1753. ctx->dst_fmt = *pix_mp;
  1754.  
  1755. /*
  1756. @@ -650,10 +673,23 @@
  1757.  
  1758. vpu_debug(4, "Codec mode = %d\n", codec_mode);
  1759. ctx->codec_ops = &ctx->dev->variant->codec_ops[codec_mode];
  1760. - if (ctx->codec_ops->init)
  1761. + if (ctx->codec_ops->init) {
  1762. ret = ctx->codec_ops->init(ctx);
  1763. + if (ret)
  1764. + return ret;
  1765. + }
  1766. +
  1767. + if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) {
  1768. + ret = hantro_postproc_alloc(ctx);
  1769. + if (ret)
  1770. + goto err_codec_exit;
  1771. + }
  1772. }
  1773. + return ret;
  1774.  
  1775. +err_codec_exit:
  1776. + if (ctx->codec_ops->exit)
  1777. + ctx->codec_ops->exit(ctx);
  1778. return ret;
  1779. }
  1780.  
  1781. @@ -680,6 +716,7 @@
  1782. struct hantro_ctx *ctx = vb2_get_drv_priv(q);
  1783.  
  1784. if (hantro_vq_is_coded(q)) {
  1785. + hantro_postproc_free(ctx);
  1786. if (ctx->codec_ops && ctx->codec_ops->exit)
  1787. ctx->codec_ops->exit(ctx);
  1788. }
  1789. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/hantro_vp8.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_vp8.c
  1790. --- linux-5.5/drivers/staging/media/hantro/hantro_vp8.c 2020-01-26 16:23:03.000000000 -0800
  1791. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/hantro_vp8.c 2020-02-14 22:59:08.117542364 -0800
  1792. @@ -151,8 +151,8 @@
  1793. int ret;
  1794.  
  1795. /* segment map table size calculation */
  1796. - mb_width = DIV_ROUND_UP(ctx->dst_fmt.width, 16);
  1797. - mb_height = DIV_ROUND_UP(ctx->dst_fmt.height, 16);
  1798. + mb_width = MB_WIDTH(ctx->src_fmt.width);
  1799. + mb_height = MB_HEIGHT(ctx->src_fmt.height);
  1800. segment_map_size = round_up(DIV_ROUND_UP(mb_width * mb_height, 4), 64);
  1801.  
  1802. /*
  1803. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/Makefile linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/Makefile
  1804. --- linux-5.5/drivers/staging/media/hantro/Makefile 2020-01-26 16:23:03.000000000 -0800
  1805. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/Makefile 2020-02-14 22:59:08.117542364 -0800
  1806. @@ -3,11 +3,13 @@
  1807. hantro-vpu-y += \
  1808. hantro_drv.o \
  1809. hantro_v4l2.o \
  1810. + hantro_postproc.o \
  1811. hantro_h1_jpeg_enc.o \
  1812. hantro_g1_h264_dec.o \
  1813. hantro_g1_mpeg2_dec.o \
  1814. hantro_g1_vp8_dec.o \
  1815. rk3399_vpu_hw_jpeg_enc.o \
  1816. + rk3399_vpu_hw_h264_dec.o \
  1817. rk3399_vpu_hw_mpeg2_dec.o \
  1818. rk3399_vpu_hw_vp8_dec.o \
  1819. hantro_jpeg.o \
  1820. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/rk3288_vpu_hw.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3288_vpu_hw.c
  1821. --- linux-5.5/drivers/staging/media/hantro/rk3288_vpu_hw.c 2020-01-26 16:23:03.000000000 -0800
  1822. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3288_vpu_hw.c 2020-02-14 22:59:08.117542364 -0800
  1823. @@ -56,6 +56,13 @@
  1824. },
  1825. };
  1826.  
  1827. +static const struct hantro_fmt rk3288_vpu_postproc_fmts[] = {
  1828. + {
  1829. + .fourcc = V4L2_PIX_FMT_YUYV,
  1830. + .codec_mode = HANTRO_MODE_NONE,
  1831. + },
  1832. +};
  1833. +
  1834. static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
  1835. {
  1836. .fourcc = V4L2_PIX_FMT_NV12,
  1837. @@ -215,6 +222,9 @@
  1838. .dec_offset = 0x400,
  1839. .dec_fmts = rk3288_vpu_dec_fmts,
  1840. .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
  1841. + .postproc_fmts = rk3288_vpu_postproc_fmts,
  1842. + .num_postproc_fmts = ARRAY_SIZE(rk3288_vpu_postproc_fmts),
  1843. + .postproc_regs = &hantro_g1_postproc_regs,
  1844. .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
  1845. HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
  1846. .codec_ops = rk3288_vpu_codec_ops,
  1847. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw.c
  1848. --- linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw.c 2020-01-26 16:23:03.000000000 -0800
  1849. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw.c 2020-02-14 22:59:08.117542364 -0800
  1850. @@ -61,6 +61,19 @@
  1851. .codec_mode = HANTRO_MODE_NONE,
  1852. },
  1853. {
  1854. + .fourcc = V4L2_PIX_FMT_H264_SLICE,
  1855. + .codec_mode = HANTRO_MODE_H264_DEC,
  1856. + .max_depth = 2,
  1857. + .frmsize = {
  1858. + .min_width = 48,
  1859. + .max_width = 1920,
  1860. + .step_width = MB_DIM,
  1861. + .min_height = 48,
  1862. + .max_height = 1088,
  1863. + .step_height = MB_DIM,
  1864. + },
  1865. + },
  1866. + {
  1867. .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
  1868. .codec_mode = HANTRO_MODE_MPEG2_DEC,
  1869. .max_depth = 2,
  1870. @@ -161,6 +174,12 @@
  1871. .init = hantro_jpeg_enc_init,
  1872. .exit = hantro_jpeg_enc_exit,
  1873. },
  1874. + [HANTRO_MODE_H264_DEC] = {
  1875. + .run = rk3399_vpu_h264_dec_run,
  1876. + .reset = rk3399_vpu_dec_reset,
  1877. + .init = hantro_h264_dec_init,
  1878. + .exit = hantro_h264_dec_exit,
  1879. + },
  1880. [HANTRO_MODE_MPEG2_DEC] = {
  1881. .run = rk3399_vpu_mpeg2_dec_run,
  1882. .reset = rk3399_vpu_dec_reset,
  1883. @@ -196,7 +215,7 @@
  1884. .dec_fmts = rk3399_vpu_dec_fmts,
  1885. .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
  1886. .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
  1887. - HANTRO_VP8_DECODER,
  1888. + HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
  1889. .codec_ops = rk3399_vpu_codec_ops,
  1890. .irqs = rk3399_irqs,
  1891. .num_irqs = ARRAY_SIZE(rk3399_irqs),
  1892. @@ -213,7 +232,8 @@
  1893. .dec_offset = 0x400,
  1894. .dec_fmts = rk3399_vpu_dec_fmts,
  1895. .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
  1896. - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
  1897. + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
  1898. + HANTRO_H264_DECODER,
  1899. .codec_ops = rk3399_vpu_codec_ops,
  1900. .irqs = rk3328_irqs,
  1901. .num_irqs = ARRAY_SIZE(rk3328_irqs),
  1902. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c
  1903. --- linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c 1969-12-31 16:00:00.000000000 -0800
  1904. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_h264_dec.c 2020-02-14 22:59:08.117542364 -0800
  1905. @@ -0,0 +1,493 @@
  1906. +// SPDX-License-Identifier: GPL-2.0
  1907. +/*
  1908. + * Hantro VPU codec driver
  1909. + *
  1910. + * Copyright (c) 2014 Rockchip Electronics Co., Ltd.
  1911. + * Hertz Wong <hertz.wong@rock-chips.com>
  1912. + * Herman Chen <herman.chen@rock-chips.com>
  1913. + *
  1914. + * Copyright (C) 2014 Google, Inc.
  1915. + * Tomasz Figa <tfiga@chromium.org>
  1916. + */
  1917. +
  1918. +#include <linux/types.h>
  1919. +#include <linux/sort.h>
  1920. +
  1921. +#include <media/v4l2-mem2mem.h>
  1922. +
  1923. +#include "hantro_hw.h"
  1924. +#include "hantro_v4l2.h"
  1925. +
  1926. +#define VDPU_SWREG(nr) ((nr) * 4)
  1927. +
  1928. +#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63)
  1929. +#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64)
  1930. +#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61)
  1931. +#define VDPU_REG_DIR_MV_BASE VDPU_SWREG(62)
  1932. +#define VDPU_REG_REFER0_BASE VDPU_SWREG(84)
  1933. +#define VDPU_REG_REFER1_BASE VDPU_SWREG(85)
  1934. +#define VDPU_REG_REFER2_BASE VDPU_SWREG(86)
  1935. +#define VDPU_REG_REFER3_BASE VDPU_SWREG(87)
  1936. +#define VDPU_REG_REFER4_BASE VDPU_SWREG(88)
  1937. +#define VDPU_REG_REFER5_BASE VDPU_SWREG(89)
  1938. +#define VDPU_REG_REFER6_BASE VDPU_SWREG(90)
  1939. +#define VDPU_REG_REFER7_BASE VDPU_SWREG(91)
  1940. +#define VDPU_REG_REFER8_BASE VDPU_SWREG(92)
  1941. +#define VDPU_REG_REFER9_BASE VDPU_SWREG(93)
  1942. +#define VDPU_REG_REFER10_BASE VDPU_SWREG(94)
  1943. +#define VDPU_REG_REFER11_BASE VDPU_SWREG(95)
  1944. +#define VDPU_REG_REFER12_BASE VDPU_SWREG(96)
  1945. +#define VDPU_REG_REFER13_BASE VDPU_SWREG(97)
  1946. +#define VDPU_REG_REFER14_BASE VDPU_SWREG(98)
  1947. +#define VDPU_REG_REFER15_BASE VDPU_SWREG(99)
  1948. +#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0)
  1949. +
  1950. +#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0)
  1951. +#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0)
  1952. +#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0)
  1953. +#define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0)
  1954. +#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))
  1955. +
  1956. +#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
  1957. +#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
  1958. +
  1959. +#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))
  1960. +#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))
  1961. +#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))
  1962. +
  1963. +#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))
  1964. +
  1965. +#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0)
  1966. +#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0)
  1967. +#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0)
  1968. +#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0)
  1969. +#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0)
  1970. +#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0)
  1971. +
  1972. +#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0)
  1973. +#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))
  1974. +#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))
  1975. +#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))
  1976. +
  1977. +#define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0)
  1978. +#define VDPU_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(21) : 0)
  1979. +#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0)
  1980. +#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0)
  1981. +#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0)
  1982. +#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0)
  1983. +#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0)
  1984. +#define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0)
  1985. +#define VDPU_REG_PICORD_COUNT_E(v) ((v) ? BIT(6) : 0)
  1986. +#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0)
  1987. +#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0)
  1988. +
  1989. +#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22))
  1990. +#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12))
  1991. +#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2))
  1992. +
  1993. +#define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0)
  1994. +
  1995. +#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25))
  1996. +#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20))
  1997. +#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15))
  1998. +#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10))
  1999. +#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5))
  2000. +#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0))
  2001. +
  2002. +#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25))
  2003. +#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20))
  2004. +#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15))
  2005. +#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10))
  2006. +#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5))
  2007. +#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0))
  2008. +
  2009. +#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2010. +#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2011. +
  2012. +#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2013. +#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2014. +
  2015. +#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2016. +#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2017. +
  2018. +#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2019. +#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2020. +
  2021. +#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2022. +#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2023. +
  2024. +#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2025. +#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2026. +
  2027. +#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2028. +#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2029. +
  2030. +#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16))
  2031. +#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0))
  2032. +
  2033. +#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25))
  2034. +#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20))
  2035. +#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15))
  2036. +#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10))
  2037. +#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5))
  2038. +#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))
  2039. +
  2040. +#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25))
  2041. +#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20))
  2042. +#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15))
  2043. +#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10))
  2044. +#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5))
  2045. +#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0))
  2046. +
  2047. +#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15))
  2048. +#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10))
  2049. +#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5))
  2050. +#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0))
  2051. +
  2052. +#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25))
  2053. +#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20))
  2054. +#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15))
  2055. +#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10))
  2056. +#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5))
  2057. +#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0))
  2058. +
  2059. +#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25))
  2060. +#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20))
  2061. +#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15))
  2062. +#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10))
  2063. +#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5))
  2064. +#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0))
  2065. +
  2066. +#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15))
  2067. +#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10))
  2068. +#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5))
  2069. +#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0))
  2070. +
  2071. +#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15))
  2072. +#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10))
  2073. +#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5))
  2074. +#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))
  2075. +
  2076. +#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0))
  2077. +
  2078. +#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0))
  2079. +
  2080. +#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0))
  2081. +
  2082. +#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22))
  2083. +#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17))
  2084. +#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9))
  2085. +#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0))
  2086. +
  2087. +#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16))
  2088. +#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0))
  2089. +
  2090. +#define VDPU_REG_FILT_CTRL_PRES(v) ((v) ? BIT(31) : 0)
  2091. +#define VDPU_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(30) : 0)
  2092. +#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16))
  2093. +#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0))
  2094. +
  2095. +#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16))
  2096. +#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0))
  2097. +
  2098. +#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24))
  2099. +#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19))
  2100. +#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14))
  2101. +#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0))
  2102. +
  2103. +#define VDPU_REG_IDR_PIC_E(v) ((v) ? BIT(8) : 0)
  2104. +#define VDPU_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(7) : 0)
  2105. +#define VDPU_REG_BLACKWHITE_E(v) ((v) ? BIT(6) : 0)
  2106. +#define VDPU_REG_CABAC_E(v) ((v) ? BIT(5) : 0)
  2107. +#define VDPU_REG_WEIGHT_PRED_E(v) ((v) ? BIT(4) : 0)
  2108. +#define VDPU_REG_CONST_INTRA_E(v) ((v) ? BIT(3) : 0)
  2109. +#define VDPU_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(2) : 0)
  2110. +#define VDPU_REG_TYPE1_QUANT_E(v) ((v) ? BIT(1) : 0)
  2111. +#define VDPU_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0)
  2112. +
  2113. +void rk3399_vpu_h264_dec_run(struct hantro_ctx *ctx)
  2114. +{
  2115. + struct hantro_dev *vpu = ctx->dev;
  2116. + struct vb2_v4l2_buffer *src_buf, *dst_buf;
  2117. + const struct hantro_h264_dec_ctrls *ctrls;
  2118. + const struct v4l2_ctrl_h264_decode_params *decode;
  2119. + const struct v4l2_ctrl_h264_slice_params *slices;
  2120. + const struct v4l2_ctrl_h264_sps *sps;
  2121. + const struct v4l2_ctrl_h264_pps *pps;
  2122. + const u8 *b0_reflist, *b1_reflist, *p_reflist;
  2123. + dma_addr_t addr;
  2124. + size_t offset = 0;
  2125. + u32 reg;
  2126. +
  2127. + /* Prepare the H264 decoder context. */
  2128. + if (hantro_h264_dec_prepare_run(ctx))
  2129. + return;
  2130. +
  2131. + src_buf = hantro_get_src_buf(ctx);
  2132. + dst_buf = hantro_get_dst_buf(ctx);
  2133. +
  2134. + ctrls = &ctx->h264_dec.ctrls;
  2135. + decode = ctrls->decode;
  2136. + slices = ctrls->slices;
  2137. + sps = ctrls->sps;
  2138. + pps = ctrls->pps;
  2139. +
  2140. + b0_reflist = ctx->h264_dec.reflists.b0;
  2141. + b1_reflist = ctx->h264_dec.reflists.b1;
  2142. + p_reflist = ctx->h264_dec.reflists.p;
  2143. +
  2144. + reg = VDPU_REG_DEC_ADV_PRE_DIS(0) |
  2145. + VDPU_REG_DEC_SCMD_DIS(0) |
  2146. + VDPU_REG_FILTERING_DIS(0) |
  2147. + VDPU_REG_PIC_FIXED_QUANT(0) |
  2148. + VDPU_REG_DEC_LATENCY(0);
  2149. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
  2150. +
  2151. + reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) |
  2152. + VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0));
  2153. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
  2154. +
  2155. + reg = VDPU_REG_APF_THRESHOLD(8) |
  2156. + VDPU_REG_STARTMB_X(0) |
  2157. + VDPU_REG_STARTMB_Y(0);
  2158. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
  2159. +
  2160. + reg = VDPU_REG_DEC_MODE(0);
  2161. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
  2162. +
  2163. + reg = VDPU_REG_DEC_STRENDIAN_E(1) |
  2164. + VDPU_REG_DEC_STRSWAP32_E(1) |
  2165. + VDPU_REG_DEC_OUTSWAP32_E(1) |
  2166. + VDPU_REG_DEC_INSWAP32_E(1) |
  2167. + VDPU_REG_DEC_OUT_ENDIAN(1) |
  2168. + VDPU_REG_DEC_IN_ENDIAN(0);
  2169. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
  2170. +
  2171. + reg = VDPU_REG_DEC_DATA_DISC_E(0) |
  2172. + VDPU_REG_DEC_MAX_BURST(16) |
  2173. + VDPU_REG_DEC_AXI_WR_ID(0) |
  2174. + VDPU_REG_DEC_AXI_RD_ID(0xff);
  2175. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
  2176. +
  2177. + reg = VDPU_REG_START_CODE_E(1) |
  2178. + VDPU_REG_CH_8PIX_ILEAV_E(0) |
  2179. + VDPU_REG_RLC_MODE_E(0) |
  2180. + VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC)) |
  2181. + VDPU_REG_PIC_FIELDMODE_E(slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) |
  2182. + VDPU_REG_PIC_TOPFIELD_E(!(slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)) |
  2183. + VDPU_REG_WRITE_MVS_E(sps->profile_idc > 66 && decode->nal_ref_idc) |
  2184. + VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) |
  2185. + VDPU_REG_PICORD_COUNT_E(sps->profile_idc > 66) |
  2186. + VDPU_REG_DEC_TIMEOUT_E(1) |
  2187. + VDPU_REG_DEC_CLK_GATE_E(1);
  2188. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
  2189. +
  2190. + reg = VDPU_REG_PRED_BC_TAP_0_0(1) |
  2191. + VDPU_REG_PRED_BC_TAP_0_1((u32)-5) |
  2192. + VDPU_REG_PRED_BC_TAP_0_2(20);
  2193. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59));
  2194. +
  2195. + reg = VDPU_REG_REFBU_E(0);
  2196. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65));
  2197. +
  2198. + reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) |
  2199. + VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) |
  2200. + VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) |
  2201. + VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) |
  2202. + VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) |
  2203. + VDPU_REG_PINIT_RLIST_F4(p_reflist[4]);
  2204. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74));
  2205. +
  2206. + reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) |
  2207. + VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) |
  2208. + VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) |
  2209. + VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) |
  2210. + VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) |
  2211. + VDPU_REG_PINIT_RLIST_F10(p_reflist[10]);
  2212. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75));
  2213. +
  2214. + reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) |
  2215. + VDPU_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0));
  2216. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76));
  2217. +
  2218. + reg = VDPU_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) |
  2219. + VDPU_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2));
  2220. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77));
  2221. +
  2222. + reg = VDPU_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) |
  2223. + VDPU_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4));
  2224. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78));
  2225. +
  2226. + reg = VDPU_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) |
  2227. + VDPU_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6));
  2228. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79));
  2229. +
  2230. + reg = VDPU_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) |
  2231. + VDPU_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8));
  2232. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80));
  2233. +
  2234. + reg = VDPU_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) |
  2235. + VDPU_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10));
  2236. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81));
  2237. +
  2238. + reg = VDPU_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) |
  2239. + VDPU_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12));
  2240. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82));
  2241. +
  2242. + reg = VDPU_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) |
  2243. + VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14));
  2244. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83));
  2245. +
  2246. + reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) |
  2247. + VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) |
  2248. + VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) |
  2249. + VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) |
  2250. + VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) |
  2251. + VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]);
  2252. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100));
  2253. +
  2254. + reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) |
  2255. + VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) |
  2256. + VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) |
  2257. + VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) |
  2258. + VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) |
  2259. + VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]);
  2260. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101));
  2261. +
  2262. + reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) |
  2263. + VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) |
  2264. + VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) |
  2265. + VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]);
  2266. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102));
  2267. +
  2268. + reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) |
  2269. + VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) |
  2270. + VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) |
  2271. + VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) |
  2272. + VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) |
  2273. + VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]);
  2274. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103));
  2275. +
  2276. + reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) |
  2277. + VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) |
  2278. + VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) |
  2279. + VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) |
  2280. + VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) |
  2281. + VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]);
  2282. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104));
  2283. +
  2284. + reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) |
  2285. + VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) |
  2286. + VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) |
  2287. + VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]);
  2288. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105));
  2289. +
  2290. + reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) |
  2291. + VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) |
  2292. + VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) |
  2293. + VDPU_REG_PINIT_RLIST_F0(p_reflist[0]);
  2294. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106));
  2295. +
  2296. + reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm);
  2297. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107));
  2298. +
  2299. + reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid);
  2300. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108));
  2301. +
  2302. + reg = VDPU_REG_STRM_START_BIT(0);
  2303. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109));
  2304. +
  2305. + reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) |
  2306. + VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) |
  2307. + VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |
  2308. + VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width));
  2309. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110));
  2310. +
  2311. + reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) |
  2312. + VDPU_REG_REF_FRAMES(sps->max_num_ref_frames);
  2313. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111));
  2314. +
  2315. + reg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) |
  2316. + VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) |
  2317. + VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) |
  2318. + VDPU_REG_FRAMENUM(slices[0].frame_num);
  2319. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112));
  2320. +
  2321. + reg = VDPU_REG_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) |
  2322. + VDPU_REG_IDR_PIC_ID(slices[0].idr_pic_id);
  2323. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113));
  2324. +
  2325. + reg = VDPU_REG_PPS_ID(slices[0].pic_parameter_set_id) |
  2326. + VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) |
  2327. + VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) |
  2328. + VDPU_REG_POC_LENGTH(slices[0].pic_order_cnt_bit_size);
  2329. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114));
  2330. +
  2331. + reg = VDPU_REG_IDR_PIC_E(decode->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) |
  2332. + VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) |
  2333. + VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) |
  2334. + VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) |
  2335. + VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) |
  2336. + VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) |
  2337. + VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) |
  2338. + VDPU_REG_TYPE1_QUANT_E(1) |
  2339. + VDPU_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY));
  2340. + vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115));
  2341. +
  2342. + /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */
  2343. + vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE);
  2344. +
  2345. + /* Source (stream) buffer. */
  2346. + addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
  2347. + vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);
  2348. +
  2349. + /* Destination (decoded frame) buffer. */
  2350. + addr = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf);
  2351. + /* Adjust dma addr to start at second line for bottom field */
  2352. + if (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
  2353. + offset = ALIGN(ctx->src_fmt.width, MB_DIM);
  2354. + vdpu_write_relaxed(vpu, addr + offset, VDPU_REG_DEC_OUT_BASE);
  2355. +
  2356. + /* Higher profiles require DMV buffer appended to reference frames. */
  2357. + if (sps->profile_idc > 66 && decode->nal_ref_idc) {
  2358. + unsigned int bytes_per_mb = 384;
  2359. +
  2360. + /* DMV buffer for monochrome start directly after Y-plane */
  2361. + if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0)
  2362. + bytes_per_mb = 256;
  2363. + offset = bytes_per_mb * MB_WIDTH(ctx->src_fmt.width) *
  2364. + MB_HEIGHT(ctx->src_fmt.height);
  2365. +
  2366. + /*
  2367. + * DMV buffer is split in two for field encoded frames,
  2368. + * adjust offset for bottom field
  2369. + */
  2370. + if (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD)
  2371. + offset += 32 * MB_WIDTH(ctx->src_fmt.width) *
  2372. + MB_HEIGHT(ctx->src_fmt.height);
  2373. + vdpu_write_relaxed(vpu, addr + offset, VDPU_REG_DIR_MV_BASE);
  2374. + }
  2375. +
  2376. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 0), VDPU_REG_REFER0_BASE);
  2377. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 1), VDPU_REG_REFER1_BASE);
  2378. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 2), VDPU_REG_REFER2_BASE);
  2379. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 3), VDPU_REG_REFER3_BASE);
  2380. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 4), VDPU_REG_REFER4_BASE);
  2381. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 5), VDPU_REG_REFER5_BASE);
  2382. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 6), VDPU_REG_REFER6_BASE);
  2383. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 7), VDPU_REG_REFER7_BASE);
  2384. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 8), VDPU_REG_REFER8_BASE);
  2385. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 9), VDPU_REG_REFER9_BASE);
  2386. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 10), VDPU_REG_REFER10_BASE);
  2387. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 11), VDPU_REG_REFER11_BASE);
  2388. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 12), VDPU_REG_REFER12_BASE);
  2389. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 13), VDPU_REG_REFER13_BASE);
  2390. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 14), VDPU_REG_REFER14_BASE);
  2391. + vdpu_write_relaxed(vpu, hantro_h264_get_ref_buf(ctx, 15), VDPU_REG_REFER15_BASE);
  2392. +
  2393. + hantro_end_prepare_run(ctx);
  2394. +
  2395. + /* Start decoding! */
  2396. + reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
  2397. + vdpu_write(vpu, reg, VDPU_SWREG(57));
  2398. +}
  2399. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c
  2400. --- linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c 2020-01-26 16:23:03.000000000 -0800
  2401. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c 2020-02-14 22:59:08.117542364 -0800
  2402. @@ -118,7 +118,7 @@
  2403. src_buf = hantro_get_src_buf(ctx);
  2404. dst_buf = hantro_get_dst_buf(ctx);
  2405.  
  2406. - hantro_prepare_run(ctx);
  2407. + hantro_start_prepare_run(ctx);
  2408.  
  2409. memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
  2410. jpeg_ctx.buffer = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
  2411. @@ -156,6 +156,6 @@
  2412. | VEPU_REG_ENCODE_ENABLE;
  2413.  
  2414. /* Kick the watchdog and start encoding */
  2415. - hantro_finish_run(ctx);
  2416. + hantro_end_prepare_run(ctx);
  2417. vepu_write(vpu, reg, VEPU_REG_ENCODE_START);
  2418. }
  2419. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c
  2420. --- linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c 2020-01-26 16:23:03.000000000 -0800
  2421. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c 2020-02-14 22:59:08.117542364 -0800
  2422. @@ -127,7 +127,7 @@
  2423. current_addr = addr;
  2424.  
  2425. if (picture->picture_structure == PICT_BOTTOM_FIELD)
  2426. - addr += ALIGN(ctx->dst_fmt.width, 16);
  2427. + addr += ALIGN(ctx->src_fmt.width, MB_DIM);
  2428. vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);
  2429.  
  2430. if (!forward_addr)
  2431. @@ -169,7 +169,7 @@
  2432. src_buf = hantro_get_src_buf(ctx);
  2433. dst_buf = hantro_get_dst_buf(ctx);
  2434.  
  2435. - hantro_prepare_run(ctx);
  2436. + hantro_start_prepare_run(ctx);
  2437.  
  2438. slice_params = hantro_get_ctrl(ctx,
  2439. V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
  2440. @@ -220,8 +220,8 @@
  2441. VDPU_REG_DEC_CLK_GATE_E(1);
  2442. vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
  2443.  
  2444. - reg = VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->dst_fmt.width)) |
  2445. - VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->dst_fmt.height)) |
  2446. + reg = VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)) |
  2447. + VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) |
  2448. VDPU_REG_ALT_SCAN_E(picture->alternate_scan) |
  2449. VDPU_REG_TOPFIELDFIRST_E(picture->top_field_first);
  2450. vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));
  2451. @@ -250,7 +250,7 @@
  2452. sequence, picture, slice_params);
  2453.  
  2454. /* Kick the watchdog and start decoding */
  2455. - hantro_finish_run(ctx);
  2456. + hantro_end_prepare_run(ctx);
  2457.  
  2458. reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
  2459. vdpu_write(vpu, reg, VDPU_SWREG(57));
  2460. diff -uNr '--exclude=.git' linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c
  2461. --- linux-5.5/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c 2020-01-26 16:23:03.000000000 -0800
  2462. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c 2020-02-14 22:59:08.117542364 -0800
  2463. @@ -508,12 +508,12 @@
  2464. {
  2465. const struct v4l2_ctrl_vp8_frame_header *hdr;
  2466. struct hantro_dev *vpu = ctx->dev;
  2467. - size_t height = ctx->dst_fmt.height;
  2468. - size_t width = ctx->dst_fmt.width;
  2469. + size_t height = ctx->src_fmt.height;
  2470. + size_t width = ctx->src_fmt.width;
  2471. u32 mb_width, mb_height;
  2472. u32 reg;
  2473.  
  2474. - hantro_prepare_run(ctx);
  2475. + hantro_start_prepare_run(ctx);
  2476.  
  2477. hdr = hantro_get_ctrl(ctx, V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER);
  2478. if (WARN_ON(!hdr))
  2479. @@ -587,7 +587,7 @@
  2480. cfg_ref(ctx, hdr);
  2481. cfg_buffers(ctx, hdr);
  2482.  
  2483. - hantro_finish_run(ctx);
  2484. + hantro_end_prepare_run(ctx);
  2485.  
  2486. hantro_reg_write(vpu, &vp8_dec_start_dec, 1);
  2487. }
  2488. diff -uNr '--exclude=.git' linux-5.5/include/media/h264-ctrls.h linux-rockchip-v4l2-5.5-work-in-progress-v5.5/include/media/h264-ctrls.h
  2489. --- linux-5.5/include/media/h264-ctrls.h 2020-01-26 16:23:03.000000000 -0800
  2490. +++ linux-rockchip-v4l2-5.5-work-in-progress-v5.5/include/media/h264-ctrls.h 2020-02-14 22:59:09.069549210 -0800
  2491. @@ -185,6 +185,10 @@
  2492. #define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01
  2493. #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02
  2494. #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04
  2495. +#define V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE 0x08
  2496. +#define V4L2_H264_DPB_ENTRY_FLAG_REF_TOP 0x10
  2497. +#define V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM 0x20
  2498. +#define V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME 0x30
  2499.  
  2500. struct v4l2_h264_dpb_entry {
  2501. __u64 reference_ts;
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