library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.all;



entity cpu is
    Port (
    clk : in STD_LOGIC;
    update : in STD_LOGIC;
    ax : in STD_LOGIC_VECTOR(3 downto 0);
    opcode : in STD_LOGIC_VECTOR(3 downto 0);
    result_add : in STD_LOGIC_VECTOR(4 downto 0);
    result_mult : in STD_LOGIC_VECTOR(7 downto 0);
    result_not : in STD_LOGIC_VECTOR(3 downto 0);
    result_and : in STD_LOGIC_VECTOR(3 downto 0);
    result_or : in STD_LOGIC_VECTOR(3 downto 0);
    A : out STD_LOGIC_VECTOR(3 downto 0);
    B : out STD_LOGIC_VECTOR(3 downto 0);
    C : out STD_LOGIC_VECTOR(3 downto 0);
    D : out STD_LOGIC_VECTOR(3 downto 0);
    op_in1 : out STD_LOGIC_VECTOR(3 downto 0);
    op_in2 : out STD_LOGIC_VECTOR(3 downto 0) );
end cpu;

architecture Behavioral of cpu is

    signal BX, CX, DX : std_logic_vector(3 downto 0);
begin

    process(clk)

    begin

    if clk='1' AND clk'event then

    case opcode is
        when "0000" => BX <= AX;
        when "0001" => CX <= AX;
        when "0010" => DX <= AX;
        when "0011" => BX <= "0000";
        when "0100" => CX <= "0000";
        when "0101" => DX <= "0000";
        when "0110" =>
            CX <= result_add,
            DX <= "0101";
        when "0111" =>
            CX <= result_mult,
            DX <= "0110";
        when "1000" =>
            CX <= result_not,
            DX <= "1101";
        when "1001" =>
            CX <= result_and,
            DX <= "0010";
        when "1010" =>
            CX <= result_or,
            DX <= "0011";
        when "1011" =>
            DX <= "000"&(bit4),
            CX <= LSB4;
        when "1100" =>
            DX <= MSB4,
            CX <= LSB4;
        when "1101" => CX <= NOT(AX);
        DX <= "0000";
        when "1110" => CX <= AX AND BX;
        DX <= "0000";
        when "1111" => CX <= AX OR BX;
        DX <= "0000";
    end case;
    end if;
    end process;


end Behavioral;